| timestamp 1641008000 |
| version 8.3 |
| tech sky130A |
| style ngspice() |
| scale 1000 1 500000 |
| resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 |
| use tspc tspc_0 1 0 650 0 1 590 |
| use tspc tspc_1 1 0 2210 0 1 590 |
| use tspc tspc_2 -1 0 1870 0 -1 2450 |
| use nand nand_0 1 0 -110 0 1 540 |
| use nand nand_1 -1 0 2650 0 -1 2100 |
| node "m4_1970_n370#" 0 75.68 1970 -370 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8400 400 0 0 0 0 |
| node "GND" 0 190.26 390 -370 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26300 1000 0 0 0 0 |
| node "m4_2730_1520#" 1 323.98 2730 1520 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49200 1760 0 0 0 0 |
| node "VDD" 0 85.656 1980 1460 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20400 580 0 0 0 0 |
| node "m4_350_1060#" 0 252.457 350 1060 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62400 1480 0 0 0 0 |
| node "GND" 3 1703 2600 2660 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 265800 8980 0 0 0 0 |
| node "GND" 1 378.84 1930 3350 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62700 1980 0 0 0 0 |
| node "clk" 3 379.35 -420 460 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37200 1940 0 0 0 0 0 0 0 0 |
| node "m2_970_460#" 12 1208.72 970 460 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 106400 6440 0 0 0 0 0 0 0 0 |
| node "m1_2700_2190#" 12 1187.47 2700 2190 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84000 5660 0 0 0 0 0 0 0 0 0 0 |
| node "Out" 19 846.75 2120 280 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 6400 320 60100 3740 0 0 0 0 0 0 0 0 |
| node "li_3590_420#" 125 2264.03 3590 420 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15000 820 21300 1120 178400 8640 0 0 0 0 0 0 0 0 |
| node "li_2030_420#" 66 157.38 2030 420 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9600 540 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "li_450_280#" 76 168.75 450 280 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10000 580 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "mc1" 150 2026.91 2700 2270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17600 960 102600 6560 30100 1740 0 0 0 0 0 0 0 0 |
| node "li_1980_2130#" 199 398.912 1980 2130 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26700 1400 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "li_n310_330#" 210 1594.32 -310 330 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23700 1320 90500 5720 0 0 0 0 0 0 0 0 0 0 |
| node "w_390_530#" 14707 435.372 390 530 nw 0 0 0 0 145124 2500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "w_1930_2072#" 27928 716.916 1930 2072 nw 0 0 0 0 238972 4204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| cap "Out" "GND" 27.9 |
| cap "w_1930_2072#" "VDD" 1.964 |
| cap "li_3590_420#" "clk" 168.462 |
| cap "li_3590_420#" "m2_970_460#" 183.333 |
| cap "Out" "m1_2700_2190#" 27.465 |
| cap "li_3590_420#" "m1_2700_2190#" 23.5 |
| cap "li_2030_420#" "m2_970_460#" 17.38 |
| cap "li_450_280#" "clk" 28.72 |
| cap "li_3590_420#" "Out" 716.418 |
| cap "w_1930_2072#" "m2_970_460#" 42.9324 |
| cap "li_2030_420#" "Out" 197.97 |
| cap "mc1" "m4_2730_1520#" 23.175 |
| cap "mc1" "VDD" 41.675 |
| cap "mc1" "m4_350_1060#" 84.575 |
| cap "w_390_530#" "m4_350_1060#" 2.9032 |
| cap "mc1" "m2_970_460#" 37.515 |
| cap "li_n310_330#" "clk" 28.72 |
| cap "mc1" "m1_2700_2190#" 63.2343 |
| cap "li_1980_2130#" "m2_970_460#" 138.025 |
| cap "li_n310_330#" "li_3590_420#" 92.2845 |
| cap "w_1930_2072#" "mc1" 2.7456 |
| cap "w_1930_2072#" "li_1980_2130#" 10.7855 |
| cap "li_n310_330#" "mc1" 37.515 |
| cap "GND" "m4_2730_1520#" 23.6471 |
| cap "m2_970_460#" "VDD" 42 |
| cap "tspc_0/D" "nand_0/a_280_n230#" 165.278 |
| cap "tspc_0/a_300_n150#" "nand_0/A" 17.42 |
| cap "tspc_0/D" "tspc_0/vdd!" 45.9643 |
| cap "tspc_0/D" "nand_0/A" 29.5549 |
| cap "tspc_0/D" "tspc_0/a_300_n150#" 127.12 |
| cap "nand_0/a_280_n230#" "tspc_0/Z4" 106.442 |
| cap "nand_0/a_280_n230#" "tspc_0/GND" 124.422 |
| cap "nand_0/a_280_n230#" "nand_0/z1" 153.26 |
| cap "nand_0/a_280_n230#" "tspc_0/Z3" 75.9225 |
| cap "nand_0/a_280_n230#" "tspc_0/Z2" 56.16 |
| cap "tspc_0/D" "tspc_0/Z4" 12.3811 |
| cap "tspc_0/D" "nand_0/z1" 2.11538 |
| cap "nand_0/A" "nand_0/vdd!" 44.8462 |
| cap "nand_0/A" "nand_0/a_280_n230#" 13.02 |
| cap "tspc_0/a_300_n150#" "nand_0/a_280_n230#" 94.1074 |
| cap "tspc_0/a_740_n680#" "tspc_0/Q" 32.1861 |
| cap "tspc_0/a_740_n680#" "tspc_0/a_300_n150#" 129.16 |
| cap "tspc_1/Z4" "li_3590_420#" 55.1 |
| cap "tspc_0/GND" "li_3590_420#" 198.939 |
| cap "tspc_0/Z4" "li_3590_420#" 107.677 |
| cap "tspc_1/Z2" "li_3590_420#" 43.32 |
| cap "tspc_0/GND" "tspc_0/a_630_n680#" 17.3347 |
| cap "tspc_0/Q" "li_3590_420#" 142.71 |
| cap "tspc_1/Z2" "tspc_0/GND" 16.9342 |
| cap "tspc_0/Q" "tspc_1/Z3" 3.50402 |
| cap "tspc_0/Q" "tspc_1/Z4" 102.17 |
| cap "tspc_0/Z3" "li_3590_420#" 57.62 |
| cap "tspc_0/Q" "tspc_0/GND" 51.0882 |
| cap "tspc_0/a_300_n150#" "li_3590_420#" 83.0378 |
| cap "tspc_0/Q" "tspc_1/Z1" 39.5832 |
| cap "tspc_0/Q" "tspc_1/Z2" 85.89 |
| cap "tspc_0/a_740_n680#" "li_3590_420#" 150.46 |
| cap "tspc_0/Q" "tspc_1/vdd!" 59.1194 |
| cap "tspc_0/a_740_n680#" "tspc_1/Z4" 4.09091 |
| cap "tspc_0/a_740_n680#" "tspc_1/Z2" 5.4 |
| cap "tspc_0/a_300_n150#" "tspc_0/Q" 177.533 |
| cap "tspc_0/vdd!" "tspc_1/vdd!" 38.2105 |
| cap "tspc_0/a_300_n150#" "tspc_0/Z3" 198.42 |
| cap "tspc_1/Q" "tspc_1/Z4" 104.585 |
| cap "tspc_1/Z3" "tspc_1/Q" 156.507 |
| cap "tspc_1/Z2" "tspc_1/Q" 12.84 |
| cap "tspc_0/Q" "tspc_1/GND" 39.1 |
| cap "tspc_0/Q" "tspc_1/Z4" 78.2567 |
| cap "tspc_1/a_300_n150#" "tspc_1/Q" 68.7785 |
| cap "tspc_0/Q" "tspc_1/Q" 50.6 |
| cap "tspc_0/Q" "tspc_1/Z3" 59.529 |
| cap "tspc_1/a_740_n680#" "tspc_1/Q" 175.043 |
| cap "tspc_0/Q" "tspc_1/Z2" 9.99 |
| cap "tspc_0/Q" "tspc_1/a_300_n150#" 179.587 |
| cap "tspc_1/a_740_n680#" "tspc_0/Q" 82.65 |
| cap "tspc_1/Z4" "tspc_0/a_740_n680#" 1.92857 |
| cap "tspc_1/Q" "tspc_1/GND" 218.86 |
| cap "tspc_0/vdd!" "mc1" 162.542 |
| cap "tspc_0/vdd!" "tspc_0/Z2" 10 |
| cap "tspc_2/Q" "tspc_0/vdd!" 32.5248 |
| cap "tspc_0/w_n140_n70#" "tspc_0/vdd!" -3.656 |
| cap "tspc_0/Z2" "mc1" 46.8 |
| cap "tspc_0/w_n140_n70#" "mc1" 9.165 |
| cap "tspc_2/D" "nand_1/z1" 6 |
| cap "tspc_0/vdd!" "tspc_2/Z2" 10 |
| cap "tspc_2/D" "tspc_2/Z1" 99.6765 |
| cap "nand_1/a_280_n230#" "tspc_0/vdd!" 7.33333 |
| cap "tspc_2/D" "tspc_0/vdd!" 272.242 |
| cap "tspc_2/w_n140_n70#" "tspc_2/a_300_n150#" 2.0976 |
| cap "tspc_2/D" "nand_1/a_280_n230#" 9.77778 |
| cap "tspc_2/a_300_n150#" "tspc_0/vdd!" 166.667 |
| cap "tspc_1/Z2" "mc1" 18 |
| cap "tspc_2/a_300_n150#" "tspc_2/D" -6.9 |
| cap "tspc_0/Q" "tspc_1/Z1" 10.4211 |
| cap "tspc_0/Z2" "mc1" 17.4522 |
| cap "tspc_2/w_n140_n70#" "mc1" 24.5544 |
| cap "tspc_0/vdd!" "mc1" 414.897 |
| cap "tspc_2/Z2" "mc1" 53.3571 |
| cap "tspc_0/vdd!" "tspc_1/Z2" 4.35484 |
| cap "tspc_0/vdd!" "tspc_0/Q" 44.0676 |
| cap "tspc_2/w_n140_n70#" "tspc_0/vdd!" -11.884 |
| cap "tspc_2/w_n140_n70#" "tspc_2/D" 8.1659 |
| cap "nand_1/a_280_n230#" "tspc_1/a_740_n680#" 1.36364 |
| cap "nand_1/GND" "tspc_1/vdd!" 39.5155 |
| cap "nand_1/A" "tspc_1/vdd!" 227.695 |
| cap "nand_1/OUT" "nand_1/z1" 1.83333 |
| cap "nand_1/A" "nand_1/OUT" 22.3793 |
| cap "tspc_1/vdd!" "tspc_2/a_300_n150#" 1.38889 |
| cap "tspc_1/vdd!" "tspc_1/Z2" 11.9132 |
| cap "nand_1/a_280_n230#" "tspc_1/vdd!" 13.125 |
| cap "tspc_2/w_n140_n70#" "tspc_1/vdd!" -6.44 |
| cap "nand_1/A" "tspc_1/Z2" 46.2522 |
| cap "tspc_2/w_n140_n70#" "nand_1/A" 9.555 |
| cap "tspc_2/Q" "tspc_2/a_740_n680#" 18.4737 |
| cap "tspc_2/D" "nand_1/z1" 14 |
| cap "tspc_2/D" "tspc_2/vdd!" 47.4 |
| cap "tspc_2/D" "tspc_2/Z1" 20.5588 |
| cap "tspc_2/D" "tspc_2/Z4" 7.71692 |
| cap "tspc_2/a_300_n150#" "tspc_2/D" 0.18 |
| cap "tspc_2/Z3" "tspc_2/D" 5.25747 |
| cap "tspc_2/w_n140_n70#" "tspc_2/D" 3.0525 |
| cap "nand_1/OUT" "nand_1/z1" 2.75 |
| merge "tspc_2/gnd!" "tspc_2/GND" -681.99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -218700 -3450 0 0 0 0 |
| merge "tspc_2/GND" "nand_1/GND" |
| merge "nand_1/GND" "tspc_1/GND" |
| merge "tspc_1/GND" "tspc_1/gnd!" |
| merge "tspc_1/gnd!" "nand_0/GND" |
| merge "nand_0/GND" "m4_1970_n370#" |
| merge "m4_1970_n370#" "tspc_0/GND" |
| merge "tspc_0/GND" "GND" |
| merge "nand_1/VSUBS" "tspc_2/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| merge "tspc_2/VSUBS" "tspc_1/VSUBS" |
| merge "tspc_1/VSUBS" "nand_0/VSUBS" |
| merge "nand_0/VSUBS" "tspc_0/VSUBS" |
| merge "tspc_0/VSUBS" "VSUBS" |
| merge "nand_1/VDD" "tspc_2/w_n140_n70#" 790.044 0 0 0 0 263348 -15264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| merge "tspc_2/w_n140_n70#" "tspc_1/w_n140_n70#" |
| merge "tspc_1/w_n140_n70#" "nand_0/VDD" |
| merge "nand_0/VDD" "w_1930_2072#" |
| merge "w_1930_2072#" "tspc_0/w_n140_n70#" |
| merge "tspc_0/w_n140_n70#" "w_390_530#" |
| merge "nand_1/vdd!" "tspc_1/vdd!" -1180.25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 -7520 0 0 0 0 |
| merge "tspc_1/vdd!" "m4_2730_1520#" |
| merge "m4_2730_1520#" "tspc_2/vdd!" |
| merge "tspc_2/vdd!" "VDD" |
| merge "VDD" "tspc_0/vdd!" |
| merge "tspc_0/vdd!" "nand_0/vdd!" |
| merge "nand_0/vdd!" "m4_350_1060#" |
| merge "tspc_2/a_300_n150#" "tspc_1/a_300_n150#" -475.331 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21000 -500 0 0 0 0 0 0 0 0 |
| merge "tspc_1/a_300_n150#" "tspc_0/a_300_n150#" |
| merge "tspc_0/a_300_n150#" "clk" |
| merge "clk" "m2_970_460#" |
| merge "nand_1/a_280_n230#" "tspc_1/a_740_n680#" 110.67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 244300 -180 0 0 0 0 0 0 0 0 0 0 |
| merge "tspc_1/a_740_n680#" "m1_2700_2190#" |
| merge "tspc_2/Q" "nand_0/A" -49.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -180 0 0 0 0 0 0 0 0 0 0 0 0 |
| merge "nand_0/A" "li_n310_330#" |
| merge "tspc_1/Q" "nand_0/a_280_n230#" -1482.29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9500 -100 0 -60 -56000 -2800 0 0 0 0 0 0 0 0 |
| merge "nand_0/a_280_n230#" "li_3590_420#" |
| merge "nand_0/OUT" "tspc_0/D" -73.35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2000 -260 0 0 0 0 0 0 0 0 0 0 0 0 |
| merge "tspc_0/D" "li_450_280#" |
| merge "nand_1/A" "mc1" -647.869 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -19200 -80 -42000 -2800 0 0 0 0 0 0 0 0 0 0 |
| merge "nand_1/OUT" "tspc_2/D" -125.318 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -52000 -240 0 0 0 0 0 0 0 0 0 0 0 0 |
| merge "tspc_2/D" "li_1980_2130#" |
| merge "tspc_1/D" "Out" -470.9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14700 -420 0 0 -2400 -190 0 0 0 0 0 0 0 0 |
| merge "Out" "tspc_0/Q" |
| merge "tspc_0/Q" "li_2030_420#" |
