| timestamp 1640958486 |
| version 8.3 |
| tech sky130A |
| style ngspice() |
| scale 1000 1 500000 |
| resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 |
| use and_pd and_pd_0 1 0 2200 0 1 790 |
| use tspc_r tspc_r_0 1 0 290 0 1 760 |
| use tspc_r tspc_r_1 1 0 290 0 -1 -850 |
| node "GND" 1 842.66 20 -130 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 343400 4380 0 0 0 0 |
| node "m4_1440_1280#" 0 173.9 1440 1280 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24600 940 0 0 0 0 |
| node "DIV" 1 109.532 -230 -910 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6900 520 0 0 0 0 0 0 0 0 |
| node "REF" 1 109.532 -230 790 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6900 520 0 0 0 0 0 0 0 0 |
| node "UP" 2 244.23 2400 670 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16200 1140 0 0 0 0 0 0 0 0 0 0 |
| node "m1_2010_600#" 1 81.02 2010 600 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4800 380 0 0 0 0 0 0 0 0 0 0 |
| node "R" 26 1557.5 2870 560 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 6400 320 114700 7100 0 0 0 0 0 0 0 0 |
| node "DOWN" 22 1071.98 2160 560 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 73300 4780 0 0 0 0 0 0 0 0 0 0 |
| node "VDD" 76 1895.43 60 -770 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3200 320 12800 640 16400 720 20000 800 213800 7140 0 0 0 0 |
| node "w_0_n1460#" 18910 2199.75 0 -1460 nw 0 0 0 0 662500 5900 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 45800 1300 0 0 0 0 |
| node "VDD" 27087 2548.65 0 1160 nw 0 0 0 0 793200 7540 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 37400 1040 0 0 0 0 |
| substrate "a_n420_n1430#" 0 0 -420 -1430 ppd 0 0 0 0 0 0 0 0 0 0 486400 12160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2463100 27820 0 0 0 0 0 0 0 0 0 0 0 0 |
| cap "VDD" "UP" 7.2 |
| cap "VDD" "R" 11.2838 |
| cap "m1_2010_600#" "UP" 4.5 |
| cap "R" "UP" 72 |
| cap "DOWN" "UP" 101.25 |
| cap "DOWN" "m1_2010_600#" 41.625 |
| cap "DOWN" "R" 185.417 |
| cap "w_0_n1460#" "VDD" 0.48 |
| cap "VDD" "GND" 113.9 |
| cap "VDD" "DIV" 27.9 |
| cap "VDD" "VDD" 0.48 |
| cap "VDD" "REF" 27.9 |
| cap "R" "GND" 53.75 |
| cap "DOWN" "GND" 50.15 |
| cap "VDD" "m4_1440_1280#" 4.92 |
| cap "tspc_r_1/w_n290_n40#" "tspc_r_1/Z2" 12.775 |
| cap "tspc_r_1/w_n290_n40#" "tspc_r_1/VDD" 33.74 |
| cap "tspc_r_1/R" "tspc_r_1/Z3" 11.355 |
| cap "tspc_r_1/VDD" "tspc_r_1/Z2" 72 |
| cap "tspc_r_0/GND" "tspc_r_1/VDD" 99.8267 |
| cap "tspc_r_0/GND" "tspc_r_1/Z2" 9.69375 |
| cap "tspc_r_1/Z1" "tspc_r_0/GND" 14.4375 |
| cap "tspc_r_1/Z3" "tspc_r_1/VDD" 10.9091 |
| cap "tspc_r_1/Z3" "tspc_r_0/GND" 7.21875 |
| cap "tspc_r_1/clk" "tspc_r_1/VDD" 62.5 |
| cap "tspc_r_1/R" "tspc_r_1/VDD" 100 |
| cap "tspc_r_1/VDD" "tspc_r_1/Qbar1" 5.68434e-14 |
| cap "tspc_r_1/VDD" "a_n420_n1430#" 45.2812 |
| cap "tspc_r_1/Q" "a_n420_n1430#" 7.21875 |
| cap "a_n420_n1430#" "tspc_r_1/Qbar" 7.21875 |
| cap "a_n420_n1430#" "tspc_r_1/Qbar1" 7.21875 |
| cap "tspc_r_1/R" "tspc_r_1/Z3" 126.785 |
| cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 30.4615 |
| cap "tspc_r_0/Z4" "tspc_r_1/Z4" 19.4595 |
| cap "tspc_r_0/GND" "tspc_r_1/Z4" 13.3333 |
| cap "tspc_r_0/Z3" "tspc_r_0/R" 13.31 |
| cap "tspc_r_0/GND" "tspc_r_0/Z4" 13.3333 |
| cap "tspc_r_0/VDD" "tspc_r_0/R" 66.6667 |
| cap "tspc_r_0/GND" "tspc_r_0/R" 64.2857 |
| cap "tspc_r_0/VDD" "tspc_r_0/Z2" 72 |
| cap "tspc_r_0/VDD" "tspc_r_0/Z3" 10.9091 |
| cap "tspc_r_0/VDD" "tspc_r_0/clk" 44.4444 |
| cap "tspc_r_0/GND" "tspc_r_0/VDD" 150.325 |
| cap "tspc_r_1/z5" "and_pd_0/GND" 13.3333 |
| cap "and_pd_0/B" "tspc_r_0/R" 150.845 |
| cap "tspc_r_0/R" "and_pd_0/GND" 145.652 |
| cap "tspc_r_0/z5" "tspc_r_1/z5" 19.4595 |
| cap "tspc_r_0/Qbar1" "tspc_r_0/R" 287.105 |
| cap "tspc_r_0/Qbar" "and_pd_0/GND" 44.4044 |
| cap "tspc_r_0/Z3" "tspc_r_0/R" 143.15 |
| cap "tspc_r_0/clk" "tspc_r_0/R" 103.99 |
| cap "tspc_r_0/z5" "and_pd_0/GND" 13.3333 |
| cap "tspc_r_0/Qbar" "tspc_r_0/R" 31.025 |
| cap "and_pd_0/a_n60_n30#" "and_pd_0/GND" 1.77636e-15 |
| cap "and_pd_0/B" "and_pd_0/Out1" -14.35 |
| cap "and_pd_0/B" "and_pd_0/A" 183.938 |
| cap "and_pd_0/A" "and_pd_0/GND" 308.57 |
| cap "and_pd_0/Z1" "tspc_r_0/Qbar" 21.0517 |
| cap "and_pd_0/a_n60_n30#" "tspc_r_0/Qbar" 68.0625 |
| cap "and_pd_0/Out1" "tspc_r_0/Qbar" 47.6929 |
| cap "and_pd_0/A" "tspc_r_0/R" 86.5 |
| cap "and_pd_0/Z1" "and_pd_0/A" 85 |
| cap "and_pd_0/A" "tspc_r_0/Qbar" 17.9186 |
| cap "and_pd_0/Z1" "and_pd_0/A" -23.46 |
| cap "and_pd_0/Out" "and_pd_0/Out1" 137.14 |
| cap "and_pd_0/GND" "and_pd_0/A" 113.28 |
| cap "and_pd_0/Out" "and_pd_0/B" 222.129 |
| cap "and_pd_0/Out" "and_pd_0/A" 90.78 |
| cap "and_pd_0/Z1" "a_n420_n1430#" 0.916667 |
| cap "and_pd_0/GND" "a_n420_n1430#" 9.20833 |
| cap "and_pd_0/Out" "a_n420_n1430#" 72.7883 |
| cap "and_pd_0/Out" "and_pd_0/VDD" 56.5714 |
| cap "and_pd_0/Out" "and_pd_0/GND" 16.129 |
| cap "tspc_r_0/Qbar" "and_pd_0/Z1" 1.69231 |
| cap "and_pd_0/A" "and_pd_0/Out1" 105.892 |
| cap "and_pd_0/B" "and_pd_0/Out1" 70.6975 |
| cap "and_pd_0/VDD" "and_pd_0/Out1" 12.375 |
| cap "and_pd_0/A" "and_pd_0/B" 58.428 |
| cap "a_n420_n1430#" "and_pd_0/Out1" 6.41667 |
| cap "and_pd_0/VDD" "and_pd_0/B" 2.66454e-15 |
| cap "tspc_r_0/w_n290_n40#" "tspc_r_0/Z2" 12.775 |
| cap "a_n420_n1430#" "tspc_r_0/Z1" 14.4375 |
| cap "a_n420_n1430#" "tspc_r_0/Z2" 9.69375 |
| cap "tspc_r_0/w_n290_n40#" "tspc_r_0/VDD" 33.74 |
| cap "a_n420_n1430#" "tspc_r_0/VDD" 56.7013 |
| cap "a_n420_n1430#" "tspc_r_0/Z3" 7.21875 |
| cap "tspc_r_0/Q" "a_n420_n1430#" 7.21875 |
| cap "tspc_r_0/Qbar1" "a_n420_n1430#" 7.21875 |
| cap "and_pd_0/a_n60_n30#" "a_n420_n1430#" 54.6607 |
| cap "and_pd_0/a_n60_n30#" "and_pd_0/VDD" 43.07 |
| cap "tspc_r_0/Qbar" "and_pd_0/Out1" 3.53571 |
| cap "and_pd_0/a_n60_n30#" "tspc_r_0/Qbar" 6.1875 |
| cap "tspc_r_0/Q" "and_pd_0/A" 2.15625 |
| cap "and_pd_0/Out1" "a_n420_n1430#" 7.21875 |
| cap "tspc_r_0/Qbar" "a_n420_n1430#" 7.21875 |
| cap "a_n420_n1430#" "and_pd_0/VDD" 18.7589 |
| cap "a_n420_n1430#" "and_pd_0/Out" 9.96875 |
| cap "a_n420_n1430#" "and_pd_0/Out1" 7.21875 |
| merge "and_pd_0/VSUBS" "and_pd_0/GND" -6351.75 0 0 0 0 0 0 0 0 0 0 -55010 -7926 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 572500 -19033 0 0 0 0 0 0 -601300 -9300 0 0 0 0 |
| merge "and_pd_0/GND" "tspc_r_1/VSUBS" |
| merge "tspc_r_1/VSUBS" "tspc_r_1/GND" |
| merge "tspc_r_1/GND" "tspc_r_0/VSUBS" |
| merge "tspc_r_0/VSUBS" "tspc_r_0/GND" |
| merge "tspc_r_0/GND" "GND" |
| merge "GND" "a_n420_n1430#" |
| merge "tspc_r_0/Q" "and_pd_0/B" -198.16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -84600 -320 0 0 0 0 0 0 0 0 0 0 |
| merge "and_pd_0/B" "UP" |
| merge "UP" "m1_2010_600#" |
| merge "and_pd_0/VDD" "and_pd_0/a_n60_n30#" 240.86 0 0 0 0 325700 -10800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3200 -320 32000 0 39000 0 79000 0 83100 -1940 0 0 0 0 |
| merge "and_pd_0/a_n60_n30#" "m4_1440_1280#" |
| merge "m4_1440_1280#" "tspc_r_0/VDD" |
| merge "tspc_r_0/VDD" "tspc_r_0/D" |
| merge "tspc_r_0/D" "tspc_r_0/w_n290_n40#" |
| merge "tspc_r_0/w_n290_n40#" "tspc_r_1/VDD" |
| merge "tspc_r_1/VDD" "tspc_r_1/w_n290_n40#" |
| merge "tspc_r_1/w_n290_n40#" "w_0_n1460#" |
| merge "w_0_n1460#" "tspc_r_1/D" |
| merge "tspc_r_1/D" "VDD" |
| merge "and_pd_0/Out" "tspc_r_0/R" -951.542 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -80 0 0 25100 -460 0 0 0 0 0 0 0 0 |
| merge "tspc_r_0/R" "tspc_r_1/R" |
| merge "tspc_r_1/R" "R" |
| merge "tspc_r_1/clk" "DIV" -12.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -60 0 0 0 0 0 0 0 0 |
| merge "tspc_r_0/clk" "REF" -12.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -60 0 0 0 0 0 0 0 0 |
| merge "and_pd_0/A" "tspc_r_1/Q" -456.84 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5200 -160 -12900 -60 0 0 0 0 0 0 0 0 0 0 |
| merge "tspc_r_1/Q" "DOWN" |
