Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-004
/
slot-016
/
9c5f04485114434c4ade81bce7d5ef873f07e536
commit
9c5f04485114434c4ade81bce7d5ef873f07e536
[
log
]
[
tgz
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author
roman3017 <rbacik@hotmail.com>
Sun Dec 26 23:49:51 2021 -0800
committer
roman3017 <rbacik@hotmail.com>
Sun Dec 26 23:49:51 2021 -0800
tree
77e6e2d0ef6be8dded1c360685cad626fa2d8aa5
parent
d90d2ed77269b67da9ceeb09dbf373d81ffaaee1
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diff
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update dv tests
openlane/user_proj/src/simpleuart.v
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openlane/user_proj/src/soc.v
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openlane/user_proj/src/wb_interconnect.v
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openlane/user_proj/src/wb_interconnect.vh
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openlane/user_proj/src/wb_led.v
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openlane/user_project_wrapper/config.tcl
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verilog/dv/Makefile
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verilog/dv/io_ports/Makefile
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verilog/dv/io_ports/io_ports_tb.v
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verilog/dv/la_test1/Makefile
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verilog/dv/la_test1/la_test1_tb.v
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verilog/dv/la_test2/Makefile
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verilog/dv/la_test2/la_test2_tb.v
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verilog/dv/mprj_stimulus/Makefile
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verilog/dv/mprj_stimulus/mprj_stimulus.c
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verilog/dv/wb_leds/.gitignore
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verilog/dv/wb_leds/Makefile
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verilog/dv/wb_leds/wb_leds.c
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verilog/dv/wb_leds/wb_leds_tb.v
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verilog/dv/wb_port/Makefile
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verilog/dv/wb_port/wb_port_tb.v
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verilog/rtl/uprj_netlists.v
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verilog/rtl/user_project_wrapper.v
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23 files changed
tree: 77e6e2d0ef6be8dded1c360685cad626fa2d8aa5
.github/
def/
docs/
gds/
lef/
lib/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
LICENSE
Makefile
README.md
README.md
Caravel User Project
Refer to
README
for this sample project documentation.
