| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/local/caravel_user_project/openlane/user_proj,user_proj,user_proj,flow_completed,0h33m14s,-1,94005.88046170225,0.685489032,32902.058161595785,35.8,1467.11,22554,0,-1,-1,-1,-1,0,0,-1,0,0,-1,1516741,225409,-4.85,-8.13,-1,-5.96,-1,-1562.19,-3487.83,-1,-904.94,-1,966921004.0,9.18,61.41,60.64,41.23,30.82,-1,18748,36149,1381,18622,0,0,0,21282,0,0,0,0,0,0,0,4,3731,3861,55,596,9300,0,9896,90.9090909090909,11,10,AREA 0,4,35,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,4,4 |
