| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/local/caravel_user_project/openlane/user_proj,user_proj,user_proj,flow_completed,0h36m48s,-1,94671.15992957851,0.687643418,33134.90597535248,35.86,1483.32,22785,0,-1,-1,-1,-1,0,0,-1,0,0,-1,1666350,231336,0.0,-1.8,-1,0.0,-1,0.0,-183.78,-1,0.0,-1,1034250912.0,12.33,63.58,65.04,46.03,41.14,-1,18787,36574,1385,19012,0,0,0,21325,0,0,0,0,0,0,0,4,3739,3865,55,596,9300,0,9896,47.61904761904762,21,20,AREA 0,4,35,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,4,4 |
