| /root/template/Makefile |
| /root/template/docs/environment.yml |
| /root/template/docs/Makefile |
| /root/template/docs/source/index.rst |
| /root/template/docs/source/conf.py |
| /root/template/verilog/dv/Makefile |
| /root/template/verilog/dv/la_test2/la_test2_tb.v |
| /root/template/verilog/dv/la_test2/la_test2.c |
| /root/template/verilog/dv/la_test2/Makefile |
| /root/template/verilog/dv/la_test1/la_test1.c |
| /root/template/verilog/dv/la_test1/Makefile |
| /root/template/verilog/dv/la_test1/la_test1_tb.v |
| /root/template/verilog/dv/io_ports/Makefile |
| /root/template/verilog/dv/io_ports/io_ports_tb.v |
| /root/template/verilog/dv/io_ports/io_ports.c |
| /root/template/verilog/dv/mprj_stimulus/Makefile |
| /root/template/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/template/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/template/verilog/dv/wb_port/wb_port_tb.v |
| /root/template/verilog/dv/wb_port/Makefile |
| /root/template/verilog/dv/wb_port/wb_port.c |
| /root/template/verilog/rtl/uprj_netlists.v |
| /root/template/verilog/rtl/user_project_wrapper.v |
| /root/template/verilog/rtl/user_proj/top.v |
| /root/template/openlane/Makefile |
| /root/template/openlane/user_project_wrapper/config.json |
| /root/template/openlane/user_project_wrapper/config.tcl |
| /root/template/openlane/user_proj/config.tcl |
