License Text Added
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv index 53dcb62..2ead606 100644 --- a/verilog/rtl/digital_core/src/digital_core.sv +++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// Digital core //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/digital_core/src/glbl_cfg.sv b/verilog/rtl/digital_core/src/glbl_cfg.sv index 9e1f371..a91502e 100644 --- a/verilog/rtl/digital_core/src/glbl_cfg.sv +++ b/verilog/rtl/digital_core/src/glbl_cfg.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// Global confg register //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/lib/async_fifo.sv b/verilog/rtl/lib/async_fifo.sv index 0d6dc29..fd59cfa 100755 --- a/verilog/rtl/lib/async_fifo.sv +++ b/verilog/rtl/lib/async_fifo.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* ASYNC FIFO - This file is part of the sdram controller project + This file is part of the sdram controller project + https://github.com/dineshannayya/yifive_r0.git http://www.opencores.org/cores/sdr_ctrl/ Description: ASYNC FIFO
diff --git a/verilog/rtl/lib/async_fifo_th.sv b/verilog/rtl/lib/async_fifo_th.sv index 5ff3df6..05860f8 100755 --- a/verilog/rtl/lib/async_fifo_th.sv +++ b/verilog/rtl/lib/async_fifo_th.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// OMS 8051 cores common library Module //// //// //// //// This file is part of the OMS 8051 cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/oms8051mini/ //// //// //// //// Description ////
diff --git a/verilog/rtl/lib/clk_ctl.v b/verilog/rtl/lib/clk_ctl.v index 7f050c0..34f5989 100644 --- a/verilog/rtl/lib/clk_ctl.v +++ b/verilog/rtl/lib/clk_ctl.v
@@ -1,8 +1,25 @@ -////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +//////////////////////////////////////////////////////////////////////// //// //// //// Tubo 8051 cores common library Module //// //// //// //// This file is part of the Turbo 8051 cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/turbo8051/ //// //// //// //// Description ////
diff --git a/verilog/rtl/lib/double_sync_high.v b/verilog/rtl/lib/double_sync_high.v index 8e39520..d1d2ca6 100755 --- a/verilog/rtl/lib/double_sync_high.v +++ b/verilog/rtl/lib/double_sync_high.v
@@ -1,9 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// OMS 8051 cores common library Module //// //// //// //// This file is part of the OMS 8051 cores project //// //// http://www.opencores.org/cores/oms8051mini/ //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// //// //// Description //// //// OMS 8051 definitions. ////
diff --git a/verilog/rtl/lib/double_sync_low.v b/verilog/rtl/lib/double_sync_low.v index 2709b91..efd4269 100755 --- a/verilog/rtl/lib/double_sync_low.v +++ b/verilog/rtl/lib/double_sync_low.v
@@ -1,9 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// OMS 8051 cores common library Module //// //// //// //// This file is part of the OMS 8051 cores project //// //// http://www.opencores.org/cores/oms8051mini/ //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// //// //// Description //// //// OMS 8051 definitions. ////
diff --git a/verilog/rtl/lib/reset_sync.sv b/verilog/rtl/lib/reset_sync.sv index f2c552f..d96c719 100644 --- a/verilog/rtl/lib/reset_sync.sv +++ b/verilog/rtl/lib/reset_sync.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// Active low reset synchronization //// //// //// //// This file is part of the yifive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description: ////
diff --git a/verilog/rtl/lib/sync_fifo.sv b/verilog/rtl/lib/sync_fifo.sv index 874adb3..464a26c 100644 --- a/verilog/rtl/lib/sync_fifo.sv +++ b/verilog/rtl/lib/sync_fifo.sv
@@ -1,7 +1,25 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* This file is part of the sdram controller project http://www.opencores.org/cores/sdr_ctrl/ + https://github.com/dineshannayya/yifive_r0.git Description: SYNC FIFO Parameters:
diff --git a/verilog/rtl/lib/wb_interface.v b/verilog/rtl/lib/wb_interface.v index 222704a..f25b147 100644 --- a/verilog/rtl/lib/wb_interface.v +++ b/verilog/rtl/lib/wb_interface.v
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// yifive common library Module //// //// //// //// This file is part of the yifive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description: ////
diff --git a/verilog/rtl/lib/wb_stagging.sv b/verilog/rtl/lib/wb_stagging.sv index 5fce5f1..8f54f0f 100644 --- a/verilog/rtl/lib/wb_stagging.sv +++ b/verilog/rtl/lib/wb_stagging.sv
@@ -1,3 +1,20 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// //---------------------------------------------------------------------- // This logic create a holding register for Wishbone interface. // This is usefull to break timing issue at interconnect @@ -10,6 +27,7 @@ //// Wishbone Stagging FF //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v index 2206db6..a78ae9d 100755 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v +++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v
@@ -1,8 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* SDRAM Controller Bank Controller This file is part of the sdram controller project + https://github.com/dineshannayya/yifive_r0.git + http://www.opencores.org/cores/yifive/ http://www.opencores.org/cores/sdr_ctrl/ Description:
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v index 5eeb1e9..d566f6f 100755 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v +++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v
@@ -1,8 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* SDRAM Controller Bank Controller This file is part of the sdram controller project + https://github.com/dineshannayya/yifive_r0.git + http://www.opencores.org/cores/yifive/ http://www.opencores.org/cores/sdr_ctrl/ Description:
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v index 025e74c..de96f95 100755 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v +++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v
@@ -1,8 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* SDRAM Controller buswidth converter This file is part of the sdram controller project + https://github.com/dineshannayya/yifive_r0.git + http://www.opencores.org/cores/yifive/ http://www.opencores.org/cores/sdr_ctrl/ Description: SDRAM Controller Buswidth converter
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v index d4d9941..bf1cd8b 100755 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v +++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
@@ -1,8 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* SDRAM Controller Core File This file is part of the sdram controller project + https://github.com/dineshannayya/yifive_r0.git + http://www.opencores.org/cores/yifive/ http://www.opencores.org/cores/sdr_ctrl/ Description: SDRAM Controller Core Module
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v index 3d9edf6..5fd7bb9 100755 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v +++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
@@ -1,8 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* SDRAM Controller Request Generation This file is part of the sdram controller project + https://github.com/dineshannayya/yifive_r0.git + http://www.opencores.org/cores/yifive/ http://www.opencores.org/cores/sdr_ctrl/ Description: SDRAM Controller Reguest Generation
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v index ef01b9d..6ec7ad2 100755 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v +++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v
@@ -1,8 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* SDRAM Controller Transfer control This file is part of the sdram controller project + https://github.com/dineshannayya/yifive_r0.git + http://www.opencores.org/cores/yifive/ http://www.opencores.org/cores/sdr_ctrl/ Description: SDRAM Controller Transfer control
diff --git a/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v b/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v index 10c10da..dc66c23 100755 --- a/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v +++ b/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v
@@ -1,4 +1,21 @@ - +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +/********************************************************************* `define SDR_REQ_ID_W 4 `define SDR_RFSH_TIMER_W 12
diff --git a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v index ab99a8c..ab49c52 100755 --- a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v +++ b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
@@ -1,8 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* SDRAM Controller top File This file is part of the sdram controller project + https://github.com/dineshannayya/yifive_r0.git + http://www.opencores.org/cores/yifive/ http://www.opencores.org/cores/sdr_ctrl/ Description: SDRAM Controller Top Module.
diff --git a/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v b/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v index 023a3ee..1a6cc6b 100755 --- a/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v +++ b/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v
@@ -1,6 +1,25 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// /********************************************************************* This file is part of the sdram controller project + https://github.com/dineshannayya/yifive_r0.git + http://www.opencores.org/cores/yifive/ http://www.opencores.org/cores/sdr_ctrl/ Description: WISHBONE to SDRAM Controller Bus Transalator
diff --git a/verilog/rtl/spi_master/src/spim_clkgen.sv b/verilog/rtl/spi_master/src/spim_clkgen.sv index 8c9fa83..bc3d9fb 100644 --- a/verilog/rtl/spi_master/src/spim_clkgen.sv +++ b/verilog/rtl/spi_master/src/spim_clkgen.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// SPI Clkgen Module //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/spi_master/src/spim_ctrl.sv b/verilog/rtl/spi_master/src/spim_ctrl.sv index 5ae41ad..b4bee53 100644 --- a/verilog/rtl/spi_master/src/spim_ctrl.sv +++ b/verilog/rtl/spi_master/src/spim_ctrl.sv
@@ -1,9 +1,26 @@ - +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// SPI CTRL I/F Module //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/spi_master/src/spim_fifo.sv b/verilog/rtl/spi_master/src/spim_fifo.sv index e1c665b..bbe3c1a 100644 --- a/verilog/rtl/spi_master/src/spim_fifo.sv +++ b/verilog/rtl/spi_master/src/spim_fifo.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// YiFive cores common library Module //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/spi_master/src/spim_regs.sv b/verilog/rtl/spi_master/src/spim_regs.sv index cfb8ead..64cb6f7 100644 --- a/verilog/rtl/spi_master/src/spim_regs.sv +++ b/verilog/rtl/spi_master/src/spim_regs.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// SPI WishBone Register I/F Module //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/spi_master/src/spim_rx.sv b/verilog/rtl/spi_master/src/spim_rx.sv index ea0d8a9..7832a8e 100644 --- a/verilog/rtl/spi_master/src/spim_rx.sv +++ b/verilog/rtl/spi_master/src/spim_rx.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// SPI RX Module //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv index a405e9a..98c7a66 100644 --- a/verilog/rtl/spi_master/src/spim_top.sv +++ b/verilog/rtl/spi_master/src/spim_top.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// SPI Master Top Module //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/spi_master/src/spim_tx.sv b/verilog/rtl/spi_master/src/spim_tx.sv index db6516e..7a9284c 100644 --- a/verilog/rtl/spi_master/src/spim_tx.sv +++ b/verilog/rtl/spi_master/src/spim_tx.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// SPI TX Module //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/syntacore/scr1/src/ahb_top.files b/verilog/rtl/syntacore/scr1/src/ahb_top.files deleted file mode 100644 index 603839e..0000000 --- a/verilog/rtl/syntacore/scr1/src/ahb_top.files +++ /dev/null
@@ -1,8 +0,0 @@ -top/scr1_dmem_router.sv -top/scr1_imem_router.sv -top/scr1_dp_memory.sv -top/scr1_tcm.sv -top/scr1_timer.sv -top/scr1_dmem_ahb.sv -top/scr1_imem_ahb.sv -top/scr1_top_ahb.sv
diff --git a/verilog/rtl/syntacore/scr1/src/axi_top.files b/verilog/rtl/syntacore/scr1/src/axi_top.files deleted file mode 100644 index 24f4b8e..0000000 --- a/verilog/rtl/syntacore/scr1/src/axi_top.files +++ /dev/null
@@ -1,7 +0,0 @@ -top/scr1_dmem_router.sv -top/scr1_imem_router.sv -top/scr1_dp_memory.sv -top/scr1_tcm.sv -top/scr1_timer.sv -top/scr1_mem_axi.sv -top/scr1_top_axi.sv \ No newline at end of file
diff --git a/verilog/rtl/syntacore/scr1/src/core.files b/verilog/rtl/syntacore/scr1/src/core.files index ca5de45..f310fe6 100644 --- a/verilog/rtl/syntacore/scr1/src/core.files +++ b/verilog/rtl/syntacore/scr1/src/core.files
@@ -1,3 +1,20 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// core/pipeline/scr1_pipe_hdu.sv core/pipeline/scr1_pipe_tdu.sv core/pipeline/scr1_ipic.sv
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv index d53127b..4afaae5 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_ipic.sv> /// @brief Integrated Programmable Interrupt Controller (IPIC) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv index ca96215..05b820c 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_csr.sv> /// @brief Control Status Registers (CSR) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv index 9c76c7d..8ce42c3 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_exu.sv> /// @brief Execution Unit (EXU) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv index 14f421b..e23e54b 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_hdu.sv> /// @brief HART Debug Unit (HDU) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv index 0cc18e6..922a518 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_ialu.sv> /// @brief Integer Arithmetic Logic Unit (IALU) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv index 8b4ae76..fec4b9d 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_idu.sv> /// @brief Instruction Decoder Unit (IDU) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv index 98b5496..83e2ef1 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_ifu.sv> /// @brief Instruction Fetch Unit (IFU) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv index 3d75570..6bece2b 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_lsu.sv> /// @brief Load/Store Unit (LSU) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv index 89c0b3e..9b4b167 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
@@ -1,3 +1,20 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details /// @file <scr1_pipe_mprf.sv> /// @brief Multi Port Register File (MPRF)
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv index ad4ff42..888a313 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_tdu.sv> /// @brief Trigger Debug Unit (TDU) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv index 4678a9a..3779eb5 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_top.sv> /// @brief SCR1 pipeline top ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv index 5682cee..4b845d8 100644 --- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv +++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_tracelog.sv> /// @brief Core tracelog module ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv b/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv index b0f6154..edc513b 100644 --- a/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv +++ b/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_cg.sv> /// @brief SCR1 clock gate primitive /// @@ -29,4 +45,4 @@ endmodule : scr1_cg -`endif // SCR1_CLKCTRL_EN \ No newline at end of file +`endif // SCR1_CLKCTRL_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv b/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv index 1af347c..f7eadfa 100644 --- a/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv +++ b/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_sync_rstn.sv> /// @brief Cells for reset handling /// @@ -228,4 +244,4 @@ assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : rst_n_in[select]; -endmodule : scr1_reset_mux2_cell \ No newline at end of file +endmodule : scr1_reset_mux2_cell
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv index 09b72f4..62fc837 100644 --- a/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv +++ b/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_clk_ctrl.sv> /// @brief SCR1 clock control /// @@ -52,4 +68,4 @@ endmodule : scr1_clk_ctrl -`endif // SCR1_CLKCTRL_EN \ No newline at end of file +`endif // SCR1_CLKCTRL_EN
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv index ba156f3..6df5558 100644 --- a/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv +++ b/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +/////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_core_top.sv> /// @brief SCR1 core top ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv index 724d98d..febeaee 100644 --- a/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv +++ b/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_dm.sv> /// @brief Debug Module (DM) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv index ba62c2a..edb621e 100644 --- a/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv +++ b/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_dmi.sv> /// @brief Debug Module Interface (DMI) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv index a370f40..b63972e 100644 --- a/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv +++ b/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_scu.sv> /// @brief System Control Unit (SCU) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv index 45687f4..2761057 100644 --- a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv +++ b/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_tapc.sv> /// @brief TAP Controller (TAPC) ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv index a577bcc..a9da091 100644 --- a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv +++ b/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_tapc_shift_reg.sv> /// @brief TAPC shift register. Parameterized implementation of JTAG TAPC's Shift Register. ///
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv index 0d94705..39715d9 100644 --- a/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv +++ b/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_tapc_synchronizer.sv> /// @brief TAPC clock domain crossing synchronizer ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh index 54cd4e1..c630f6a 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_ahb.svh> /// @brief AHB header file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh index 7b89dc6..36179a8 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_arch_description.svh> /// @brief Architecture description file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh index 6f76889..ebe67e6 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_arch_types.svh> /// @brief Pipeline types description file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh index 18dcafb..d9ee33a 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_csr.svh> /// @brief CSR mapping/description file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh index 0d4b0d9..8c98684 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_dm.svh> /// @brief Debug Module header file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh index 1d73fe4..155792c 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_pipe_hdu.svh> /// @brief HART Debug Unit definitions file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh index 4a42dc3..555137c 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_ipic.svh> /// @brief IPIC header file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh index 395403e..997df58 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_memif.svh> /// @brief Memory interface definitions file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh index 890807a..ff380a1 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_riscv_isa_decoding.svh> /// @brief RISC-V ISA definitions file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh index 35659d5..2c8f5df 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_scu.svh> /// @brief SCU header file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh index 0fd8ac5..5532c59 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_search_ms1.svh> /// @brief Most significant one search function ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh index e96ea44..cdf5068 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_tapc.svh> /// @brief TAPC header file ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh index 79382cf..fda1616 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_tdu.svh> /// @brief Trigger Debug Module header ///
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh index 58f99d6..c061103 100644 --- a/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh +++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////// //// //// //// yifive Wishbone define for syntacore //// //// //// //// This file is part of the yifive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description: ////
diff --git a/verilog/rtl/syntacore/scr1/src/run_modemsim b/verilog/rtl/syntacore/scr1/src/run_modemsim index ae5f764..51910e9 100755 --- a/verilog/rtl/syntacore/scr1/src/run_modemsim +++ b/verilog/rtl/syntacore/scr1/src/run_modemsim
@@ -1,2 +1,19 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// vlib work vlog -f wb_top.files -f core.files +incdir+includes -sv
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv index f1a8f00..43958b1 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_dmem_ahb.sv> /// @brief Data memory AHB bridge ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv index badd8cd..749085a 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_dmem_router.sv> /// @brief Data memory router ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv index b9e893a..393a7af 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////// //// //// //// yifive Wishbone interface for Data memory //// //// //// //// This file is part of the yifive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description: ////
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv index 971591d..00a2281 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_dp_memory.sv> /// @brief Dual-port synchronous memory with byte enable inputs ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv index 47ad399..764f0d3 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_imem_ahb.sv> /// @brief Instruction memory AHB bridge ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv index 7652201..72554f1 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_imem_router.sv> /// @brief Instruction memory router ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv index fb6c137..60b732f 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////// //// //// //// yifive Wishbone interface for Instruction memory //// //// //// //// This file is part of the yifive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description: ////
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv index 1b9155d..cad4658 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_mem_axi.sv> /// @brief Memory AXI bridge ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv index 82a8b06..5a5d61e 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_tcm.sv> /// @brief Tightly-Coupled Memory (TCM) ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv index 6787754..7750789 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_timer.sv> /// @brief Memory-mapped Timer ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv index 288d15e..7856118 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_top_ahb.sv> /// @brief SCR1 AHB top ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv index bbcc30d..f7e4962 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv
@@ -1,4 +1,20 @@ -/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Syntacore LLC +// ////////////////////////////////////////////////////////////////////////// /// @file <scr1_top_axi.sv> /// @brief SCR1 AXI top ///
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv index 3ded0b8..ccb49e8 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////// //// //// //// yifive Wishbone interface for syntacore //// //// //// //// This file is part of the yifive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description: ////
diff --git a/verilog/rtl/syntacore/scr1/src/wb_top.files b/verilog/rtl/syntacore/scr1/src/wb_top.files index 1a3ba74..25f9f8f 100644 --- a/verilog/rtl/syntacore/scr1/src/wb_top.files +++ b/verilog/rtl/syntacore/scr1/src/wb_top.files
@@ -1,3 +1,20 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// top/scr1_dmem_router.sv top/scr1_dp_memory.sv top/scr1_tcm.sv
diff --git a/verilog/rtl/syntacore/scr1/synth/Makefile b/verilog/rtl/syntacore/scr1/synth/Makefile index 2288b2c..723d4c4 100644 --- a/verilog/rtl/syntacore/scr1/synth/Makefile +++ b/verilog/rtl/syntacore/scr1/synth/Makefile
@@ -1,3 +1,20 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// #------------------------------------------------------------------------------ # Makefile for Synthesis #------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/synth/run_synth b/verilog/rtl/syntacore/scr1/synth/run_synth index e537107..d549ad4 100755 --- a/verilog/rtl/syntacore/scr1/synth/run_synth +++ b/verilog/rtl/syntacore/scr1/synth/run_synth
@@ -1,3 +1,20 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// ##################################################### # Clean up old file and freshly create the directory ####################################################
diff --git a/verilog/rtl/uart/src/uart_cfg.sv b/verilog/rtl/uart/src/uart_cfg.sv index 1cd7ee1..ca4dea6 100644 --- a/verilog/rtl/uart/src/uart_cfg.sv +++ b/verilog/rtl/uart/src/uart_cfg.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// UART Configuration //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv index 09b3f6a..1141b3d 100644 --- a/verilog/rtl/uart/src/uart_core.sv +++ b/verilog/rtl/uart/src/uart_core.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// UART CORE with TX/RX 16 Byte Buffer //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/uart/src/uart_rxfsm.sv b/verilog/rtl/uart/src/uart_rxfsm.sv index e7dea59..58916e6 100644 --- a/verilog/rtl/uart/src/uart_rxfsm.sv +++ b/verilog/rtl/uart/src/uart_rxfsm.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// UART RX FSM //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/uart/src/uart_txfsm.sv b/verilog/rtl/uart/src/uart_txfsm.sv index fd8f947..ad6507e 100644 --- a/verilog/rtl/uart/src/uart_txfsm.sv +++ b/verilog/rtl/uart/src/uart_txfsm.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// UART TX FSM //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index 0dc98b6..6464c64 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// Wishbone host Interface //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/wb_interconnect/src/wb_arb.sv b/verilog/rtl/wb_interconnect/src/wb_arb.sv index a477c94..16e0da7 100644 --- a/verilog/rtl/wb_interconnect/src/wb_arb.sv +++ b/verilog/rtl/wb_interconnect/src/wb_arb.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// Wishbone Arbitor //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index 9ef5574..e710cfb 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -1,8 +1,26 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////// //// //// //// Wishbone Interconnect //// //// //// //// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// //// http://www.opencores.org/cores/yifive/ //// //// //// //// Description ////