met5 density fix
diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz index 316cc67..27e75c0 100644 --- a/def/user_project_wrapper.def.gz +++ b/def/user_project_wrapper.def.gz Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index 2a3260d..96a0cc6 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz index ce047a1..b32aaf5 100644 --- a/lef/user_project_wrapper.lef.gz +++ b/lef/user_project_wrapper.lef.gz Binary files differ
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz index 7635e80..f7c880f 100644 --- a/mag/user_project_wrapper.mag.gz +++ b/mag/user_project_wrapper.mag.gz Binary files differ
diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz index 73c6405..aeadd12 100644 --- a/maglef/user_project_wrapper.mag.gz +++ b/maglef/user_project_wrapper.mag.gz Binary files differ
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 9de5b13..e8c75d9 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -4,7 +4,7 @@ u_riscv_top 200 700 N u_sram_2kb 200 165 N -u_mbist1 1100 1300 N +u_mbist1 1100 1325 N u_sram1_2kb 200 1325 N u_mbist2 1100 1850 N
diff --git a/openlane/wb_interconnect/interactive.tcl b/openlane/wb_interconnect/interactive.tcl index b44b517..a180a5c 100644 --- a/openlane/wb_interconnect/interactive.tcl +++ b/openlane/wb_interconnect/interactive.tcl
@@ -121,6 +121,190 @@ } } +proc gen_pdn {args} { + puts_info "Generating PDN..." + TIMER::timer_start + + set ::env(SAVE_DEF) [index_file $::env(pdn_tmp_file_tag).def] + set ::env(PGA_RPT_FILE) [index_file $::env(pdn_report_file_tag).pga.rpt] + + try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/pdn.tcl \ + |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log 0] + + + TIMER::timer_stop + exec echo "[TIMER::get_runtime]" >> [index_file $::env(pdn_log_file_tag)_runtime.txt 0] + + quit_on_unconnected_pdn_nodes + + set_def $::env(SAVE_DEF) +} + +proc run_power_grid_generation {args} { + if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } { + # they both must exist and be equal in length + # current assumption: they cannot have a common ground + if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } { + puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined" + return -code error + } + # standard cell power and ground nets are assumed to be the first net + set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0] + set ::env(GND_PIN) [lindex $::env(GND_NETS) 0] + } elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } { + set ::env(VDD_NETS) [list] + set ::env(GND_NETS) [list] + # get the pins that are in $yosys_tmp_file_tag.pg_define.v + # that are not in $yosys_result_file_tag.v + # + set full_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_tmp_file_tag).pg_define.v] + puts_info $full_pins + + set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_result_file_tag).v] + puts_info $non_pg_pins + + # assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...) + foreach {vdd gnd} $full_pins { + if { $vdd ne "" && $vdd ni $non_pg_pins } { + lappend ::env(VDD_NETS) $vdd + } + if { $gnd ne "" && $gnd ni $non_pg_pins } { + lappend ::env(GND_NETS) $gnd + } + } + } else { + set ::env(VDD_NETS) $::env(VDD_PIN) + set ::env(GND_NETS) $::env(GND_PIN) + } + + puts_info "Power planning the following nets" + puts_info "Power: $::env(VDD_NETS)" + puts_info "Ground: $::env(GND_NETS)" + + if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } { + puts_err "VDD_NETS and GND_NETS must be of equal lengths" + return -code error + } + + # internal macros power connections + if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} { + set macro_hooks [dict create] + set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","] + foreach pdn_hook $pdn_hooks { + set instance_name [lindex $pdn_hook 0] + set power_net [lindex $pdn_hook 1] + set ground_net [lindex $pdn_hook 2] + dict append macro_hooks $instance_name [subst {$power_net $ground_net}] + set power_net_indx [lsearch $::env(VDD_NETS) $power_net] + set ground_net_indx [lsearch $::env(GND_NETS) $ground_net] + + # make sure that the specified power domains exist. + if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } { + puts_err "Can't find $power_net and $ground_net domain. \ + Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)." + } + } + + } + + # generate multiple power grids per pair of (VDD,GND) + # offseted by WIDTH + SPACING + foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) { + set ::env(VDD_NET) $vdd + set ::env(GND_NET) $gnd + puts_info "Connecting Power: $vdd & gnd to All internal macros." + + # internal macros power connections + set ::env(FP_PDN_MACROS) "" + if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } { + # if macros connections to power are explicitly set + # default behavoir macro pins will be connected to the first power domain + if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } { + set ::env(FP_PDN_ENABLE_MACROS_GRID) 0 + foreach {instance_name hooks} $macro_hooks { + set power [lindex $hooks 0] + set ground [lindex $hooks 1] + if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } { + set ::env(FP_PDN_ENABLE_MACROS_GRID) 1 + puts_info "Connecting $instance_name to $power and $ground nets." + lappend ::env(FP_PDN_MACROS) $instance_name + } + } + } + } else { + puts_warn "All internal macros will not be connected to power $vdd & $gnd." + } + + gen_pdn + + set ::env(FP_PDN_ENABLE_RAILS) 0 + set ::env(FP_PDN_ENABLE_MACROS_GRID) 0 + + # allow failure until open_pdks is up to date... + catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]} + catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]} + + catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \ + [expr $::env(FP_PDN_CORE_RING_VOFFSET)\ + +2*($::env(FP_PDN_CORE_RING_VWIDTH)\ + +max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]} + catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\ + +2*($::env(FP_PDN_CORE_RING_HWIDTH)+\ + max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]} + + puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)" + puts "FP_PDN_HOFFSET: $::env(FP_PDN_VOFFSET)" + puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)" + puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)" + } + set ::env(FP_PDN_ENABLE_RAILS) 1 +} + + +proc run_floorplan {args} { + puts_info "Running Floorplanning..." + # |----------------------------------------------------| + # |---------------- 2. FLOORPLAN ------------------| + # |----------------------------------------------------| + # + # intial fp + init_floorplan + + + # place io + if { [info exists ::env(FP_PIN_ORDER_CFG)] } { + place_io_ol + } else { + if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } { + place_io + global_placement_or + place_contextualized_io \ + -lef $::env(FP_CONTEXT_LEF) \ + -def $::env(FP_CONTEXT_DEF) + } else { + place_io + } + } + + apply_def_template + + if { [info exist ::env(EXTRA_LEFS)] } { + if { [info exist ::env(MACRO_PLACEMENT_CFG)] } { + file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg + manual_macro_placement f + } else { + global_placement_or + basic_macro_placement + } + } + + # tapcell + tap_decap_or + scrot_klayout -layout $::env(CURRENT_DEF) + # power grid generation + run_power_grid_generation +} + proc run_flow {args} { set script_dir [file dirname [file normalize [info script]]]
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 11fdeb7..2973df2 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h37m7s,-1,2.9187422166874217,10.2784,1.4593711083437109,-1,534.86,15,0,0,0,0,0,0,-1,0,0,-1,-1,1473539,10786,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.52,4.54,3.22,0.59,0.54,-1,298,2697,298,2697,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h37m54s,-1,2.9187422166874217,10.2784,1.4593711083437109,-1,535.66,15,0,0,0,0,0,0,-1,0,0,-1,-1,1475745,10933,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.52,4.51,3.23,0.65,0.54,-1,298,2697,298,2697,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/spef/user_project_wrapper.spef.gz b/spef/user_project_wrapper.spef.gz index 52a5e59..ccf698d 100644 --- a/spef/user_project_wrapper.spef.gz +++ b/spef/user_project_wrapper.spef.gz Binary files differ
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz index 6388e1f..47e190c 100644 --- a/spi/lvs/user_project_wrapper.spice.gz +++ b/spi/lvs/user_project_wrapper.spice.gz Binary files differ