riscv_regress simulation works through docker

verilog/dv/Makefile

diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 4076ba9..a1ce832 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus risc_boot user_risc_boot user_uart user_spi user_i2cm
+PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \

verilog/dv/riscv_regress/Makefile

diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index c1bba74..f6e545f 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -194,7 +194,7 @@
 # Targets
 .PHONY: tests run_iverilog run_modelsim run_modelsim_wlf run_vcs run_ncsim run_verilator run_verilator_wf
 
-default: clean_test_list run_verilator
+default: clean_test_list run_iverilog
 
 clean_test_list:
 	rm -f $(test_info)