first version of riscduino with sdram removed, pinmux and sar_adc added
diff --git a/.gitmodules b/.gitmodules index 3e46499..6b99e94 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -8,3 +8,6 @@ [submodule "verilog/rtl/syntacore/scr1/dependencies/coremark"] path = verilog/rtl/syntacore/scr1/dependencies/coremark url = https://github.com/eembc/coremark +[submodule "caravel"] + path = caravel + url = https://github.com/efabless/caravel-lite
diff --git a/caravel b/caravel new file mode 160000 index 0000000..13f2590 --- /dev/null +++ b/caravel
@@ -0,0 +1 @@ +Subproject commit 13f2590e4b3a74b910dac56a6b757f5a66fd5212
diff --git a/openlane/pinmux/base.sdc b/openlane/pinmux/base.sdc new file mode 100644 index 0000000..8def5de --- /dev/null +++ b/openlane/pinmux/base.sdc
@@ -0,0 +1,57 @@ +# SPDX-FileCopyrightText: 2021 , Dinesh Annayya +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> + + +set_units -time ns +set ::env(WBM_CLOCK_PERIOD) "10" +set ::env(WBM_CLOCK_PORT) "mclk" +set ::env(WBM_CLOCK_NAME) "mclk" + + +###################################### +# WB Clock domain input output +###################################### +create_clock [get_ports $::env(WBM_CLOCK_PORT)] -name $::env(WBM_CLOCK_PORT) -period $::env(WBM_CLOCK_PERIOD) + + +set wb_input_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.6] +set wb_output_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.6] +puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value" +puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value" + + +set_input_delay 2.0 -clock [get_clocks $::env(WBM_CLOCK_PORT)] {h_reset_n} + +set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port reg_cs] +set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port reg_wr] +set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port reg_addr*] +set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port reg_wdata*] +set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port reg_be*] +set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_err_o*] + +set_output_delay 4.5 -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port reg_rdata*] +set_output_delay 4.5 -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port reg_ack] + + +set_clock_uncertainty -from $::env(WBM_CLOCK_NAME) -to $::env(WBM_CLOCK_NAME) -setup 0.400 + + +# TODO set this as parameter +set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] +set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs] +
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl new file mode 100755 index 0000000..a98636c --- /dev/null +++ b/openlane/pinmux/config.tcl
@@ -0,0 +1,94 @@ +# SPDX-FileCopyrightText: 2021 , Dinesh Annayya +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> + +# Global +# ------ + +set script_dir [file dirname [file normalize [info script]]] +# Name + +set ::env(DESIGN_NAME) pinmux + +set ::env(DESIGN_IS_CORE) "0" +set ::env(FP_PDN_CORE_RING) "0" + +# Timing configuration +set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PORT) "mclk" + +set ::env(SYNTH_MAX_FANOUT) 4 + +# Sources +# ------- + +# Local sources + no2usb sources +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/pinmux/src/pinmux.sv \ + $script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv \ + $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv \ + $script_dir/../../verilog/rtl/pinmux/src/pwm.sv \ + $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv \ + $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv \ + $script_dir/../../verilog/rtl/lib/registers.v" + + +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +set ::env(SDC_FILE) "$script_dir/base.sdc" +set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" + +set ::env(LEC_ENABLE) 0 + +set ::env(VDD_PIN) [list {vccd1}] +set ::env(GND_PIN) [list {vssd1}] + + +# Floorplanning +# ------------- + +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 500 400" + + +# If you're going to use multiple power domains, then keep this disabled. +set ::env(RUN_CVC) 0 + +#set ::env(PDN_CFG) $script_dir/pdn.tcl + + +set ::env(PL_ROUTABILITY_DRIVEN) 1 +set ::env(PL_TARGET_DENSITY) "0.35" +set ::env(CELL_PAD) "4" + + +# helps in anteena fix +set ::env(USE_ARC_ANTENNA_CHECK) "0" + +set ::env(FP_IO_VEXTEND) 4 +set ::env(FP_IO_HEXTEND) 4 + +set ::env(FP_PDN_VPITCH) 100 +set ::env(FP_PDN_HPITCH) 100 +set ::env(FP_PDN_VWIDTH) 5 +set ::env(FP_PDN_HWIDTH) 5 + +set ::env(GLB_RT_MAXLAYER) 4 +set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 + +set ::env(DIODE_INSERTION_STRATEGY) 5 + +
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg new file mode 100644 index 0000000..3c03978 --- /dev/null +++ b/openlane/pinmux/pin_order.cfg
@@ -0,0 +1,339 @@ +#BUS_SORT +#MANUAL_PLACE + +#N +mclk +h_reset_n +irq_lines\[15\] +irq_lines\[14\] +irq_lines\[13\] +irq_lines\[12\] +irq_lines\[11\] +irq_lines\[10\] +irq_lines\[9\] +irq_lines\[8\] +irq_lines\[7\] +irq_lines\[6\] +irq_lines\[5\] +irq_lines\[4\] +irq_lines\[3\] +irq_lines\[2\] +irq_lines\[1\] +irq_lines\[0\] +user_irq\[2\] +user_irq\[1\] +user_irq\[0\] +soft_irq +fuse_mhartid\[31\] +fuse_mhartid\[30\] +fuse_mhartid\[29\] +fuse_mhartid\[28\] +fuse_mhartid\[27\] +fuse_mhartid\[26\] +fuse_mhartid\[25\] +fuse_mhartid\[24\] +fuse_mhartid\[23\] +fuse_mhartid\[22\] +fuse_mhartid\[21\] +fuse_mhartid\[20\] +fuse_mhartid\[19\] +fuse_mhartid\[18\] +fuse_mhartid\[17\] +fuse_mhartid\[16\] +fuse_mhartid\[15\] +fuse_mhartid\[14\] +fuse_mhartid\[13\] +fuse_mhartid\[12\] +fuse_mhartid\[11\] +fuse_mhartid\[10\] +fuse_mhartid\[9\] +fuse_mhartid\[8\] +fuse_mhartid\[7\] +fuse_mhartid\[6\] +fuse_mhartid\[5\] +fuse_mhartid\[4\] +fuse_mhartid\[3\] +fuse_mhartid\[2\] +fuse_mhartid\[1\] +fuse_mhartid\[0\] + +ssram_sck +ssram_ss +ssram_oen +ssram_do\[3\] +ssram_do\[2\] +ssram_do\[1\] +ssram_do\[0\] +ssram_di\[3\] +ssram_di\[2\] +ssram_di\[1\] +ssram_di\[0\] + +usb_dp_o +usb_dn_o +usb_oen +usb_dp_i +usb_dn_i +uart_txd +uart_rxd +i2cm_clk_o +i2cm_clk_i +i2cm_clk_oen +i2cm_data_oen +i2cm_data_o +i2cm_data_i +spim_sck +spim_ss +spim_miso +spim_mosi +pulse1m_mclk + + +reg_cs 200 0 +reg_wr +reg_addr\[7\] +reg_addr\[6\] +reg_addr\[5\] +reg_addr\[4\] +reg_addr\[3\] +reg_addr\[2\] +reg_addr\[1\] +reg_addr\[0\] +reg_be\[3\] +reg_be\[2\] +reg_be\[1\] +reg_be\[0\] +reg_wdata\[31\] +reg_wdata\[30\] +reg_wdata\[29\] +reg_wdata\[28\] +reg_wdata\[27\] +reg_wdata\[26\] +reg_wdata\[25\] +reg_wdata\[24\] +reg_wdata\[23\] +reg_wdata\[22\] +reg_wdata\[21\] +reg_wdata\[20\] +reg_wdata\[19\] +reg_wdata\[18\] +reg_wdata\[17\] +reg_wdata\[16\] +reg_wdata\[15\] +reg_wdata\[14\] +reg_wdata\[13\] +reg_wdata\[12\] +reg_wdata\[11\] +reg_wdata\[10\] +reg_wdata\[9\] +reg_wdata\[8\] +reg_wdata\[7\] +reg_wdata\[6\] +reg_wdata\[5\] +reg_wdata\[4\] +reg_wdata\[3\] +reg_wdata\[2\] +reg_wdata\[1\] +reg_wdata\[0\] +reg_rdata\[31\] +reg_rdata\[30\] +reg_rdata\[29\] +reg_rdata\[28\] +reg_rdata\[27\] +reg_rdata\[26\] +reg_rdata\[25\] +reg_rdata\[24\] +reg_rdata\[23\] +reg_rdata\[22\] +reg_rdata\[21\] +reg_rdata\[20\] +reg_rdata\[19\] +reg_rdata\[18\] +reg_rdata\[17\] +reg_rdata\[16\] +reg_rdata\[15\] +reg_rdata\[14\] +reg_rdata\[13\] +reg_rdata\[12\] +reg_rdata\[11\] +reg_rdata\[10\] +reg_rdata\[9\] +reg_rdata\[8\] +reg_rdata\[7\] +reg_rdata\[6\] +reg_rdata\[5\] +reg_rdata\[4\] +reg_rdata\[3\] +reg_rdata\[2\] +reg_rdata\[1\] +reg_rdata\[0\] +reg_ack + +digital_io_in\[15\] 300 0 +digital_io_out\[15\] +digital_io_oen\[15\] +digital_io_in\[16\] +digital_io_out\[16\] +digital_io_oen\[16\] +digital_io_in\[17\] +digital_io_out\[17\] +digital_io_oen\[17\] +digital_io_in\[18\] +digital_io_out\[18\] +digital_io_oen\[18\] +digital_io_in\[19\] +digital_io_out\[19\] +digital_io_oen\[19\] +digital_io_in\[20\] +digital_io_out\[20\] +digital_io_oen\[20\] +digital_io_in\[21\] +digital_io_out\[21\] +digital_io_oen\[21\] +digital_io_in\[22\] +digital_io_out\[22\] +digital_io_oen\[22\] +digital_io_in\[23\] +digital_io_out\[23\] +digital_io_oen\[23\] + +#S +pinmux_debug\[31\] 0000 0 +pinmux_debug\[30\] +pinmux_debug\[29\] +pinmux_debug\[28\] +pinmux_debug\[27\] +pinmux_debug\[26\] +pinmux_debug\[25\] +pinmux_debug\[24\] +pinmux_debug\[23\] +pinmux_debug\[22\] +pinmux_debug\[21\] +pinmux_debug\[20\] +pinmux_debug\[19\] +pinmux_debug\[18\] +pinmux_debug\[17\] +pinmux_debug\[16\] +pinmux_debug\[15\] +pinmux_debug\[14\] +pinmux_debug\[13\] +pinmux_debug\[12\] +pinmux_debug\[11\] +pinmux_debug\[10\] +pinmux_debug\[9\] +pinmux_debug\[8\] +pinmux_debug\[7\] +pinmux_debug\[6\] +pinmux_debug\[5\] +pinmux_debug\[4\] +pinmux_debug\[3\] +pinmux_debug\[2\] +pinmux_debug\[1\] +pinmux_debug\[0\] + + + +#E +digital_io_in\[0\] +digital_io_out\[0\] +digital_io_oen\[0\] +digital_io_in\[1\] +digital_io_out\[1\] +digital_io_oen\[1\] +digital_io_in\[2\] +digital_io_out\[2\] +digital_io_oen\[2\] +digital_io_in\[3\] +digital_io_out\[3\] +digital_io_oen\[3\] +digital_io_in\[4\] +digital_io_out\[4\] +digital_io_oen\[4\] +digital_io_in\[5\] +digital_io_out\[5\] +digital_io_oen\[5\] +digital_io_in\[6\] +digital_io_out\[6\] +digital_io_oen\[6\] +digital_io_in\[7\] +digital_io_out\[7\] +digital_io_oen\[7\] +digital_io_in\[8\] +digital_io_out\[8\] +digital_io_oen\[8\] +digital_io_in\[9\] +digital_io_out\[9\] +digital_io_oen\[9\] +digital_io_in\[10\] +digital_io_out\[10\] +digital_io_oen\[10\] +digital_io_in\[11\] +digital_io_out\[11\] +digital_io_oen\[11\] +digital_io_in\[12\] +digital_io_out\[12\] +digital_io_oen\[12\] +digital_io_in\[13\] +digital_io_out\[13\] +digital_io_oen\[13\] +digital_io_in\[14\] +digital_io_out\[14\] +digital_io_oen\[14\] + +#WR +digital_io_in\[24\] +digital_io_out\[24\] +digital_io_oen\[24\] +digital_io_in\[25\] +digital_io_out\[25\] +digital_io_oen\[25\] +digital_io_in\[26\] +digital_io_out\[26\] +digital_io_oen\[26\] +digital_io_in\[27\] +digital_io_out\[27\] +digital_io_oen\[27\] +digital_io_in\[28\] +digital_io_out\[28\] +digital_io_oen\[28\] +digital_io_in\[29\] +digital_io_out\[29\] +digital_io_oen\[29\] +digital_io_in\[30\] +digital_io_out\[30\] +digital_io_oen\[30\] +digital_io_in\[31\] +digital_io_out\[31\] +digital_io_oen\[31\] +digital_io_in\[32\] +digital_io_out\[32\] +digital_io_oen\[32\] +digital_io_in\[33\] +digital_io_out\[33\] +digital_io_oen\[33\] +digital_io_in\[34\] +digital_io_out\[34\] +digital_io_oen\[34\] +digital_io_in\[35\] +digital_io_out\[35\] +digital_io_oen\[35\] +digital_io_in\[36\] +digital_io_out\[36\] +digital_io_oen\[36\] +digital_io_in\[37\] +digital_io_out\[37\] +digital_io_oen\[37\] + +#W +sflash_di\[3\] 0200 0 +sflash_di\[2\] +sflash_di\[1\] +sflash_di\[0\] +sflash_do\[3\] +sflash_do\[2\] +sflash_do\[1\] +sflash_do\[0\] +sflash_sck +sflash_ss +sflash_oen +
diff --git a/openlane/sar_adc/config.tcl b/openlane/sar_adc/config.tcl new file mode 100644 index 0000000..ac93cf0 --- /dev/null +++ b/openlane/sar_adc/config.tcl
@@ -0,0 +1,86 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# section begin +set script_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) sar_adc +#section end +set ::env(RUN_KLAYOUT) 0 +set ::env(DESIGN_IS_CORE) 0 +set ::env(FP_PDN_CORE_RING) 0 + +# User Configurations +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +## Source Verilog Files +set ::env(VERILOG_FILES) "\ + $script_dir/../../caravel/verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/sar_adc/SAR.sv \ + $script_dir/../../verilog/rtl/sar_adc/ACMP.sv \ + $script_dir/../../verilog/rtl/sar_adc/sar_adc.sv \ + $script_dir/../../verilog/rtl/sar_adc/adc_reg.sv \ + $script_dir/../../verilog/rtl/lib/registers.v" + +## Clock configurations +set ::env(CLOCK_PORT) "clk" +set ::env(CLOCK_NET) "clk" + +set ::env(CLOCK_PERIOD) "100" + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +#set ::env(PDN_CFG) $script_dir/pdn.tcl + +set ::env(FP_SIZING) "absolute" +set ::env(DIE_AREA) "0 0 500 300" + +set ::env(FP_HORIZONTAL_HALO) 15 +set ::env(FP_VERTICAL_HALO) 15 + +#set ::env(GLB_RT_OBS) "met2 109.85000 19.89500 171.54500 69.22000" +set ::env(CLOCK_TREE_SYNTH) 0 + +set ::env(PL_TARGET_DENSITY) "0.01" +set ::env(GLB_RT_MAXLAYER) 5 +set ::env(GLB_RT_ADJUSTMENT) 0.15 + +set ::env(FP_PDN_CHECK_NODES) 0 +set ::env(FP_PDN_VPITCH) "45" +set ::env(FP_PDN_VWIDTH) "3.5" + +set ::env(FP_PDN_HPITCH) "40" +set ::env(FP_PDN_HWIDTH) "6.5" + +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 +set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 + +set ::env(DIODE_INSERTION_STRATEGY) 4 + +set ::env(FP_VERTICAL_HALO) "35" +set ::env(FP_HERTICAL_HALO) "35" + + +## Internal Macros +### Macro Placement +#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg + +### Black-box verilog and views + +set ::env(VDD_NETS) [list {vccd1} {vccd2}] +set ::env(GND_NETS) [list {vssd1} {vssd2}] +set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" + +## LVS mismatch is to be solved manually by shorting VDD and VSS pins to the core ring +set ::env(QUIT_ON_LVS_ERROR) "0"
diff --git a/openlane/sar_adc/pdn.tcl b/openlane/sar_adc/pdn.tcl new file mode 100644 index 0000000..de972f1 --- /dev/null +++ b/openlane/sar_adc/pdn.tcl
@@ -0,0 +1,130 @@ +# Power nets + +if { ! [info exists ::env(VDD_NET)] } { + set ::env(VDD_NET) $::env(VDD_PIN) +} + +if { ! [info exists ::env(GND_NET)] } { + set ::env(GND_NET) $::env(GND_PIN) +} + +set ::power_nets $::env(VDD_NET) +set ::ground_nets $::env(GND_NET) + +if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } { + if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } { + # to parameterize -- needs a PDNGEN fix + set pdngen::global_connections { + VPWR { + {inst_name .* pin_name VPWR} + {inst_name .* pin_name VPB} + } + VGND { + {inst_name .* pin_name VGND} + {inst_name .* pin_name VNB} + } + } + } +} + +# Used if the design is the core of the chip +set stdcell_core { + name grid + straps { + $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + $::env(FP_PDN_UPPER_LAYER) {width $::env(FP_PDN_HWIDTH) pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} + } + connect {{$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}} + pins { $::env(FP_PDN_UPPER_LAYER) } +} + +# Used if the design is a macro in the core +set stdcell_macro { + name grid + straps { + $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + $::env(FP_PDN_UPPER_LAYER) {width $::env(FP_PDN_HWIDTH) pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} + } + connect {{$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}} +} + +# Assesses whether the deisgn is the core of the chip or not based on the value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section +if { [info exists ::env(DESIGN_IS_CORE)] } { + if { $::env(DESIGN_IS_CORE) == 1 } { + set stdcell $stdcell_core + } else { + set stdcell $stdcell_macro + } +} else { + set stdcell $stdcell_core +} + +# Adds the core ring if enabled. +if { [info exists ::env(FP_PDN_CORE_RING)] } { + if { $::env(FP_PDN_CORE_RING) == 1 } { + dict append stdcell core_ring { + $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_CORE_RING_VWIDTH) spacing $::env(FP_PDN_CORE_RING_VSPACING) core_offset $::env(FP_PDN_CORE_RING_VOFFSET)} + } + } +} + +# Adds the core ring if enabled. +if { [info exists ::env(FP_PDN_ENABLE_RAILS)] } { + if { $::env(FP_PDN_ENABLE_RAILS) == 1 } { + dict append stdcell rails { + $::env(FP_PDN_RAILS_LAYER) {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)} + } + dict update stdcell connect current_connect { + append current_connect { {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}} + } + } else { + dict append stdcell rails {} + } +} + +pdngen::specify_grid stdcell [subst $stdcell] + +# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs +# TODO: generate automatically per instance: + +if { $::env(VDD_NET) == "vccd1" } { + set macro { + orient {R0 R180 MX MY R90 R270 MXR90 MYR90} + power_pins "$::env(VDD_NET)" + ground_pins "$::env(GND_NET)" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect {{met4_PIN_ver met5}} + } +} elseif { $::env(VDD_NET) == "vdda1" } { + set macro { + orient {R0 R180 MX MY R90 R270 MXR90 MYR90} + power_pins "vdda1" + ground_pins "vssa1" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect {{met4_PIN_ver met5}} + } +} else { + set macro { + orient {R0 R180 MX MY R90 R270 MXR90 MYR90} + power_pins "$::env(VDD_NET) vdd" + ground_pins "$::env(GND_NET) gnd" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect {{met4_PIN_ver met5}} + } +} + +pdngen::specify_grid macro [subst $macro] + +set ::halo [expr min($::env(FP_HORIZONTAL_HALO), $::env(FP_VERTICAL_HALO))] + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ; \ No newline at end of file
diff --git a/openlane/sar_adc/pin_order.cfg b/openlane/sar_adc/pin_order.cfg new file mode 100644 index 0000000..392a553 --- /dev/null +++ b/openlane/sar_adc/pin_order.cfg
@@ -0,0 +1,99 @@ +#BUS_SORT +#MANUAL_PLACE + +#S +clk +reset_n +pulse1m_mclk +reg_cs +reg_wr +reg_addr\[7\] +reg_addr\[6\] +reg_addr\[5\] +reg_addr\[4\] +reg_addr\[3\] +reg_addr\[2\] +reg_addr\[1\] +reg_addr\[0\] +reg_be\[3\] +reg_be\[2\] +reg_be\[1\] +reg_be\[0\] +reg_wdata\[31\] +reg_wdata\[30\] +reg_wdata\[29\] +reg_wdata\[28\] +reg_wdata\[27\] +reg_wdata\[26\] +reg_wdata\[25\] +reg_wdata\[24\] +reg_wdata\[23\] +reg_wdata\[22\] +reg_wdata\[21\] +reg_wdata\[20\] +reg_wdata\[19\] +reg_wdata\[18\] +reg_wdata\[17\] +reg_wdata\[16\] +reg_wdata\[15\] +reg_wdata\[14\] +reg_wdata\[13\] +reg_wdata\[12\] +reg_wdata\[11\] +reg_wdata\[10\] +reg_wdata\[9\] +reg_wdata\[8\] +reg_wdata\[7\] +reg_wdata\[6\] +reg_wdata\[5\] +reg_wdata\[4\] +reg_wdata\[3\] +reg_wdata\[2\] +reg_wdata\[1\] +reg_wdata\[0\] +reg_rdata\[31\] +reg_rdata\[30\] +reg_rdata\[29\] +reg_rdata\[28\] +reg_rdata\[27\] +reg_rdata\[26\] +reg_rdata\[25\] +reg_rdata\[24\] +reg_rdata\[23\] +reg_rdata\[22\] +reg_rdata\[21\] +reg_rdata\[20\] +reg_rdata\[19\] +reg_rdata\[18\] +reg_rdata\[17\] +reg_rdata\[16\] +reg_rdata\[15\] +reg_rdata\[14\] +reg_rdata\[13\] +reg_rdata\[12\] +reg_rdata\[11\] +reg_rdata\[10\] +reg_rdata\[9\] +reg_rdata\[8\] +reg_rdata\[7\] +reg_rdata\[6\] +reg_rdata\[5\] +reg_rdata\[4\] +reg_rdata\[3\] +reg_rdata\[2\] +reg_rdata\[1\] +reg_rdata\[0\] +reg_ack + + +#N +sar2dac\[7\] +sar2dac\[6\] +sar2dac\[5\] +sar2dac\[4\] +sar2dac\[3\] +sar2dac\[2\] +sar2dac\[1\] +sar2dac\[0\] +analog_din +analog_dac_out
diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc index a531c30..e151002 100644 --- a/openlane/spi_master/base.sdc +++ b/openlane/spi_master/base.sdc
@@ -27,7 +27,7 @@ ###################################### create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(WB_CLOCK_PERIOD) -create_generated_clock -name $::env(SPI_CLOCK_PORT) -source [get_ports $::env(WB_CLOCK_PORT)] -master_clock $::env(WB_CLOCK_PORT) -divide_by 2 -add -comment "SPI Clock Out" [get_port io_out[0]] +create_generated_clock -name $::env(SPI_CLOCK_PORT) -source [get_ports $::env(WB_CLOCK_PORT)] -master_clock $::env(WB_CLOCK_PORT) -divide_by 2 -add -comment "SPI Clock Out" [get_port spi_clk] set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6] set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6] @@ -53,49 +53,38 @@ set spi_input_delay_value [expr $::env(SPI_CLOCK_PERIOD) * 0.6] set spi_output_delay_value [expr $::env(SPI_CLOCK_PERIOD) * 0.6] -set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[3]] -set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[2]] -set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[1]] -set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[0]] +set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[3]] +set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[2]] +set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[1]] +set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[0]] -set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[3]] -set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[2]] -set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[1]] -set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[0]] +set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[3]] +set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[2]] +set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[1]] +set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[0]] #io_out[0] is spiclcok #set_output_delay $wb_output_delay_value -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[0]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[5]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[4]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[3]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[2]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[1]] +set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_csn0] +set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[3]] +set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[2]] +set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[1]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[5]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[4]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[3]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[2]] -set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[1]] -set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[5]] -set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[4]] -set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[3]] -set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[2]] -set_output_delay 0.0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[1]] +set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_csn0] +set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[3]] +set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[2]] +set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[1]] +set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[0]] # Chip select asserted multiple cycle eariler than spi clock -set_output_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[1]] +set_output_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_csn0] -set_output_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[5]] -set_output_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[4]] -set_output_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[3]] -set_output_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[2]] -set_output_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[1]] -set_clock_uncertainty -from $::env(SPI_CLOCK_PORT) -to $::env(SPI_CLOCK_PORT) -setup 0.800 -set_clock_uncertainty -from $::env(WB_CLOCK_PERIOD) -to $::env(WB_CLOCK_PERIOD) -setup 0.800 -set_clock_uncertainty -from $::env(SPI_CLOCK_PORT) -to $::env(SPI_CLOCK_PORT) -hold 0.050 -set_clock_uncertainty -from $::env(WB_CLOCK_PERIOD) -to $::env(WB_CLOCK_PERIOD) -hold 0.050 +set_clock_uncertainty -from $::env(SPI_CLOCK_PORT) -to $::env(SPI_CLOCK_PORT) -setup 0.800 +set_clock_uncertainty -from $::env(WB_CLOCK_PORT) -to $::env(WB_CLOCK_PORT) -setup 0.800 +set_clock_uncertainty -from $::env(SPI_CLOCK_PORT) -to $::env(SPI_CLOCK_PORT) -hold 0.050 +set_clock_uncertainty -from $::env(WB_CLOCK_PORT) -to $::env(WB_CLOCK_PORT) -hold 0.050 # TODO set this as parameter set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg index 63d486b..bfe29dc 100644 --- a/openlane/spi_master/pin_order.cfg +++ b/openlane/spi_master/pin_order.cfg
@@ -4,22 +4,6 @@ #W mclk 0000 0 rst_n -io_in\[3\] 0200 0 -io_out\[5\] -io_oeb\[5\] -io_in\[2\] -io_out\[4\] -io_oeb\[4\] -io_in\[1\] -io_out\[3\] -io_oeb\[3\] -io_in\[0\] -io_out\[2\] -io_oeb\[2\] -io_out\[1\] -io_oeb\[1\] -io_out\[0\] -io_oeb\[0\] #E spi_debug\[0\] 0000 0 @@ -55,6 +39,18 @@ spi_debug\[30\] spi_debug\[31\] +spi_sdi\[3\] 0200 0 +spi_sdi\[2\] +spi_sdi\[1\] +spi_sdi\[0\] +spi_sdo\[3\] +spi_sdo\[2\] +spi_sdo\[1\] +spi_sdo\[0\] +spi_clk +spi_csn0 +spi_oen + #S wbd_stb_i 0000 0 wbd_we_i 0000 1
diff --git a/openlane/uart_i2cm_usb/pin_order.cfg b/openlane/uart_i2cm_usb/pin_order.cfg index 394ddc6..36b397b 100644 --- a/openlane/uart_i2cm_usb/pin_order.cfg +++ b/openlane/uart_i2cm_usb/pin_order.cfg
@@ -4,20 +4,8 @@ #S app_clk 0000 0 usb_clk -uart_rstn -i2c_rstn -usb_rstn -uart_i2c_usb_sel\[1\] -uart_i2c_usb_sel\[0\] -io_in\[1\] -io_out\[1\] -io_oeb\[1\] -io_in\[0\] -io_out\[0\] -io_oeb\[0\] -#N -reg_cs 0000 0 +reg_cs reg_wr reg_addr\[3\] reg_addr\[2\] @@ -90,3 +78,26 @@ reg_rdata\[1\] reg_rdata\[0\] reg_ack + + +uart_rstn +i2c_rstn +usb_rstn +uart_i2c_usb_sel\[1\] +uart_i2c_usb_sel\[0\] +scl_pad_i +scl_pad_o +scl_pad_oen_o +sda_pad_i +sda_pad_o +sda_padoen_o +uart_rxd +uart_txd +usb_in_dp +usb_in_dn +usb_out_dp +usb_out_dn +usb_out_tx_oen + + +
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 908108a..05749d4 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -49,8 +49,8 @@ set ::env(PDN_CFG) $script_dir/pdn.tcl -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" +#set ::env(SDC_FILE) "$script_dir/base.sdc" +#set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" set ::env(SYNTH_READ_BLACKBOX_LIB) 1 @@ -58,33 +58,33 @@ set ::env(VERILOG_FILES_BLACKBOX) "\ $script_dir/../../verilog/gl/spi_master.v \ $script_dir/../../verilog/gl/wb_interconnect.v \ - $script_dir/../../verilog/gl/glbl_cfg.v \ + $script_dir/../../verilog/gl/pinmux.v \ + $script_dir/../../verilog/gl/sar_adc.v \ $script_dir/../../verilog/gl/uart_i2cm_usb.v \ - $script_dir/../../verilog/gl/sdram.v \ + $script_dir/../../verilog/rtl/sar_adc/DAC_8BIT.v \ $script_dir/../../verilog/gl/wb_host.v \ - $script_dir/../../verilog/gl/clk_skew_adjust.v \ $script_dir/../../verilog/gl/syntacore.v \ " set ::env(EXTRA_LEFS) "\ $lef_root/spi_master.lef \ - $lef_root/glbl_cfg.lef \ + $lef_root/pinmux.lef \ $lef_root/wb_interconnect.lef \ - $lef_root/sdram.lef \ $lef_root/uart_i2cm_usb.lef \ $lef_root/wb_host.lef \ - $lef_root/clk_skew_adjust.lef \ + $lef_root/sar_adc.lef \ + $lef_root/DAC_8BIT.lef \ $lef_root/syntacore.lef \ " set ::env(EXTRA_GDS_FILES) "\ $gds_root/spi_master.gds \ - $gds_root/glbl_cfg.gds \ + $gds_root/pinmux.gds \ $gds_root/wb_interconnect.gds \ $gds_root/uart_i2cm_usb.gds \ - $gds_root/sdram.gds \ $gds_root/wb_host.gds \ - $gds_root/clk_skew_adjust.gds \ + $gds_root/sar_adc.gds \ + $gds_root/DAC_8BIT.gds \ $gds_root/syntacore.gds \ " @@ -101,8 +101,8 @@ set ::env(VDD_PIN) [list {vdda1 vdda2 vccd1 vccd2}] set ::env(GND_PIN) [list {vssa1 vssa2 vssd1 vssd2}] -set ::env(VDD_NETS) [list {vccd1}] -set ::env(GND_NETS) [list {vssd1}] +set ::env(VDD_NETS) [list {vdda1 vdda2 vccd1 vccd2}] +set ::env(GND_NETS) [list {vssa1 vssa2 vssd1 vssd2}] @@ -127,7 +127,7 @@ set ::env(FP_PDN_HOFFSET) "5" -set ::env(FP_PDN_HPITCH) "80" +set ::env(FP_PDN_HPITCH) "120" set ::env(FP_PDN_HSPACING) "15" set ::env(FP_PDN_HWIDTH) "3" set ::env(FP_PDN_LOWER_LAYER) "met4" @@ -136,6 +136,6 @@ set ::env(FP_PDN_RAIL_WIDTH) "0.48" set ::env(FP_PDN_UPPER_LAYER) "met5" set ::env(FP_PDN_VOFFSET) "5" -set ::env(FP_PDN_VPITCH) "80" +set ::env(FP_PDN_VPITCH) "120" set ::env(FP_PDN_VSPACING) "15" set ::env(FP_PDN_VWIDTH) "3"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 890ad90..051c72b 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,17 +1,8 @@ u_spi_master 300 2700 N -u_sdram_ctrl 1000 2700 N -u_glbl_cfg 2000 2700 N +u_uart_i2c_usb 1000 2700 N +u_adc 2000 2700 N +u_dac 2000 3100 N u_riscv_top 500 800 N -u_uart_i2c_usb 2200 1000 N +u_pinmux 2200 1000 N u_intercon 300 2300 N u_wb_host 300 300 N -u_skew_wi 2600 2300 N -u_skew_riscv 500 600 N -u_skew_uart 2200 800 N -u_skew_spi 150 2700 N -u_skew_sdram 800 2700 N -u_skew_glbl 1850 2850 N -u_skew_wh 800 600 N -u_skew_sd_co 950 3300 N -u_skew_sd_ci 1100 3300 N -u_skew_sp_co 100 1800 N
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 6c64bb6..fe8cc0a 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -338,7 +338,10 @@ s3_wbd_adr_o\[2\] s3_wbd_adr_o\[1\] s3_wbd_adr_o\[0\] -s3_wbd_sel_o +s3_wbd_sel_o\[3\] +s3_wbd_sel_o\[2\] +s3_wbd_sel_o\[1\] +s3_wbd_sel_o\[0\] s3_wbd_dat_o\[31\] s3_wbd_dat_o\[30\] s3_wbd_dat_o\[29\]
diff --git a/verilog/rtl/lib/pulse_gen_type1.sv b/verilog/rtl/lib/pulse_gen_type1.sv new file mode 100644 index 0000000..838fe03 --- /dev/null +++ b/verilog/rtl/lib/pulse_gen_type1.sv
@@ -0,0 +1,37 @@ + +//------------------------------------------------------------------------ +// This module is used to generate 1ms and 1sec pulse based on 1us trigger +// pulse +//------------------------------------------------------------------------ + +module pulse_gen_type1( + output logic clk_pulse, + + input logic clk, + input logic reset_n, + input logic trigger +); + +parameter WD= 10; // This will count from 0 to 1023 +parameter MAX_CNT = 999; + +logic [WD-1:0] cnt; + +assign clk_pulse = (cnt == 0) && trigger; + +always @ (posedge clk or negedge reset_n) +begin + if (reset_n == 1'b0) begin + cnt <= 'b0; + end else begin + if(trigger) begin + if(cnt >= MAX_CNT) + cnt <= 0; + else + cnt <= cnt +1; + end + end +end + +endmodule +
diff --git a/verilog/rtl/lib/pulse_gen_type2.sv b/verilog/rtl/lib/pulse_gen_type2.sv new file mode 100644 index 0000000..9bc759e --- /dev/null +++ b/verilog/rtl/lib/pulse_gen_type2.sv
@@ -0,0 +1,36 @@ + +//------------------------------------------------------------------------ +// This module is used to generate 1us based on config value +//------------------------------------------------------------------------ + +module pulse_gen_type2 #(parameter WD = 10) + ( + output logic clk_pulse, + + input logic clk, + input logic reset_n, + input logic [WD-1:0] cfg_max_cnt +); + + +logic [WD-1:0] cnt; + + +always @ (posedge clk or negedge reset_n) +begin + if (reset_n == 1'b0) begin + cnt <= 'b0; + clk_pulse <= 'b0; + end else begin + if(cnt == cfg_max_cnt) begin + cnt <= 0; + clk_pulse <= 1'b1; + end else begin + cnt <= cnt +1; + clk_pulse <= 1'b0; + end + end +end + +endmodule +
diff --git a/verilog/rtl/lib/registers.v b/verilog/rtl/lib/registers.v index 44b2b1d..e4a87a1 100755 --- a/verilog/rtl/lib/registers.v +++ b/verilog/rtl/lib/registers.v
@@ -202,10 +202,7 @@ /********************************************************************* -** copyright message here. - -** module: generic register - + module: generic register ***********************************************************************/ module generic_register ( //List of Inputs @@ -245,10 +242,7 @@ /********************************************************************* -** copyright message here. - -** module: generic register - + module: generic interrupt status ***********************************************************************/ module generic_intr_stat_reg ( //inputs @@ -292,3 +286,44 @@ endmodule + +/********************************************************************* + module: generic 32b register +***********************************************************************/ +module gen_32b_reg ( + //List of Inputs + cs, + we, + data_in, + reset_n, + clk, + + //List of Outs + data_out + ); + + parameter RESET_DEFAULT = 32'h0; + input [3:0] we; + input cs; + input [31:0] data_in; + input reset_n; + input clk; + output [31:0] data_out; + + + reg [31:0] data_out; + +always @ (posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + data_out <= RESET_DEFAULT ; + end + else begin + if(cs && we[0]) data_out[7:0] <= data_in[7:0]; + if(cs && we[1]) data_out[15:8] <= data_in[15:8]; + if(cs && we[2]) data_out[23:16] <= data_in[23:16]; + if(cs && we[3]) data_out[31:24] <= data_in[31:24]; + end +end + + +endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_control.sv b/verilog/rtl/pinmux/src/gpio_control.sv new file mode 100644 index 0000000..4c917dc --- /dev/null +++ b/verilog/rtl/pinmux/src/gpio_control.sv
@@ -0,0 +1,44 @@ + +// GPIO Interrupt Generation +module gpio_intr ( + input logic mclk ,// System clk + input logic h_reset_n ,// system reset + input logic [31:0] gpio_prev_indata ,// previously captured GPIO I/P pins data + input logic [31:0] cfg_gpio_data_in ,// GPIO I/P pins data captured into this + input logic [31:0] cfg_gpio_out_data ,// GPIO statuc O/P data from config reg + input logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level + input logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt + input logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt + + + output logic [31:0] pad_gpio_out ,// GPIO O/P to the gpio cfg reg + output logic [31:0] gpio_int_event // to the cfg interrupt status reg + +); + + +integer i; +//----------------------------------------------------------------------- +// Logic for interrupt detection +//----------------------------------------------------------------------- + +reg [31:0] local_gpio_int_event; // to the cfg interrupt status reg +always @(cfg_gpio_data_in or cfg_gpio_negedge_int_sel or cfg_gpio_posedge_int_sel + or gpio_prev_indata) +begin + for (i=0; i<32; i=i+1) + begin + // looking for rising edge int + local_gpio_int_event[i] = ((cfg_gpio_posedge_int_sel[i] & ~gpio_prev_indata[i] + & cfg_gpio_data_in[i]) | + (cfg_gpio_negedge_int_sel[i] & gpio_prev_indata[i] & + ~cfg_gpio_data_in[i])); + // looking for falling edge int + end +end + +assign gpio_int_event = local_gpio_int_event[31:0]; // goes as O/P to the cfg reg + +assign pad_gpio_out = cfg_gpio_out_data[31:0] ;// O/P on the GPIO bus + +endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_intr.sv b/verilog/rtl/pinmux/src/gpio_intr.sv new file mode 100644 index 0000000..331918d --- /dev/null +++ b/verilog/rtl/pinmux/src/gpio_intr.sv
@@ -0,0 +1,43 @@ + +// GPIO Interrupt Generation +module gpio_intr ( + input logic mclk ,// System clk + input logic h_reset_n ,// system reset + input logic [31:0] gpio_prev_indata ,// previously captured GPIO I/P pins data + input logic [31:0] cfg_gpio_data_in ,// GPIO I/P pins data captured into this + input logic [31:0] cfg_gpio_out_data ,// GPIO statuc O/P data from config reg + input logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level + input logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt + input logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt + + + output logic [31:0] pad_gpio_out ,// GPIO O/P to the gpio cfg reg + output logic [31:0] gpio_int_event // to the cfg interrupt status reg + +); + + +integer i; +//----------------------------------------------------------------------- +// Logic for interrupt detection +//----------------------------------------------------------------------- + +reg [31:0] local_gpio_int_event; // to the cfg interrupt status reg +always_comb +begin + for (i=0; i<32; i=i+1) + begin + // looking for rising edge int + local_gpio_int_event[i] = ((cfg_gpio_posedge_int_sel[i] & ~gpio_prev_indata[i] + & cfg_gpio_data_in[i]) | + (cfg_gpio_negedge_int_sel[i] & gpio_prev_indata[i] & + ~cfg_gpio_data_in[i])); + // looking for falling edge int + end +end + +assign gpio_int_event = local_gpio_int_event[31:0]; // goes as O/P to the cfg reg + +assign pad_gpio_out = cfg_gpio_out_data[31:0] ;// O/P on the GPIO bus + +endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv new file mode 100755 index 0000000..2b284be --- /dev/null +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -0,0 +1,695 @@ +module pinmux ( + // System Signals + // Inputs + input logic mclk, + input logic h_reset_n, + + // Reg Bus Interface Signal + input logic reg_cs, + input logic reg_wr, + input logic [7:0] reg_addr, + input logic [31:0] reg_wdata, + input logic [3:0] reg_be, + + // Outputs + output logic [31:0] reg_rdata, + output logic reg_ack, + + // Risc configuration + output logic [31:0] fuse_mhartid, + output logic [15:0] irq_lines, + output logic soft_irq, + output logic [2:0] user_irq, + + // Digital IO + output logic [37:0] digital_io_out, + output logic [37:0] digital_io_oen, + input logic [37:0] digital_io_in, + + // SFLASH I/F + input logic sflash_sck, + input logic sflash_ss, + input logic sflash_oen, + input logic [3:0] sflash_do, + output logic [3:0] sflash_di, + + // SSRAM I/F + input logic ssram_sck, + input logic ssram_ss, + input logic ssram_oen, + input logic [3:0] ssram_do, + output logic [3:0] ssram_di, + + // USB I/F + input logic usb_dp_o, + input logic usb_dn_o, + input logic usb_oen, + output logic usb_dp_i, + output logic usb_dn_i, + + // UART I/F + input logic uart_txd, + output logic uart_rxd, + + // I2CM I/F + input logic i2cm_clk_o, + output logic i2cm_clk_i, + input logic i2cm_clk_oen, + input logic i2cm_data_oen, + input logic i2cm_data_o, + output logic i2cm_data_i, + + // SPI MASTER + input logic spim_sck, + input logic spim_ss, + input logic spim_miso, + output logic spim_mosi, + + output logic pulse1m_mclk, + output logic [31:0] pinmux_debug + ); + + + + +/* clock pulse */ +//******************************************************** +logic pulse1u_mclk ;// 1 UsSecond Pulse for waveform Generator +logic pulse1m_mclk ;// 1MilliSecond Pulse for waveform Generator +logic pulse1s_mclk ;// 1Second Pulse for waveform Generator +logic [9:0] cfg_pulse_1us ;// 1us pulse generation config + +//--------------------------------------------------- +// 6 PWM variabled +//--------------------------------------------------- + +logic [5:0] pwm_wfm ; +logic [5:0] cfg_pwm_enb ; +logic [15:0] cfg_pwm0_high ; +logic [15:0] cfg_pwm0_low ; +logic [15:0] cfg_pwm1_high ; +logic [15:0] cfg_pwm1_low ; +logic [15:0] cfg_pwm2_high ; +logic [15:0] cfg_pwm2_low ; +logic [15:0] cfg_pwm3_high ; +logic [15:0] cfg_pwm3_low ; +logic [15:0] cfg_pwm4_high ; +logic [15:0] cfg_pwm4_low ; +logic [15:0] cfg_pwm5_high ; +logic [15:0] cfg_pwm5_low ; + + +wire [31:0] gpio_prev_indata ;// previously captured GPIO I/P pins data +wire [31:0] cfg_gpio_out_data ;// GPIO statuc O/P data from config reg +wire [31:0] cfg_gpio_dir_sel ;// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output +wire [31:0] cfg_gpio_out_type ;// GPIO Type, Unused +wire [31:0] cfg_multi_func_sel ;// GPIO Multi function type +wire [31:0] cfg_gpio_posedge_int_sel ;// select posedge interrupt +wire [31:0] cfg_gpio_negedge_int_sel ;// select negedge interrupt +wire [31:00] cfg_gpio_data_in ; + + +reg [7:0] port_a_in; // PORT A Data In +reg [7:0] port_b_in; // PORT B Data In +reg [7:0] port_c_in; // PORT C Data In +reg [7:0] port_d_in; // PORT D Data In + +wire [7:0] port_a_out; // PORT A Data Out +wire [7:0] port_b_out; // PORT B Data Out +wire [7:0] port_c_out; // PORT C Data Out +wire [7:0] port_d_out; // PORT D Data Out +wire [31:0] pad_gpio_in; // GPIO data input from PAD +wire [31:0] pad_gpio_out; // GPIO Data out towards PAD +wire [31:0] gpio_int_event; // GPIO Interrupt indication +reg [1:0] ext_intr_in; // External PAD level interrupt + +// GPIO to PORT Mapping +assign pad_gpio_in[7:0] = port_a_in; +assign pad_gpio_in[15:8] = port_b_in; +assign pad_gpio_in[23:16] = port_c_in; +assign pad_gpio_in[31:24] = port_d_in; + +assign port_a_out = pad_gpio_out[7:0]; +assign port_b_out = pad_gpio_out[15:8]; +assign port_c_out = pad_gpio_out[23:16]; +assign port_d_out = pad_gpio_out[31:24]; + +assign pinmux_debug = '0; // Todo: Need to fix + +gpio_intr u_gpio_intr ( + // System Signals + // Inputs + .mclk (mclk ), + .h_reset_n (h_reset_n ), + + // GPIO cfg input pins + .gpio_prev_indata (gpio_prev_indata ), + .cfg_gpio_data_in (cfg_gpio_data_in ), + .cfg_gpio_dir_sel (cfg_gpio_dir_sel ), + .cfg_gpio_out_data (cfg_gpio_out_data ), + .cfg_gpio_posedge_int_sel(cfg_gpio_posedge_int_sel), + .cfg_gpio_negedge_int_sel(cfg_gpio_negedge_int_sel), + + + // GPIO output pins + .pad_gpio_out (pad_gpio_out ), + .gpio_int_event (gpio_int_event ) + ); + + +// 1us pulse +pulse_gen_type2 #(.WD(10)) u_pulse_1us ( + + .clk_pulse (pulse1u_mclk), + .clk (mclk ), + .reset_n (h_reset_n ), + .cfg_max_cnt (cfg_pulse_1us) + + ); + +// 1millisecond pulse +pulse_gen_type1 u_pulse_1ms ( + + .clk_pulse (pulse1m_mclk), + .clk (mclk ), + .reset_n (h_reset_n ), + .trigger (pulse1u_mclk) + + ); + +// 1 second pulse +pulse_gen_type2 u_pulse_1s ( + + .clk_pulse (pulse1s_mclk), + .clk (mclk ), + .reset_n (h_reset_n ), + .cfg_max_cnt (cfg_pulse_1us) + + ); + +pinmux_reg u_pinmux_reg( + // System Signals + // Inputs + .mclk (mclk ), + .h_reset_n (h_reset_n ), + + + // Reg read/write Interface Inputs + .reg_cs (reg_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr ), + .reg_wdata (reg_wdata ), + .reg_be (reg_be ), + + .reg_rdata (reg_rdata ), + .reg_ack (reg_ack ), + + .ext_intr_in (ext_intr_in ), + + .fuse_mhartid (fuse_mhartid ), + .irq_lines (irq_lines ), + .soft_irq (soft_irq ), + .user_irq (user_irq ), + + .cfg_pulse_1us (cfg_pulse_1us ), + + + .cfg_pwm0_high (cfg_pwm0_high ), + .cfg_pwm0_low (cfg_pwm0_low ), + .cfg_pwm1_high (cfg_pwm1_high ), + .cfg_pwm1_low (cfg_pwm1_low ), + .cfg_pwm2_high (cfg_pwm2_high ), + .cfg_pwm2_low (cfg_pwm2_low ), + .cfg_pwm3_high (cfg_pwm3_high ), + .cfg_pwm3_low (cfg_pwm3_low ), + .cfg_pwm4_high (cfg_pwm4_high ), + .cfg_pwm4_low (cfg_pwm4_low ), + .cfg_pwm5_high (cfg_pwm5_high ), + .cfg_pwm5_low (cfg_pwm5_low ), + + // GPIO input pins + .gpio_in_data (pad_gpio_in ), + .gpio_int_event (gpio_int_event ), + + // GPIO config pins + .cfg_gpio_out_data (cfg_gpio_out_data ), + .cfg_gpio_dir_sel (cfg_gpio_dir_sel ), + .cfg_gpio_out_type (cfg_gpio_out_type ), + .cfg_gpio_posedge_int_sel (cfg_gpio_posedge_int_sel), + .cfg_gpio_negedge_int_sel (cfg_gpio_negedge_int_sel), + .cfg_multi_func_sel (cfg_multi_func_sel ), + .cfg_gpio_data_in (cfg_gpio_data_in ), + + + // Outputs + .gpio_prev_indata (gpio_prev_indata ) + ); + + +// 6 PWM Waveform Generator +pwm u_pwm_0 ( + .waveform (pwm_wfm[0] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse1m_mclk ), + .cfg_pwm_enb (cfg_pwm_enb[0] ), + .cfg_pwm_high (cfg_pwm0_high ), + .cfg_pwm_low (cfg_pwm0_low ) + ); + +pwm u_pwm_1 ( + .waveform (pwm_wfm[1] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse1m_mclk ), + .cfg_pwm_enb (cfg_pwm_enb[1] ), + .cfg_pwm_high (cfg_pwm1_high ), + .cfg_pwm_low (cfg_pwm1_low ) + ); + +pwm u_pwm_2 ( + .waveform (pwm_wfm[2] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse1m_mclk ), + .cfg_pwm_enb (cfg_pwm_enb[2] ), + .cfg_pwm_high (cfg_pwm2_high ), + .cfg_pwm_low (cfg_pwm2_low ) + ); + +pwm u_pwm_3 ( + .waveform (pwm_wfm[3] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse1m_mclk ), + .cfg_pwm_enb (cfg_pwm_enb[3] ), + .cfg_pwm_high (cfg_pwm3_high ), + .cfg_pwm_low (cfg_pwm3_low ) + ); +pwm u_pwm_4 ( + .waveform (pwm_wfm[4] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse1m_mclk ), + .cfg_pwm_enb (cfg_pwm_enb[4] ), + .cfg_pwm_high (cfg_pwm4_high ), + .cfg_pwm_low (cfg_pwm4_low ) + ); +pwm u_pwm_5 ( + .waveform (pwm_wfm[5] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse1m_mclk ), + .cfg_pwm_enb (cfg_pwm_enb[5] ), + .cfg_pwm_high (cfg_pwm5_high ), + .cfg_pwm_low (cfg_pwm5_low ) + ); + +/************************************************ +* Pin Mapping ATMGE CONFIG +* ATMEGA328 caravel Pin Mapping +* Pin-1 PC6/RESET* digital_io[0] +* Pin-2 PD0/RXD digital_io[1] +* Pin-3 PD1/TXD digital_io[2] +* Pin-4 PD2/INT0 digital_io[3] +* Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] +* Pin-6 PD4 digital_io[5] +* Pin-7 VCC - +* Pin-8 GND - +* Pin-9 PB6/XTAL1/TOSC1 digital_io[6] +* Pin-10 PB7/XTAL2/TOSC2 digital_io[7] +* Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] +* Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] +* Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] +* Pin-14 PB0/CLKO/ICP1 digital_io[11] +* Pin-15 PB1/OC1A(PWM3) digital_io[12] +* Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] +* Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] +* Pin-18 PB4/MISO digital_io[15] +* Pin-19 PB5/SCK digital_io[16] +* Pin-20 AVCC - +* Pin-21 AREF analog_io[10] +* Pin-22 GND - +* Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] +* Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] +* Pin-25 PC2/ADC2 digital_io[20]/analog_io[13] +* Pin-26 PC3/ADC3 digital_io[21]/analog_io[14] +* Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15] +* Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16] +* +* Additional Pad used for Externam ROM/RAM +* sflash_sck digital_io[24] +* sflash_ss digital_io[25] +* sflash_io0 digital_io[26] +* sflash_io1 digital_io[27] +* sflash_io2 digital_io[28] +* sflash_io3 digital_io[29] +* +* ssram_sck digital_io[30] +* ssram_ss digital_io[31] +* ssram_io0 digital_io[32] +* ssram_io1 digital_io[33] +* ssram_io2 digital_io[34] +* ssram_io3 digital_io[35] +* +* usb_dp digital_io[36] +* usb_dn digital_io[37] +**************************************************************** +* Pin-1 RESET is not supported as there is no suppport for fuse config +**************/ + +assign cfg_pwm_enb = cfg_multi_func_sel[5:0]; +wire [1:0] cfg_int_enb = cfg_multi_func_sel[7:6]; +wire cfg_uart_enb = cfg_multi_func_sel[8]; +wire cfg_i2cm_enb = cfg_multi_func_sel[9]; +wire cfg_spim_enb = cfg_multi_func_sel[10]; + +wire [7:0] cfg_port_a_dir_sel = cfg_gpio_dir_sel[7:0]; +wire [7:0] cfg_port_b_dir_sel = cfg_gpio_dir_sel[15:8]; +wire [7:0] cfg_port_c_dir_sel = cfg_gpio_dir_sel[23:16]; +wire [7:0] cfg_port_d_dir_sel = cfg_gpio_dir_sel[31:24]; + + +// datain selection +always_comb begin + port_a_in = 'h0; + port_b_in = 'h0; + port_c_in = 'h0; + port_d_in = 'h0; + uart_rxd = 'h0; + ext_intr_in= 'h0; + spim_mosi = 'h0; + i2cm_data_i= 'h0; + i2cm_clk_i = 'h0; + + //Pin-1 PC6/RESET* digital_io[0] + port_c_in[6] = digital_io_in[0]; + + //Pin-2 PD0/RXD digital_io[1] + port_d_in[0] = digital_io_in[1]; + if(cfg_uart_enb) uart_rxd = digital_io_in[1]; + + //Pin-3 PD1/TXD digital_io[2] + port_d_in[1] = digital_io_in[2]; + + + //Pin-4 PD2/INT0 digital_io[3] + port_d_in[2] = digital_io_in[3]; + if(cfg_int_enb[0]) ext_intr_in[0] = digital_io_in[3]; + + //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] + port_d_in[3] = digital_io_in[4]; + if(cfg_int_enb[1]) ext_intr_in[1] = digital_io_in[4]; + + //Pin-6 PD4 digital_io[5] + port_d_in[4] = digital_io_in[5]; + + //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] + port_b_in[6] = digital_io_in[6]; + + // Pin-10 PB7/XTAL2/TOSC2 digital_io[7] + port_b_in[7] = digital_io_in[7]; + + //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] + port_d_in[5] = digital_io_in[8]; + + //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] + port_d_in[6] = digital_io_in[9]; + + //Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] + port_d_in[7] = digital_io_in[10]; + + //Pin-14 PB0/CLKO/ICP1 digital_io[11] + port_b_in[0] = digital_io_in[11]; + + //Pin-15 PB1/OC1A(PWM3) digital_io[12] + port_b_in[1] = digital_io_in[12]; + + //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] + port_b_in[2] = digital_io_in[13]; + + //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] + port_b_in[3] = digital_io_in[14]; + if(cfg_spim_enb) spim_mosi = digital_io_in[14]; + + //Pin-18 PB4/MISO digital_io[15] + port_b_in[4] = digital_io_in[15]; + + //Pin-19 PB5/SCK digital_io[16] + port_b_in[5]= digital_io_in[16]; + + //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] + port_c_in[0] = digital_io_in[18]; + + //Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] + port_c_in[1] = digital_io_in[19]; + + //Pin-25 PC2/ADC2 digital_io[20]/analog_io[13] + port_c_in[2] = digital_io_in[20]; + + //Pin-26 PC3/ADC3 digital_io[21]/analog_io[14] + port_c_in[3] = digital_io_in[21]; + + //Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15] + port_c_in[4] = digital_io_in[22]; + if(cfg_i2cm_enb) i2cm_data_i = digital_io_in[22]; + + //Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16] + port_c_in[5] = digital_io_in[23]; + if(cfg_i2cm_enb) i2cm_clk_i = digital_io_in[23]; + + sflash_di[0] = digital_io_in[26]; + sflash_di[1] = digital_io_in[27]; + sflash_di[2] = digital_io_in[28]; + sflash_di[3] = digital_io_in[29]; + + ssram_di[0] = digital_io_in[32]; + ssram_di[1] = digital_io_in[33]; + ssram_di[2] = digital_io_in[34]; + ssram_di[3] = digital_io_in[35]; + + usb_dp_i = digital_io_in[36]; + usb_dn_i = digital_io_in[37]; +end + +// dataout selection +always_comb begin + digital_io_out = 'h0; + //Pin-1 PC6/RESET* digital_io[0] + if(cfg_port_c_dir_sel[6]) digital_io_out[0] = port_c_out[6]; + + //Pin-2 PD0/RXD digital_io[1] + if(cfg_port_d_dir_sel[0]) digital_io_out[1] = port_d_out[0]; + + //Pin-3 PD1/TXD digital_io[2] + if (cfg_uart_enb) digital_io_out[2] = uart_txd; + else if(cfg_port_d_dir_sel[1]) digital_io_out[2] = port_d_out[1]; + + + //Pin-4 PD2/INT0 digital_io[3] + if(cfg_port_d_dir_sel[2]) digital_io_out[3] = port_d_out[2]; + + //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] + if(cfg_pwm_enb[0]) digital_io_out[4] = pwm_wfm[0]; + if(cfg_port_d_dir_sel[3]) digital_io_out[4] = port_d_out[3]; + + //Pin-6 PD4 digital_io[5] + if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4]; + + //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] + if(cfg_port_b_dir_sel[6]) digital_io_out[6] = port_b_out[6]; + + + // Pin-10 PB7/XTAL2/TOSC2 digital_io[7] + if(cfg_port_b_dir_sel[7]) digital_io_out[7] = port_b_out[7]; + + //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] + if(cfg_pwm_enb[1]) digital_io_out[8] = pwm_wfm[1]; + else if(cfg_port_d_dir_sel[5]) digital_io_out[8] = port_d_out[5]; + + //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] + if(cfg_pwm_enb[2]) digital_io_out[9] = pwm_wfm[2]; + else if(cfg_port_d_dir_sel[6]) digital_io_out[9] = port_d_out[6]; + + + //Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] + if(cfg_port_d_dir_sel[7]) digital_io_out[10] = port_d_out[7]; + + //Pin-14 PB0/CLKO/ICP1 digital_io[11] + if(cfg_port_b_dir_sel[0]) digital_io_out[11] = port_b_out[0]; + + //Pin-15 PB1/OC1A(PWM3) digital_io[12] + if(cfg_pwm_enb[3]) digital_io_out[12] = pwm_wfm[3]; + else if(cfg_port_b_dir_sel[1]) digital_io_out[12] = port_b_out[1]; + + //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] + if(cfg_pwm_enb[4]) digital_io_out[13] = pwm_wfm[4]; + else if(cfg_spim_enb) digital_io_out[13] = spim_ss; + else if(cfg_port_b_dir_sel[2]) digital_io_out[13] = port_b_out[2]; + + //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] + if(cfg_pwm_enb[5]) digital_io_out[14] = pwm_wfm[5]; + else if(cfg_port_b_dir_sel[3]) digital_io_out[14] = port_b_out[3]; + + //Pin-18 PB4/MISO digital_io[15] + if(cfg_spim_enb) digital_io_out[15] = spim_miso; + else if(cfg_port_b_dir_sel[4]) digital_io_out[15] = port_b_out[4]; + + //Pin-19 PB5/SCK digital_io[16] + if(cfg_spim_enb) digital_io_out[16] = spim_sck; + else if(cfg_port_b_dir_sel[5]) digital_io_out[16] = port_b_out[5]; + + //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] + if(cfg_port_c_dir_sel[0]) digital_io_out[18] = port_c_out[0]; + + //Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] + if(cfg_port_c_dir_sel[1]) digital_io_out[19] = port_c_out[1]; + + //Pin-25 PC2/ADC2 digital_io[20]/analog_io[13] + if(cfg_port_c_dir_sel[2]) digital_io_out[20] = port_c_out[2]; + + //Pin-26 PC3/ADC3 digital_io[21]/analog_io[14] + if(cfg_port_c_dir_sel[3]) digital_io_out[21] = port_c_out[3]; + + //Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15] + if(cfg_i2cm_enb) digital_io_out[22] = i2cm_data_o; + else if(cfg_port_c_dir_sel[4]) digital_io_out[22] = port_c_out[4]; + + //Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16] + if(cfg_i2cm_enb) digital_io_out[23] = i2cm_clk_o; + else if(cfg_port_c_dir_sel[5]) digital_io_out[23] = port_c_out[5]; + + // Serial Flash + digital_io_out[24] = sflash_sck ; + digital_io_out[25] = sflash_ss ; + digital_io_out[26] = sflash_do[0] ; + digital_io_out[27] = sflash_do[1] ; + digital_io_out[28] = sflash_do[2] ; + digital_io_out[29] = sflash_do[3] ; + + // Serail SRAM + digital_io_out[30] = ssram_sck ; + digital_io_out[31] = ssram_ss ; + digital_io_out[32] = ssram_do[0] ; + digital_io_out[33] = ssram_do[1] ; + digital_io_out[34] = ssram_do[2] ; + digital_io_out[35] = ssram_do[3] ; + + // USB 1.1 + digital_io_out[36] = usb_dp_o ; + digital_io_out[37] = usb_dn_o ; +end + +// dataoen selection +always_comb begin + digital_io_oen = 38'h3F_FFFF_FFFF; + //Pin-1 PC6/RESET* digital_io[0] + if(cfg_port_c_dir_sel[6]) digital_io_oen[0] = 1'b0; + + //Pin-2 PD0/RXD digital_io[1] + if (cfg_uart_enb) digital_io_oen[1] = 1'b1; + else if(cfg_port_d_dir_sel[0]) digital_io_oen[1] = 1'b0; + + //Pin-3 PD1/TXD digital_io[2] + if (cfg_uart_enb) digital_io_oen[2] = 1'b0; + else if(cfg_port_d_dir_sel[1]) digital_io_oen[2] = 1'b0; + + //Pin-4 PD2/INT0 digital_io[3] + if(cfg_int_enb[0]) digital_io_oen[3] = 1'b1; + else if(cfg_port_d_dir_sel[2]) digital_io_oen[3] = 1'b0; + + //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] + if(cfg_pwm_enb[0]) digital_io_oen[4] = 1'b0; + else if(cfg_int_enb[1]) digital_io_oen[4] = 1'b1; + else if(cfg_port_d_dir_sel[3]) digital_io_oen[4] = 1'b0; + + //Pin-6 PD4 digital_io[5] + if(cfg_port_d_dir_sel[4]) digital_io_oen[5] = 1'b0; + + //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] + if(cfg_port_b_dir_sel[6]) digital_io_oen[6] = 1'b0; + + // Pin-10 PB7/XTAL2/TOSC2 digital_io[7] + if(cfg_port_b_dir_sel[7]) digital_io_oen[7] = 1'b0; + + //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] + if(cfg_pwm_enb[1]) digital_io_oen[8] = 1'b0; + else if(cfg_port_d_dir_sel[5]) digital_io_oen[8] = 1'b0; + + //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] + if(cfg_pwm_enb[2]) digital_io_oen[9] = 1'b0; + else if(cfg_port_d_dir_sel[6]) digital_io_oen[9] = 1'b0; + + //Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] + if(cfg_port_d_dir_sel[7]) digital_io_oen[10] = 1'b0; + + //Pin-14 PB0/CLKO/ICP1 digital_io[11] + if(cfg_port_b_dir_sel[0]) digital_io_oen[11] = 1'b0; + + //Pin-15 PB1/OC1A(PWM3) digital_io[12] + if(cfg_pwm_enb[3]) digital_io_oen[12] = 1'b0; + else if(cfg_port_b_dir_sel[1]) digital_io_oen[12] = 1'b0; + + //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] + if(cfg_pwm_enb[4]) digital_io_oen[13] = 1'b0; + else if(cfg_spim_enb) digital_io_oen[13] = 1'b0; + else if(cfg_port_b_dir_sel[2]) digital_io_oen[13] = 1'b0; + + //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] + if(cfg_spim_enb) digital_io_oen[14] = 1'b1; + else if(cfg_pwm_enb[5]) digital_io_oen[14] = 1'b0; + else if(cfg_port_b_dir_sel[3]) digital_io_oen[14] = 1'b0; + + //Pin-18 PB4/MISO digital_io[15] + if(cfg_spim_enb) digital_io_oen[15] = 1'b0; + else if(cfg_port_b_dir_sel[4]) digital_io_oen[15] = 1'b0; + + //Pin-19 PB5/SCK digital_io[16] + if(cfg_spim_enb) digital_io_oen[16] = 1'b0; + else if(cfg_port_b_dir_sel[5]) digital_io_oen[16] = 1'b0; + + //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] + if(cfg_port_c_dir_sel[0]) digital_io_oen[18] = 1'b0; + + //Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] + if(cfg_port_c_dir_sel[1]) digital_io_oen[19] = 1'b0; + + //Pin-25 PC2/ADC2 digital_io[20]/analog_io[13] + if(cfg_port_c_dir_sel[2]) digital_io_oen[20] = 1'b0; + + //Pin-26 PC3/ADC3 digital_io[21]/analog_io[14] + if(cfg_port_c_dir_sel[3]) digital_io_oen[21] = 1'b0; + + //Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15] + if(cfg_i2cm_enb) digital_io_oen[22] = i2cm_data_oen; + else if(cfg_port_c_dir_sel[4]) digital_io_oen[22] = 1'b0; + + //Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16] + if(cfg_i2cm_enb) digital_io_oen[23] = i2cm_clk_oen; + else if(cfg_port_c_dir_sel[5]) digital_io_oen[23] = 1'b0; + + // Serial Flash + digital_io_oen[24] = 1'b0 ; + digital_io_oen[25] = 1'b0 ; + digital_io_oen[26] = sflash_oen; + digital_io_oen[27] = sflash_oen; + digital_io_oen[28] = sflash_oen; + digital_io_oen[29] = sflash_oen; + + // Serail SRAM + digital_io_oen[30] = 1'b0 ; + digital_io_oen[31] = 1'b0 ; + digital_io_oen[32] = ssram_oen; + digital_io_oen[33] = ssram_oen; + digital_io_oen[34] = ssram_oen; + digital_io_oen[35] = ssram_oen; + + // USB 1.1 + digital_io_oen[36] = usb_oen; + digital_io_oen[37] = usb_oen; +end + + +endmodule + +
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv new file mode 100644 index 0000000..eba780d --- /dev/null +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -0,0 +1,666 @@ + +module pinmux_reg ( + // System Signals + // Inputs + input logic mclk, + input logic h_reset_n, + + // Reg Bus Interface Signal + input logic reg_cs, + input logic reg_wr, + input logic [7:0] reg_addr, + input logic [31:0] reg_wdata, + input logic [3:0] reg_be, + + // Outputs + output logic [31:0] reg_rdata, + output logic reg_ack, + + input logic [1:0] ext_intr_in, + + // Risc configuration + output logic [31:0] fuse_mhartid, + output logic [15:0] irq_lines, + output logic soft_irq, + output logic [2:0] user_irq, + + output logic [9:0] cfg_pulse_1us, + + //--------------------------------------------------- + // 6 PWM Configuration + //--------------------------------------------------- + + output logic [15:0] cfg_pwm0_high , + output logic [15:0] cfg_pwm0_low , + output logic [15:0] cfg_pwm1_high , + output logic [15:0] cfg_pwm1_low , + output logic [15:0] cfg_pwm2_high , + output logic [15:0] cfg_pwm2_low , + output logic [15:0] cfg_pwm3_high , + output logic [15:0] cfg_pwm3_low , + output logic [15:0] cfg_pwm4_high , + output logic [15:0] cfg_pwm4_low , + output logic [15:0] cfg_pwm5_high , + output logic [15:0] cfg_pwm5_low , + + // GPIO input pins + input logic [31:0] gpio_in_data ,// GPIO I/P pins + input logic [31:0] gpio_int_event ,// from gpio control blk + + + + // GPIO config pins + output logic [31:0] cfg_gpio_out_data ,// to the GPIO control block + output logic [31:0] cfg_gpio_data_in ,// GPIO I/P pins data captured into this + output logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level + output logic [31:0] cfg_gpio_out_type ,// O/P is static , '1' : waveform + output logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt + output logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt + output logic [31:0] cfg_multi_func_sel ,// multifunction pins + + // Outputs + output logic [31:0] gpio_prev_indata // prv data from GPIO I/P pins + ); + + + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +reg sw_rd_en ; +reg sw_wr_en; +reg [4:0] sw_addr; // addressing 16 registers +reg [31:0] sw_reg_wdata; +reg [3:0] wr_be ; +reg reg_cs_l; +reg reg_cs_2l; + +reg [31:0] reg_out; + +wire [31:0] reg_0; // Chip ID +wire [31:0] reg_1; // Risc Fuse Id +reg [31:0] reg_2; // GPIO Read Data +reg [31:0] reg_3; // GPIO Output Data +reg [31:0] reg_4; // GPIO Dir Sel +reg [31:0] reg_5; // GPIO Type +reg [31:0] reg_6; // Interrupt +reg [31:0] reg_7; // +reg [31:0] reg_8; // +reg [31:0] reg_9; // GPIO Interrupt Status +wire [31:0] reg_10; // GPIO Interrupt Status +reg [31:0] reg_11; // GPIO Interrupt Mask +reg [31:0] reg_12; // GPIO Posedge Interrupt Select +reg [31:0] reg_13; // GPIO Negedge Interrupt Select +reg [31:0] reg_14; // Software-Reg_14 +reg [31:0] reg_15; // Software-Reg_15 +reg [31:0] reg_16; // PWN-0 Config +reg [31:0] reg_17; // PWN-1 Config +reg [31:0] reg_18; // PWN-2 Config +reg [31:0] reg_19; // PWN-3 Config +reg [31:0] reg_20; // PWN-4 Config +reg [31:0] reg_21; // PWN-5 Config + + +reg cs_int; +wire gpio_intr; + + + +//----------------------------------------------------------------------- +// To avoid interface timing, all the content are registered +//----------------------------------------------------------------------- +always @ (posedge mclk or negedge h_reset_n) +begin + if (h_reset_n == 1'b0) + begin + sw_addr <= '0; + sw_rd_en <= '0; + sw_wr_en <= '0; + sw_reg_wdata <= '0; + wr_be <= '0; + reg_cs_l <= '0; + reg_cs_2l <= '0; + end else begin + sw_addr <= reg_addr [6:2]; + sw_rd_en <= reg_cs & !reg_wr; + sw_wr_en <= reg_cs & reg_wr; + sw_reg_wdata <= reg_wdata; + wr_be <= reg_be; + reg_cs_l <= reg_cs; + reg_cs_2l <= reg_cs_l; + end +end + + +//----------------------------------------------------------------------- +// Read path mux +//----------------------------------------------------------------------- + +always @ (posedge mclk or negedge h_reset_n) +begin : preg_out_Seq + if (h_reset_n == 1'b0) begin + reg_rdata [31:0] <= 32'h0000_0000; + reg_ack <= 1'b0; + end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin + reg_rdata [31:0] <= reg_out [31:0]; + reg_ack <= 1'b1; + end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin + reg_ack <= 1'b1; + end else begin + reg_ack <= 1'b0; + end +end + + +//----------------------------------------------------------------------- +// register read enable and write enable decoding logic +//----------------------------------------------------------------------- +wire sw_wr_en_0 = sw_wr_en & (sw_addr == 5'h0); +wire sw_rd_en_0 = sw_rd_en & (sw_addr == 5'h0); +wire sw_wr_en_1 = sw_wr_en & (sw_addr == 5'h1); +wire sw_rd_en_1 = sw_rd_en & (sw_addr == 5'h1); +wire sw_wr_en_2 = sw_wr_en & (sw_addr == 5'h2); +wire sw_rd_en_2 = sw_rd_en & (sw_addr == 5'h2); +wire sw_wr_en_3 = sw_wr_en & (sw_addr == 5'h3); +wire sw_rd_en_3 = sw_rd_en & (sw_addr == 5'h3); +wire sw_wr_en_4 = sw_wr_en & (sw_addr == 5'h4); +wire sw_rd_en_4 = sw_rd_en & (sw_addr == 5'h4); +wire sw_wr_en_5 = sw_wr_en & (sw_addr == 5'h5); +wire sw_rd_en_5 = sw_rd_en & (sw_addr == 5'h5); +wire sw_wr_en_6 = sw_wr_en & (sw_addr == 5'h6); +wire sw_rd_en_6 = sw_rd_en & (sw_addr == 5'h6); +wire sw_wr_en_7 = sw_wr_en & (sw_addr == 5'h7); +wire sw_rd_en_7 = sw_rd_en & (sw_addr == 5'h7); +wire sw_wr_en_8 = sw_wr_en & (sw_addr == 5'h8); +wire sw_rd_en_8 = sw_rd_en & (sw_addr == 5'h8); +wire sw_wr_en_9 = sw_wr_en & (sw_addr == 5'h9); +wire sw_rd_en_9 = sw_rd_en & (sw_addr == 5'h9); +wire sw_wr_en_10 = sw_wr_en & (sw_addr == 5'hA); +wire sw_rd_en_10 = sw_rd_en & (sw_addr == 5'hA); +wire sw_wr_en_11 = sw_wr_en & (sw_addr == 5'hB); +wire sw_rd_en_11 = sw_rd_en & (sw_addr == 5'hB); +wire sw_wr_en_12 = sw_wr_en & (sw_addr == 5'hC); +wire sw_rd_en_12 = sw_rd_en & (sw_addr == 5'hC); +wire sw_wr_en_13 = sw_wr_en & (sw_addr == 5'hD); +wire sw_rd_en_13 = sw_rd_en & (sw_addr == 5'hD); +wire sw_wr_en_14 = sw_wr_en & (sw_addr == 5'hE); +wire sw_rd_en_14 = sw_rd_en & (sw_addr == 5'hE); +wire sw_wr_en_15 = sw_wr_en & (sw_addr == 5'hF); +wire sw_rd_en_15 = sw_rd_en & (sw_addr == 5'hF); +wire sw_wr_en_16 = sw_wr_en & (sw_addr == 5'h10); +wire sw_rd_en_16 = sw_rd_en & (sw_addr == 5'h10); +wire sw_wr_en_17 = sw_wr_en & (sw_addr == 5'h11); +wire sw_rd_en_17 = sw_rd_en & (sw_addr == 5'h11); +wire sw_wr_en_18 = sw_wr_en & (sw_addr == 5'h12); +wire sw_rd_en_18 = sw_rd_en & (sw_addr == 5'h12); +wire sw_wr_en_19 = sw_wr_en & (sw_addr == 5'h13); +wire sw_rd_en_19 = sw_rd_en & (sw_addr == 5'h13); +wire sw_wr_en_20 = sw_wr_en & (sw_addr == 5'h14); +wire sw_rd_en_20 = sw_rd_en & (sw_addr == 5'h14); +wire sw_wr_en_21 = sw_wr_en & (sw_addr == 5'h15); +wire sw_rd_en_21 = sw_rd_en & (sw_addr == 5'h15); + + + +//----------------------------------------------------------------------- +// Individual register assignments +//----------------------------------------------------------------------- + +// Chip ID +wire [15:0] manu_id = 16'h8949; // Asci value of YI +wire [7:0] chip_id = 8'h02; +wire [7:0] chip_rev = 8'h01; + +assign reg_0 = {manu_id,chip_id,chip_rev}; + + +//----------------------------------------------------------------------- +// reg-1, reset value = 32'hA55A_A55A +// ----------------------------------------------------------------- + +gen_32b_reg #(32'hA55A_A55A) u_reg_1 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_1 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_1 ) + ); + +assign fuse_mhartid = reg_1; + +//----------------------------------------------------------------------- +// Logic for gpio_data_in +//----------------------------------------------------------------------- +logic [31:0] gpio_in_data_s; +logic [31:0] gpio_in_data_ss; +// Double Sync the gpio pin data for edge detection +always @ (posedge mclk or negedge h_reset_n) +begin + if (h_reset_n == 1'b0) begin + reg_2 <= 'h0 ; + gpio_in_data_s <= 32'd0; + gpio_in_data_ss <= 32'd0; + end + else begin + gpio_in_data_s <= gpio_in_data; + gpio_in_data_ss <= gpio_in_data_s; + reg_2 <= gpio_in_data_ss; + end +end + + +assign cfg_gpio_data_in = reg_2[31:0]; // to be used for edge interrupt detect +assign gpio_prev_indata = gpio_in_data_ss; + +//----------------------------------------------------------------------- +// Logic for cfg_gpio_out_data +//----------------------------------------------------------------------- +assign cfg_gpio_out_data = reg_3[31:0]; // data to the GPIO control blk + +gen_32b_reg #(32'h0) u_reg_3 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_3 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_3 ) + ); +//----------------------------------------------------------------------- +// Logic for cfg_gpio_dir_sel +//----------------------------------------------------------------------- +assign cfg_gpio_dir_sel = reg_4[31:0]; // data to the GPIO O/P pins + +gen_32b_reg #(32'h0) u_reg_4 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_4 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_4 ) + ); +//----------------------------------------------------------------------- +// Logic for cfg_gpio_out_type +//----------------------------------------------------------------------- +assign cfg_gpio_out_type = reg_5[31:0]; // to be used for read + +gen_32b_reg #(32'h0) u_reg_5 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_5 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_5 ) + ); + + +//----------------------------------------------------------------------- +// reg-6 +//----------------------------------------------------------------- +assign irq_lines = reg_6[15:0]; +assign soft_irq = reg_6[16]; +assign user_irq = {gpio_intr,ext_intr_in}; + +generic_register #(8,0 ) u_reg6_be0 ( + .we ({8{sw_wr_en_6 & + wr_be[0] }} ), + .data_in (sw_reg_wdata[7:0] ), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_6[7:0] ) + ); + +generic_register #(8,0 ) u_reg6_be1 ( + .we ({8{sw_wr_en_6 & + wr_be[1] }} ), + .data_in (sw_reg_wdata[15:8]), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_6[15:8] ) + ); + +assign reg_6[31:16] = '0; + +// Register-7 +gen_32b_reg #(32'h0) u_reg_7 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_7 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_7 ) + ); + +assign cfg_pulse_1us = reg_7[9:0]; + +//----------------------------------------------------------------------- +// Logic for cfg_int_status +// Always update int_status, even if no register write is occuring. +// Interrupt posting is higher priority than int clear by host +//----------------------------------------------------------------------- +wire [31:0] cfg_gpio_int_status = reg_9[31:0]; // to be used for read + +//-------------------------------------------------------- +// Interrupt Status Generation +// Note: Reg_9 --> Interrupt Status Register, Writting '1' will clear the +// corresponding interrupt status bit. Writting '0' has no +// effect +// Reg_10 --> Writting one to this register will set the interrupt in +// interrupt status register (reg_9), Writting '0' does not has any +// effect. +/// Always update int_status, even if no register write is occuring. +// Interrupt posting is higher priority than int clear by host +//-------------------------------------------------------- +wire [31:0] gpio_int_status = reg_9; +always @(posedge mclk or negedge h_reset_n) +begin + if(~h_reset_n) + begin + reg_9[31:0] <= 32'h0; + end + else + begin + if(sw_wr_en_9 && wr_be[0]) + begin + reg_9[7:0] <= ((~sw_reg_wdata[7:0] & gpio_int_status[7:0]) | gpio_int_event[7:0]); + end + else if(sw_wr_en_10 && wr_be[0]) + begin + reg_9[7:0] <= ((sw_reg_wdata[7:0] | gpio_int_status[7:0]) | gpio_int_event[7:0]); + end + else + begin + reg_9[7:0] <= (gpio_int_status[7:0] | gpio_int_event[7:0]); + end + + if(sw_wr_en_9 && wr_be[1]) + begin + reg_9[15:8] <= ((~sw_reg_wdata[15:8] & gpio_int_status[15:8]) | gpio_int_event[15:8]); + end + else if(sw_wr_en_10 && wr_be[1]) + begin + reg_9[15:8] <= ((sw_reg_wdata[15:8] | gpio_int_status[15:8]) | gpio_int_event[15:8]); + end + else + begin + reg_9[15:8] <= (gpio_int_status[15:8] | gpio_int_event[15:8]); + end + + if(sw_wr_en_9 && wr_be[2]) + begin + reg_9[23:16] <= ((~sw_reg_wdata[23:16] & gpio_int_status[23:16]) | gpio_int_event[23:16]); + end + else if(sw_wr_en_10 && wr_be[2]) + begin + reg_9[23:16] <= ((sw_reg_wdata[23:16] | gpio_int_status[23:16]) | gpio_int_event[23:16]); + end + else + begin + reg_9[23:16] <= (gpio_int_status[23:16] | gpio_int_event[23:16]); + end + + if(sw_wr_en_9 && wr_be[3]) + begin + reg_9[31:24] <= ((~sw_reg_wdata[31:24] & gpio_int_status[31:24]) | gpio_int_event[31:24]); + end + else if(sw_wr_en_10 && wr_be[3]) + begin + reg_9[31:24] <= ((sw_reg_wdata[31:24] | gpio_int_status[31:24]) | gpio_int_event[31:24]); + end + else + begin + reg_9[31:24] <= (gpio_int_status[31:24] | gpio_int_event[31:24]); + end + end +end +//------------------------------------------------- +// Returns same value as interrupt status register +//------------------------------------------------ + +assign reg_10 = reg_9; +//----------------------------------------------------------------------- +// Logic for cfg_gpio_int_mask : GPIO interrupt mask +//----------------------------------------------------------------------- +wire [31:0] cfg_gpio_int_mask = reg_11[31:0]; // to be used for read + +assign gpio_intr = ( | (reg_9 & reg_11) ); // interrupt pin to the RISC + + +// Register-11 +gen_32b_reg #(32'h0) u_reg_11 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_11 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_11 ) + ); +//----------------------------------------------------------------------- +// Logic for cfg_gpio_posedge_int_sel : Enable posedge GPIO interrupt +//----------------------------------------------------------------------- +assign cfg_gpio_posedge_int_sel = reg_12[31:0]; // to be used for read +gen_32b_reg #(32'h0) u_reg_12 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_12 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_12 ) + ); +//----------------------------------------------------------------------- +// Logic for cfg_gpio_negedge_int_sel : Enable negedge GPIO interrupt +//----------------------------------------------------------------------- +assign cfg_gpio_negedge_int_sel = reg_13[31:0]; // to be used for read +gen_32b_reg #(32'h0) u_reg_13 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_13 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_13 ) + ); + +//----------------------------------------------------------------------- +// Logic for cfg_multi_func_sel :Enable GPIO to act as multi function pins +//----------------------------------------------------------------------- +assign cfg_multi_func_sel = reg_14[31:0]; // to be used for read + + +gen_32b_reg #(32'h0) u_reg_14 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_14 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_14 ) + ); + +// Reg-15 +gen_32b_reg #(32'h0) u_reg_15 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_15 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_15 ) + ); +//----------------------------------------------------------------------- +// Logic for PWM-0 Config +//----------------------------------------------------------------------- +assign cfg_pwm0_low = reg_16[15:0]; // low period of w/f +assign cfg_pwm0_high = reg_16[31:16]; // high period of w/f + +gen_32b_reg #(32'h0) u_reg_16 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_16 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_16 ) + ); + + +//----------------------------------------------------------------------- +// Logic for PWM-1 Config +//----------------------------------------------------------------------- +assign cfg_pwm1_low = reg_17[15:0]; // low period of w/f +assign cfg_pwm1_high = reg_17[31:16]; // high period of w/f +gen_32b_reg #(32'h0) u_reg_17 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_17 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_17 ) + ); + +//----------------------------------------------------------------------- +// Logic for PWM-2 Config +//----------------------------------------------------------------------- +assign cfg_pwm2_low = reg_18[15:0]; // low period of w/f +assign cfg_pwm2_high = reg_18[31:16]; // high period of w/f +gen_32b_reg #(32'h0) u_reg_18 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_18 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_18 ) + ); + +//----------------------------------------------------------------------- +// Logic for PWM-3 Config +//----------------------------------------------------------------------- +assign cfg_pwm3_low = reg_19[15:0]; // low period of w/f +assign cfg_pwm3_high = reg_19[31:16]; // high period of w/f +gen_32b_reg #(32'h0) u_reg_19 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_19 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_19 ) + ); + +//----------------------------------------------------------------------- +// Logic for PWM-4 Config +//----------------------------------------------------------------------- +assign cfg_pwm4_low = reg_20[15:0]; // low period of w/f +assign cfg_pwm4_high = reg_20[31:16]; // high period of w/f + +gen_32b_reg #(32'h0) u_reg_20 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_20 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_20 ) + ); + +//----------------------------------------------------------------------- +// Logic for PWM-5 Config +//----------------------------------------------------------------------- +assign cfg_pwm5_low = reg_21[15:0]; // low period of w/f +assign cfg_pwm5_high = reg_21[31:16]; // high period of w/f + +gen_32b_reg #(32'h0) u_reg_21 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_21 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_21 ) + ); + + + +//----------------------------------------------------------------------- +// Register Read Path Multiplexer instantiation +//----------------------------------------------------------------------- + +always_comb +begin + reg_out [31:0] = 32'h0; + + case (sw_addr [4:0]) + 5'b00000 : reg_out [31:0] = reg_0 [31:0]; + 5'b00001 : reg_out [31:0] = reg_1 [31:0]; + 5'b00010 : reg_out [31:0] = reg_2 [31:0]; + 5'b00011 : reg_out [31:0] = reg_3 [31:0]; + 5'b00100 : reg_out [31:0] = reg_4 [31:0]; + 5'b00101 : reg_out [31:0] = reg_5 [31:0]; + 5'b00110 : reg_out [31:0] = reg_6 [31:0]; + 5'b00111 : reg_out [31:0] = reg_7 [31:0]; + 5'b01000 : reg_out [31:0] = reg_8 [31:0]; + 5'b01001 : reg_out [31:0] = reg_9 [31:0]; + 5'b01010 : reg_out [31:0] = reg_10 [31:0]; + 5'b01011 : reg_out [31:0] = reg_11 [31:0]; + 5'b01100 : reg_out [31:0] = reg_12 [31:0]; + 5'b01101 : reg_out [31:0] = reg_13 [31:0]; + 5'b01110 : reg_out [31:0] = reg_14 [31:0]; + 5'b01111 : reg_out [31:0] = reg_15 [31:0]; + 5'b10000 : reg_out [31:0] = reg_16 [31:0]; + 5'b10010 : reg_out [31:0] = reg_17 [31:0]; + 5'b10011 : reg_out [31:0] = reg_18 [31:0]; + 5'b10100 : reg_out [31:0] = reg_19 [31:0]; + 5'b10101 : reg_out [31:0] = reg_20 [31:0]; + 5'b10110 : reg_out [31:0] = reg_21 [31:0]; + default : reg_out [31:0] = 32'h0; + endcase +end + + +endmodule
diff --git a/verilog/rtl/pinmux/src/pwm.sv b/verilog/rtl/pinmux/src/pwm.sv new file mode 100644 index 0000000..7a30772 --- /dev/null +++ b/verilog/rtl/pinmux/src/pwm.sv
@@ -0,0 +1,44 @@ + +//------------------------------------------------------------------- +// PWM waveform period: 1000/((cfg_pwm_high+1) + (cfg_pwm_low+1)) +// For 1 Second with Duty cycle 50 = 1000/((499+1) + (499+1)) +// For 1 Second with 1ms On and 999ms Off = 1000/((0+1) + (998+1)) +// Timing Run's with 1 Milisecond pulse +//------------------------------------------------------------------- + +module pwm( + output logic waveform, + + input logic h_reset_n, + input logic mclk, + input logic pulse1m_mclk, + input logic cfg_pwm_enb, + input logic [15:0] cfg_pwm_high, + input logic [15:0] cfg_pwm_low +); + +logic [15:0] pwm_cnt ; // PWM on/off counter + + +always @(posedge mclk or negedge h_reset_n) +begin + if ( ~h_reset_n ) + begin + pwm_cnt <= 16'h0; + waveform <= 1'b0; + end + else if ( pulse1m_mclk && cfg_pwm_enb) + begin + if ( pwm_cnt == 16'h0 && waveform == 1'b0) begin + pwm_cnt <= cfg_pwm_high; + waveform <= ~waveform; + end else if ( pwm_cnt == 16'h0 && waveform == 1'b1) begin + pwm_cnt <= cfg_pwm_low; + waveform <= ~waveform; + end else begin + pwm_cnt <= pwm_cnt - 1; + end + end +end + +endmodule
diff --git a/verilog/rtl/sar_adc/ACMP.sv b/verilog/rtl/sar_adc/ACMP.sv new file mode 100644 index 0000000..7f58f42 --- /dev/null +++ b/verilog/rtl/sar_adc/ACMP.sv
@@ -0,0 +1,103 @@ +module ACMP( +`ifdef USE_POWER_PINS + input wire vccd2, + input wire vssd2, +`endif + input wire clk, + input wire INP, + input wire INN, + input wire VDD, + input wire VSS, + output wire Q +); + +`ifdef ACMP_FUNCTIONAL + + assign Q = INP > INN ; +`else + + wire clkb; + wire net1, + net2, + net3, + net4, + net5, + net6, + net7; + + sky130_fd_sc_hd__inv_1 x15 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(clk), .Y(clkb)); + sky130_fd_sc_hd__a221oi_1 x7 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A1(INP), .A2(INP), .B1(clkb), .B2(VDD), .C1(net2), .Y(net1)); + sky130_fd_sc_hd__a221oi_1 x8 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A1(INN), .A2(INN), .B1(clkb), .B2(VDD), .C1(net1), .Y(net2)); + sky130_fd_sc_hd__inv_1 x2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(net3), .Y(net6)); + sky130_fd_sc_hd__inv_1 x3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(net4), .Y(net5)); + sky130_fd_sc_hd__o221ai_1 x6 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A1(INP), .A2(INP), .B1(clk), .B2(VSS), .C1(net4), .Y(net3)); + sky130_fd_sc_hd__o221ai_1 x9 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A1(INN), .A2(INN), .B1(clk), .B2(VSS), .C1(net3), .Y(net4)); + sky130_fd_sc_hd__nor3_1 x10 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(net5), .B(net1), .C(net7), .Y(Q)); + sky130_fd_sc_hd__nor3_1 x11 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(Q), .B(net6), .C(net2), .Y(net7)); + +`endif + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/sar_adc/ACMP_HVL.v b/verilog/rtl/sar_adc/ACMP_HVL.v new file mode 100644 index 0000000..543cd6e --- /dev/null +++ b/verilog/rtl/sar_adc/ACMP_HVL.v
@@ -0,0 +1,112 @@ +/* + An analog comparator using HVL cells +*/ + +module ACMP_HVL( +`ifdef USE_POWER_PINS + input wire vccd2, + input wire vssd2, +`endif + input wire clk, + input wire INP, + input wire INN, + output wire Q +); + wire clkb; + wire Q1b, Q1; + wire Q2b, Q2; + wire Qb; + + sky130_fd_sc_hvl__inv_1 x0 ( + .Y(clkb), + .A(clk) + ); + + sky130_fd_sc_hvl__nor3_1 x5( + .Y(Q), + .A(Q1b), + .B(Q2b), + .C(Qb) + ); + + sky130_fd_sc_hvl__nor3_1 x6( + .Y(Qb), + .A(Q1), + .B(Q2), + .C(Q) + ); + + latch_nand3 x1 ( + .CLK(clk), + .VP(INP), + .VN(INN), + .Q(Q1), + .Qb(Q1b) + ); + + latch_nor3 x2 ( + .CLK(clkb), + .VP(INP), + .VN(INN), + .Q(Q2), + .Qb(Q2b) + ); + +endmodule + +module latch_nor3 ( + input wire CLK, + input wire VP, + input wire VN, + output wire Q, + output wire Qb +); + + sky130_fd_sc_hvl__nor3_1 x1( + .Y(Qb), + .A(CLK), + .B(VP), + .C(Q) + ); + sky130_fd_sc_hvl__nor3_1 x2( + .Y(Q), + .A(CLK), + .B(VN), + .C(Qb) + ); + +endmodule + +module latch_nand3 ( + input wire CLK, + input wire VP, + input wire VN, + output wire Q, + output wire Qb +); + wire Q0, Q0b; + + sky130_fd_sc_hvl__nand3_1 x1( + .Y(Q0b), + .A(CLK), + .B(VP), + .C(Q0) + ); + sky130_fd_sc_hvl__nand3_1 x2( + .Y(Q0), + .A(CLK), + .B(VN), + .C(Q0b) + ); + + sky130_fd_sc_hvl__inv_4 x3 ( + .Y(Qb), + .A(Q0) + ); + + sky130_fd_sc_hvl__inv_4 x4 ( + .Y(Q), + .A(Q0b) + ); + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/sar_adc/DAC_8BIT.v b/verilog/rtl/sar_adc/DAC_8BIT.v new file mode 100644 index 0000000..8030e18 --- /dev/null +++ b/verilog/rtl/sar_adc/DAC_8BIT.v
@@ -0,0 +1,24 @@ +module DAC_8BIT ( +`ifdef USE_POWER_PINS + input wire vdd, // User area 1 1.8V supply + input wire gnd, // User area 1 digital ground +`endif + input wire d0, + input wire d1, + input wire d2, + input wire d3, + input wire d4, + input wire d5, + input wire d6, + input wire d7, + + input wire inp1, + input wire inp2, + + output wire out_v +); + +// Dummy behavirol model to verify the DAC connection with the user_project_wrapper +assign out_v = d0 | d1 | d2 | d3 | d4 | d5 | d6 | d7 ; + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/sar_adc/SAR.sv b/verilog/rtl/sar_adc/SAR.sv new file mode 100644 index 0000000..9931483 --- /dev/null +++ b/verilog/rtl/sar_adc/SAR.sv
@@ -0,0 +1,65 @@ +// file: SAR.v +// A parametrized Successive Approximation Register (SAR) +// The module is so compact; it is only 110 cells for +// 8-bit SAR using SKY130 HD library +// +// author: Mohamed Shalan (mshalan@aucegypt.edu) + +`timescale 1ns/1ns + +module SAR #(parameter SIZE = 8) ( + input wire clk, // The clock + input wire reset_n, // Active low reset + input wire start, // Conversion start + input wire cmp, // Analog comparator output + output wire [SIZE-1:0] out, // The output sample + output wire [SIZE-1:0] outn, // Inverted output for active low DAC + output wire done, // Conversion is done + output wire clkn // Inverted clock to be used by the clocked analog comparator +); + + reg [SIZE-1:0] result; + reg [SIZE-1:0] shift; + + // FSM to handle the SAR operation + reg [1:0] state, nstate; + localparam IDLE=0, CONV=1, DONE=2; + + always @* + case (state) + IDLE: if(start) nstate = CONV; + else nstate = IDLE; + CONV: if(shift == 1'b1) nstate = DONE; + else nstate = CONV; + DONE: nstate = IDLE; + default: nstate = IDLE; + endcase + + always @(posedge clk or negedge reset_n) + if(!reset_n) + state <= IDLE; + else + state <= nstate; + + // Shift Register + always @(posedge clk) + if(state == IDLE) + shift <= 1'b1 << (SIZE-1); + else if(state == CONV) + shift<= shift >> 1; + + // The SAR + wire [SIZE-1:0] current = (cmp == 1'b0) ? ~shift : {SIZE{1'b1}} ; + wire [SIZE-1:0] next = shift >> 1; + always @(posedge clk) + if(state == IDLE) + result <= 1'b1 << (SIZE-1); + else if(state == CONV) + result <= (result | next) & current; + + assign out = result; + assign outn = ~result; + assign clkn = ~clk; + assign done = (state==DONE); + +endmodule
diff --git a/verilog/rtl/sar_adc/adc_reg.sv b/verilog/rtl/sar_adc/adc_reg.sv new file mode 100644 index 0000000..24dcf0f --- /dev/null +++ b/verilog/rtl/sar_adc/adc_reg.sv
@@ -0,0 +1,262 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// ADC register //// +//// //// +//// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// This block generate all the ADC config and status //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 26 Sept 2021 Dinesh A //// +//// Initial version //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module adc_reg ( + + input logic mclk, + input logic reset_n, + + // Reg Bus Interface Signal + input logic reg_cs, + input logic reg_wr, + input logic [7:0] reg_addr, + input logic [31:0] reg_wdata, + input logic [3:0] reg_be, + + // Outputs + output logic [31:0] reg_rdata, + output logic reg_ack, + + input logic pulse1m_mclk, + // ADC I/F + output logic start_conv, + output logic [2:0] adc_ch_no, + input logic conv_done, + input logic [7:0] adc_result + + + ); + + + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +logic sw_rd_en; +logic sw_wr_en; +logic [3:0] sw_addr ; // addressing 16 registers +logic [3:0] wr_be ; +logic [31:0] sw_reg_wdata; + +logic reg_cs_l ; +logic reg_cs_2l ; + + +logic [31:0] reg_0; // ADC Config +logic [31:0] reg_1; // ADC Ch-1 Result +logic [31:0] reg_2; // ADC Ch-2 Result +logic [31:0] reg_3; // ADC Ch-3 Result +logic [31:0] reg_4; // ADC Ch-4 Result +logic [31:0] reg_5; // ADC Ch-5 Result +logic [31:0] reg_6; // ADC Ch-6 Result +logic [31:0] reg_7; // Software-Reg_7 +logic [31:0] reg_out; + +//----------------------------------------------------------------------- +// Main code starts here +//----------------------------------------------------------------------- + +//----------------------------------------------------------------------- +// To avoid interface timing, all the content are registered +//----------------------------------------------------------------------- +always @ (posedge mclk or negedge reset_n) +begin + if (reset_n == 1'b0) + begin + sw_addr <= '0; + sw_rd_en <= '0; + sw_wr_en <= '0; + sw_reg_wdata <= '0; + wr_be <= '0; + reg_cs_l <= '0; + reg_cs_2l <= '0; + end else begin + sw_addr <= reg_addr [5:2]; + sw_rd_en <= reg_cs & !reg_wr; + sw_wr_en <= reg_cs & reg_wr; + sw_reg_wdata <= reg_wdata; + wr_be <= reg_be; + reg_cs_l <= reg_cs; + reg_cs_2l <= reg_cs_l; + end +end + + +//----------------------------------------------------------------------- +// Read path mux +//----------------------------------------------------------------------- + +always @ (posedge mclk or negedge reset_n) +begin : preg_out_Seq + if (reset_n == 1'b0) begin + reg_rdata [31:0] <= 32'h0000_0000; + reg_ack <= 1'b0; + end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin + reg_rdata [31:0] <= reg_out [31:0]; + reg_ack <= 1'b1; + end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin + reg_ack <= 1'b1; + end else begin + reg_ack <= 1'b0; + end +end + + +//----------------------------------------------------------------------- +// register read enable and write enable decoding logic +//----------------------------------------------------------------------- +wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0); +wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0); +wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1); +wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1); +wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2); +wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2); +wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3); +wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3); +wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4); +wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4); +wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5); +wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5); +wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6); +wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6); +wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7); +wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7); + +always @( *) +begin : preg_sel_Com + + reg_out [31:0] = 32'd0; + + case (sw_addr [3:0]) + 4'b0000 : reg_out [31:0] = reg_0 [31:0]; + 4'b0001 : reg_out [31:0] = {24'h0,reg_1 [7:0]}; + 4'b0010 : reg_out [31:0] = {24'h0,reg_2 [7:0]}; + 4'b0011 : reg_out [31:0] = {24'h0,reg_3 [7:0]}; + 4'b0100 : reg_out [31:0] = {24'h0,reg_4 [7:0]}; + 4'b0101 : reg_out [31:0] = {24'h0,reg_5 [7:0]}; + 4'b0110 : reg_out [31:0] = {24'h0,reg_6 [7:0]}; + default : reg_out [31:0] = 'h0; + endcase +end + + + +//----------------------------------------------------------------------- +// Individual register assignments +//----------------------------------------------------------------------- +logic [5:0] cfg_adc_enb = reg_0[5:0]; + +gen_32b_reg #(32'h0) u_reg_0 ( + //List of Inputs + .reset_n (reset_n ), + .clk (mclk ), + .cs (sw_wr_en_0 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_0 ) + ); + + +always @(posedge mclk or negedge reset_n) +begin + if(~reset_n) begin + reg_1[7:0] <= 8'h0; + reg_2[7:0] <= 8'h0; + reg_3[7:0] <= 8'h0; + reg_4[7:0] <= 8'h0; + reg_5[7:0] <= 8'h0; + reg_6[7:0] <= 8'h0; + start_conv <= '0; + adc_ch_no <= '0; + end else begin + if(cfg_adc_enb[0] && pulse1m_mclk) begin + if(start_conv && conv_done) begin + start_conv <= 0; + case(adc_ch_no) + 3'b000: reg_1[7:0] <= adc_result; + 3'b001: reg_2[7:0] <= adc_result; + 3'b010: reg_3[7:0] <= adc_result; + 3'b011: reg_4[7:0] <= adc_result; + 3'b100: reg_5[7:0] <= adc_result; + 3'b101: reg_6[7:0] <= adc_result; + endcase + end + end else begin + start_conv <= 1; + if(adc_ch_no == 5) begin + adc_ch_no <= 0; + end else begin + adc_ch_no <= adc_ch_no+1; + end + end + end +end + + + + +endmodule
diff --git a/verilog/rtl/sar_adc/sar_adc.sv b/verilog/rtl/sar_adc/sar_adc.sv new file mode 100644 index 0000000..6514e98 --- /dev/null +++ b/verilog/rtl/sar_adc/sar_adc.sv
@@ -0,0 +1,170 @@ +module sar_adc( +`ifdef USE_POWER_PINS + input logic vccd1 ,// User area 1 1.8V supply + input logic vssd1 ,// User area 1 digital ground + input logic vccd2 ,// User area 2 1.8V supply (analog) + input logic vssd2 ,// User area 2 ground (analog) +`endif + + + input logic clk ,// The clock (digital) + input logic reset_n ,// Active low reset (digital) + + // Reg Bus Interface Signal + input logic reg_cs , + input logic reg_wr , + input logic [7:0] reg_addr , + input logic [31:0] reg_wdata , + input logic [3:0] reg_be , + + // Outputs + output logic [31:0] reg_rdata , + output logic reg_ack , + + input logic pulse1m_mclk , + output logic [7:0] sar2dac ,// SAR O/P towards DAC + + input logic analog_dac_out, // DAC analog o/p for compare + + // ACMP (HD) Ports + input logic analog_din // (Analog) + +); + + logic clkn; + logic [5:0] sar_cmp; // SAR compare signal + logic sar_cmp_int; + logic [2:0] adc_ch_no; + logic start_conv ;// Conversion start (digital) + logic conv_done ;// Conversion is done (digital) + logic [7:0] adc_result ;// SAR o/p (digital) + +always_comb +begin + sar_cmp_int = 0; + case(adc_ch_no) + 3'b000 : sar_cmp_int = sar_cmp[0]; + 3'b001 : sar_cmp_int = sar_cmp[1]; + 3'b010 : sar_cmp_int = sar_cmp[2]; + 3'b011 : sar_cmp_int = sar_cmp[3]; + 3'b100 : sar_cmp_int = sar_cmp[4]; + 3'b101 : sar_cmp_int = sar_cmp[5]; + endcase + + +end + +adc_reg u_adc_reg ( + .mclk (mclk), + .reset_n (reset_n), + + // Reg Bus Interface Signal + .reg_cs (reg_cs), + .reg_wr (reg_wr), + .reg_addr (reg_addr), + .reg_wdata (reg_wdata), + .reg_be (reg_be), + + // Outputs + .reg_rdata (reg_rdata), + .reg_ack (reg_ack), + + .pulse1m_mclk (pulse1m_mclk), + // ADC I/F + .start_conv (start_conv), + .adc_ch_no (adc_ch_no), + .conv_done (conv_done), + .adc_result (adc_result) + + ); + + + ACMP COMP_0 ( + `ifdef USE_POWER_PINS + .vccd2 (vccd2 ), + .vssd2 (vssd2 ), + .VDD (vccd2 ), + .VSS (vssd2 ), + `endif + .clk (clk ), + .INP (analog_din[0] ), + .INN (analog_dac_out ), + .Q (sar_cmp[0] ) + ); + + ACMP COMP_1 ( + `ifdef USE_POWER_PINS + .vccd2 (vccd2 ), + .vssd2 (vssd2 ), + .VDD (vccd2 ), + .VSS (vssd2 ), + `endif + .clk (clk ), + .INP (analog_din[1] ), + .INN (analog_dac_out ), + .Q (sar_cmp[1] ) + ); + + ACMP COMP_2 ( + `ifdef USE_POWER_PINS + .vccd2 (vccd2 ), + .vssd2 (vssd2 ), + .VDD (vccd2 ), + .VSS (vssd2 ), + `endif + .clk (clk ), + .INP (analog_din[2] ), + .INN (analog_dac_out ), + .Q (sar_cmp[2] ) + ); + + ACMP COMP_3 ( + `ifdef USE_POWER_PINS + .vccd2 (vccd2 ), + .vssd2 (vssd2 ), + .VDD (vccd2 ), + .VSS (vssd2 ), + `endif + .clk (clk ), + .INP (analog_din[3] ), + .INN (analog_dac_out ), + .Q (sar_cmp[3] ) + ); + ACMP COMP_4 ( + `ifdef USE_POWER_PINS + .vccd2 (vccd2 ), + .vssd2 (vssd2 ), + .VDD (vccd2 ), + .VSS (vssd2 ), + `endif + .clk (clk ), + .INP (analog_din[4] ), + .INN (analog_dac_out ), + .Q (sar_cmp[4] ) + ); + ACMP COMP_5 ( + `ifdef USE_POWER_PINS + .vccd2 (vccd2 ), + .vssd2 (vssd2 ), + .VDD (vccd2 ), + .VSS (vssd2 ), + `endif + .clk (clk ), + .INP (analog_din[5] ), + .INN (analog_dac_out ), + .Q (sar_cmp[5] ) + ); + + SAR CTRL ( + .clk (clk ), + .reset_n (reset_n ), + .start (start_conv ), + .cmp (sar_cmp_int ), + .out (adc_result ), + .done (conv_done ), + .outn (sar2dac ), + .clkn (clkn ) + ); + + +endmodule
diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv index 042319c..02aacc7 100644 --- a/verilog/rtl/spi_master/src/spim_top.sv +++ b/verilog/rtl/spi_master/src/spim_top.sv
@@ -117,10 +117,11 @@ output logic [31:0] spi_debug, // PAD I/f - input logic [3:0] io_in , - output logic [5:0] io_out , - output logic [5:0] io_oeb - + input logic [3:0] spi_sdi, + output logic spi_clk, + output logic spi_csn0,// No hold fix for CS#, as it asserted much eariler than SPI clock + output logic [3:0] spi_sdo, + output logic spi_oen ); @@ -218,16 +219,9 @@ logic spi_sdo1; logic spi_sdo2; logic spi_sdo3; -logic spi_sdi0; -logic spi_sdi1; -logic spi_sdi2; -logic spi_sdi3; logic spi_en_tx; logic spi_init_done; -logic spi_sdo0_out; -logic spi_sdo1_out; -logic spi_sdo2_out; -logic spi_sdo3_out; +logic [3:0] spi_sdo_int; logic spi_sdo0_dl; logic spi_sdo1_dl; @@ -235,42 +229,26 @@ logic spi_sdo3_dl; -assign spi_sdi0 = io_in[0]; -assign spi_sdi1 = io_in[1]; -assign spi_sdi2 = io_in[2]; -assign spi_sdi3 = io_in[3]; - -assign io_out[0] = spi_clk; -assign io_out[1] = spi_csn0;// No hold fix for CS#, as it asserted much eariler than SPI clock -assign #1 io_out[2] = spi_sdo0_out; -assign #1 io_out[3] = spi_sdo1_out; -assign #1 io_out[4] = spi_sdo2_out; -assign #1 io_out[5] = spi_sdo3_out; // ADDing Delay cells for Interface hold fix -sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio0 (.X(spi_sdo0_d1),.A(spi_sdo0)); +sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio0 (.X(spi_sdo0_d1),.A(spi_sdo_int[0])); sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio0 (.X(spi_sdo0_d2),.A(spi_sdo0_d1)); -sky130_fd_sc_hd__clkbuf_16 u_buf_sdio0 (.X(spi_sdo0_out),.A(spi_sdo0_d2)); +sky130_fd_sc_hd__clkbuf_16 u_buf_sdio0 (.X(spi_sdo0),.A(spi_sdo0_d2)); -sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio1 (.X(spi_sdo1_d1),.A(spi_sdo1)); +sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio1 (.X(spi_sdo1_d1),.A(spi_sdo_int[1])); sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio1 (.X(spi_sdo1_d2),.A(spi_sdo1_d1)); -sky130_fd_sc_hd__clkbuf_16 u_buf_sdio1 (.X(spi_sdo1_out),.A(spi_sdo1_d2)); +sky130_fd_sc_hd__clkbuf_16 u_buf_sdio1 (.X(spi_sdo1),.A(spi_sdo1_d2)); -sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio2 (.X(spi_sdo2_d1),.A(spi_sdo2)); +sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio2 (.X(spi_sdo2_d1),.A(spi_sdo_int[2])); sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio2 (.X(spi_sdo2_d2),.A(spi_sdo2_d1)); -sky130_fd_sc_hd__clkbuf_16 u_buf_sdio2 (.X(spi_sdo2_out),.A(spi_sdo2_d2)); +sky130_fd_sc_hd__clkbuf_16 u_buf_sdio2 (.X(spi_sdo2),.A(spi_sdo2_d2)); -sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio3 (.X(spi_sdo3_d1),.A(spi_sdo3)); +sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio3 (.X(spi_sdo3_d1),.A(spi_sdo_int[3])); sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio3 (.X(spi_sdo3_d2),.A(spi_sdo3_d1)); -sky130_fd_sc_hd__clkbuf_16 u_buf_sdio3 (.X(spi_sdo3_out),.A(spi_sdo3_d2)); +sky130_fd_sc_hd__clkbuf_16 u_buf_sdio3 (.X(spi_sdo3),.A(spi_sdo3_d2)); -assign io_oeb[0] = 1'b0; // spi_clk -assign io_oeb[1] = 1'b0; // spi_csn -assign #1 io_oeb[2] = !spi_en_tx; // spi_dio0 -assign #1 io_oeb[3] = !spi_en_tx; // spi_dio1 -assign #1 io_oeb[4] = (spi_mode == 0) ? 1 'b0 : !spi_en_tx; // spi_dio2 -assign #1 io_oeb[5] = (spi_mode == 0) ? 1 'b0 : !spi_en_tx; // spi_dio3 +assign spi_oen = !spi_en_tx; spim_if #( .WB_WIDTH(WB_WIDTH)) u_wb_if( .mclk (mclk ), @@ -485,15 +463,15 @@ .spi_csn2 (spi_csn2 ), .spi_csn3 (spi_csn3 ), .spi_mode (spi_mode ), - .spi_sdo0 (spi_sdo0 ), - .spi_sdo1 (spi_sdo1 ), - .spi_sdo2 (spi_sdo2 ), - .spi_sdo3 (spi_sdo3 ), - .spi_sdi0 (spi_sdi0 ), - .spi_sdi1 (spi_sdi1 ), - .spi_sdi2 (spi_sdi2 ), - .spi_sdi3 (spi_sdi3 ), - .spi_en_tx_out (spi_en_tx ) + .spi_sdo0 (spi_sdo_int[0] ), + .spi_sdo1 (spi_sdo_int[1] ), + .spi_sdo2 (spi_sdo_int[2] ), + .spi_sdo3 (spi_sdo_int[3] ), + .spi_sdi0 (spi_sdi[0] ), + .spi_sdi1 (spi_sdi[1] ), + .spi_sdi2 (spi_sdi[2] ), + .spi_sdi3 (spi_sdi[3] ), + .spi_en_tx_out (spi_en_tx ) ); endmodule
diff --git a/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv b/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv index ad97a12..69b31d4 100644 --- a/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv +++ b/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv
@@ -87,62 +87,37 @@ input logic reg_be, // Outputs - output logic [31:0] reg_rdata, + output logic [31:0] reg_rdata, output logic reg_ack, + ///////////////////////////////////////////////////////// + // i2c interface + /////////////////////////////////////////////////////// + input logic scl_pad_i , // SCL-line input + output logic scl_pad_o , // SCL-line output (always 1'b0) + output logic scl_pad_oen_o , // SCL-line output enable (active low) + + input logic sda_pad_i , // SDA-line input + output logic sda_pad_o , // SDA-line output (always 1'b0) + output logic sda_padoen_o , // SDA-line output enable (active low) - // Pad Control - input logic [1:0] io_in, - output logic [1:0] io_out, - output logic [1:0] io_oeb + // UART I/F + input logic uart_rxd , + output logic uart_txd , + + input logic usb_in_dp , + input logic usb_in_dn , + + output logic usb_out_dp , + output logic usb_out_dn , + output logic usb_out_tx_oen ); -///////////////////////////////////////////////////////// -// uart interface -/////////////////////////////////////////////////////// - -logic uart_rxd ; -logic uart_txd ; -///////////////////////////////////////////////////////// -// i2c interface -/////////////////////////////////////////////////////// -logic scl_pad_i ; // SCL-line input -logic scl_pad_o ; // SCL-line output (always 1'b0) -logic scl_pad_oen_o ; // SCL-line output enable (active low) - -logic sda_pad_i ; // SDA-line input -logic sda_pad_o ; // SDA-line output (always 1'b0) -logic sda_padoen_o ; // SDA-line output enable (active low) - -///////////////////////////////////////////////////////// -// usb interface -/////////////////////////////////////////////////////// -logic usb_in_dp ; -logic usb_in_dn ; - -logic usb_out_dp ; -logic usb_out_dn ; -logic usb_out_tx_oen ; `define SEL_UART 2'b00 `define SEL_I2C 2'b01 `define SEL_USB 2'b10 -assign io_oeb[0] = (uart_i2c_usb_sel == `SEL_UART) ? 1'b1 : - (uart_i2c_usb_sel == `SEL_I2C) ? scl_pad_oen_o : usb_out_tx_oen ; -assign uart_rxd = (uart_i2c_usb_sel == `SEL_UART) ? io_in[0]: 1'b0; -assign scl_pad_i = (uart_i2c_usb_sel == `SEL_I2C) ? io_in[0]: 1'b0; -assign usb_in_dn = (uart_i2c_usb_sel == `SEL_USB) ? io_in[0]: 1'b0; -assign io_out[0] = (uart_i2c_usb_sel == `SEL_UART) ? 1'b0 : - (uart_i2c_usb_sel == `SEL_I2C) ? scl_pad_o : usb_out_dn; - - -assign io_oeb[1] = (uart_i2c_usb_sel == `SEL_UART) ? 1'b0 : - (uart_i2c_usb_sel == `SEL_I2C) ? sda_padoen_o : usb_out_tx_oen ; -assign io_out[1] = (uart_i2c_usb_sel == `SEL_UART) ? uart_txd: - (uart_i2c_usb_sel == `SEL_I2C) ? sda_pad_o : usb_out_dp; -assign sda_pad_i = (uart_i2c_usb_sel == `SEL_I2C) ? io_in[1] : 1'b0; -assign usb_in_dp = (uart_i2c_usb_sel == `SEL_USB) ? io_in[1] : 1'b0; //----------------------------------------
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index d32b2ef..d5afe73 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -19,9 +19,8 @@ //// //// //// Digital core //// //// //// -//// This file is part of the YIFive cores project //// -//// https://github.com/dineshannayya/yifive_r0.git //// -//// http://www.opencores.org/cores/yifive/ //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// //// //// //// Description //// //// This is digital core and integrate all the main block //// @@ -99,6 +98,12 @@ //// usb1.1 host integrated part of uart_i2cm_usb module,//// //// due to number of IO pin limitation, //// //// Only UART/I2C/USB selected based on config mode //// +//// 1.2 - 29th Sept 2021, Dinesh.A //// +//// 1. copied the repo from yifive and renames as //// +//// riscdunino //// +//// 2. Removed the SDRAM controlled //// +//// 3. Added PinMux //// +//// 4. Added SAR ADC for 6 channel //// //// //// ////////////////////////////////////////////////////////////////////// //// //// @@ -233,15 +238,15 @@ //--------------------------------------------------------------------- // SPI Master Wishbone Interface //--------------------------------------------------------------------- -wire wbd_sdram_stb_o ; -wire [WB_WIDTH-1:0] wbd_sdram_adr_o ; -wire wbd_sdram_we_o ; // 1 - Write, 0 - Read -wire [WB_WIDTH-1:0] wbd_sdram_dat_o ; -wire [WB_WIDTH/8-1:0] wbd_sdram_sel_o ; // Byte enable -wire wbd_sdram_cyc_o ; -wire [2:0] wbd_sdram_cti_o ; -wire [WB_WIDTH-1:0] wbd_sdram_dat_i ; -wire wbd_sdram_ack_i ; +wire wbd_adc_stb_o ; +wire [7:0] wbd_adc_adr_o ; +wire wbd_adc_we_o ; // 1 - Write, 0 - Read +wire [WB_WIDTH-1:0] wbd_adc_dat_o ; +wire [WB_WIDTH/8-1:0] wbd_adc_sel_o ; // Byte enable +wire wbd_adc_cyc_o ; +wire [2:0] wbd_adc_cti_o ; +wire [WB_WIDTH-1:0] wbd_adc_dat_i ; +wire wbd_adc_ack_i ; //--------------------------------------------------------------------- // Global Register Wishbone Interface @@ -260,7 +265,7 @@ // Global Register Wishbone Interface //--------------------------------------------------------------------- wire wbd_uart_stb_o; // strobe/request -wire [7:0] wbd_uart_adr_o; // address +wire [31:0] wbd_uart_adr_o; // address wire wbd_uart_we_o; // write wire [31:0] wbd_uart_dat_o; // data output wire wbd_uart_sel_o; // byte enable @@ -306,7 +311,6 @@ wire [3:0] cfg_cska_wh ; // clock skew adjust for web host -wire wbd_clk_wi ; // clock for wishbone interconnect wire wbd_clk_riscv ; // clock for riscv wire wbd_clk_uart ; // clock for uart wire wbd_clk_spi ; // clock for spi @@ -314,38 +318,55 @@ wire wbd_clk_glbl ; // clock for global reg wire wbd_clk_wh ; // clock for global reg -wire [3:0] cfg_cska_sd_co; // clock skew adjust for sdram clock out -wire [3:0] cfg_cska_sd_ci; // clock skew adjust for sdram clock input -wire [3:0] cfg_cska_sp_co; // clock skew adjust for SPI clock out -wire io_out_29_ ; // Internally tapped SDRAM clock -wire io_in_29_ ; // Clock Skewed Pad SDRAM clock -wire io_in_30_ ; // SPI clock out - -//------------------------------------------------ -// Configuration Parameter -//------------------------------------------------ -wire [1:0] cfg_sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit -wire [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, -wire sdr_init_done ; // Indicate SDRAM Initialisation Done -wire [3:0] cfg_sdr_tras_d ; // Active to precharge delay -wire [3:0] cfg_sdr_trp_d ; // Precharge to active delay -wire [3:0] cfg_sdr_trcd_d ; // Active to R/W delay -wire cfg_sdr_en ; // Enable SDRAM controller -wire [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller -wire [12:0] cfg_sdr_mode_reg ; -wire [2:0] cfg_sdr_cas ; // SDRAM CAS Latency -wire [3:0] cfg_sdr_trcar_d ; // Auto-refresh period -wire [3:0] cfg_sdr_twr_d ; // Write recovery delay -wire [11: 0] cfg_sdr_rfsh ; -wire [2 : 0] cfg_sdr_rfmax ; wire [31:0] spi_debug ; -wire [31:0] sdram_debug ; +wire [31:0] pinmux_debug ; wire [63:0] riscv_debug ; +// SFLASH I/F +wire sflash_sck ; +wire sflash_ss ; +wire sflash_oen ; +wire [3:0] sflash_do ; +wire [3:0] sflash_di ; +// SSRAM I/F +wire ssram_sck ; +wire ssram_ss ; +wire ssram_oen ; +wire [3:0] ssram_do ; +wire [3:0] ssram_di ; +// USB I/F +wire usb_dp_o ; +wire usb_dn_o ; +wire usb_oen ; +wire usb_dp_i ; +wire usb_dn_i ; + +// UART I/F +wire uart_txd ; +wire uart_rxd ; + +// I2CM I/F +wire i2cm_clk_o ; +wire i2cm_clk_i ; +wire i2cm_clk_oen ; +wire i2cm_data_oen ; +wire i2cm_data_o ; +wire i2cm_data_i ; + +// SPI MASTER +wire spim_sck ; +wire spim_ss ; +wire spim_miso ; +wire spim_mosi ; + +wire [7:0] sar2dac ; +wire analog_dac_out ; +wire pulse1m_mclk ; +wire h_reset_n ; ///////////////////////////////////////////////////////// // Clock Skew Ctrl //////////////////////////////////////////////////////// @@ -363,7 +384,7 @@ assign cfg_cska_sp_co = cfg_clk_ctrl2[11:8];// SPI clock out control //assign la_data_out = {riscv_debug,spi_debug,sdram_debug}; -assign la_data_out[127:0] = {sdram_debug,spi_debug,riscv_debug}; +assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug}; //clk_buf u_buf1_wb_rstn (.clk_i(wbd_int_rst_n),.clk_o(wbd_int1_rst_n)); //clk_buf u_buf2_wb_rstn (.clk_i(wbd_int1_rst_n),.clk_o(wbd_int2_rst_n)); @@ -404,7 +425,7 @@ // Slave Port .wbs_clk_out (wbd_clk_int ), - .wbs_clk_i (wbd_clk_wh ), + .wbs_clk_i (wbd_clk_int ), .wbs_cyc_o (wbd_int_cyc_i ), .wbs_stb_o (wbd_int_stb_i ), .wbs_adr_o (wbd_int_adr_i ), @@ -450,7 +471,7 @@ .wb_rst_n (wbd_int_rst_n ), - .wb_clk (wbd_clk_riscv ), + .wb_clk (wbd_clk_int ), // Instruction memory interface .wbd_imem_stb_o (wbd_riscv_imem_stb_i ), .wbd_imem_adr_o (wbd_riscv_imem_adr_i ), @@ -486,7 +507,7 @@ `endif ) u_spi_master ( - .mclk (wbd_clk_spi ), + .mclk (wbd_clk_int ), .rst_n (spi_rst_n ), .wbd_stb_i (wbd_spim_stb_o ), @@ -501,67 +522,18 @@ .spi_debug (spi_debug ), // Pad Interface - .io_in (io_in[35:32] ), // io_in[31:30] unused ports - .io_out ({io_out[35:31],io_in_30_} ), - .io_oeb (io_oeb[35:30] ) + .spi_sdi (sflash_di ), + .spi_clk (sflash_sck ), + .spi_csn0 (sflash_ss ), + .spi_sdo (sflash_do ), + .spi_oen (sflash_oen ) ); -sdrc_top - `ifndef SYNTHESIS - #(.APP_AW(WB_WIDTH), - .APP_DW(WB_WIDTH), - .APP_BW(4), - .SDR_DW(8), - .SDR_BW(1)) - `endif - u_sdram_ctrl ( - .cfg_sdr_width (cfg_sdr_width ), - .cfg_colbits (cfg_colbits ), - .sdram_debug (sdram_debug ), - - // WB bus - .wb_rst_n (wbd_int_rst_n ), - .wb_clk_i (wbd_clk_sdram ), - - .wb_stb_i (wbd_sdram_stb_o ), - .wb_addr_i (wbd_sdram_adr_o ), - .wb_we_i (wbd_sdram_we_o ), - .wb_dat_i (wbd_sdram_dat_o ), - .wb_sel_i (wbd_sdram_sel_o ), - .wb_cyc_i (wbd_sdram_cyc_o ), - .wb_ack_o (wbd_sdram_ack_i ), - .wb_dat_o (wbd_sdram_dat_i ), - - - /* Interface to SDRAMs */ - .sdram_clk (sdram_clk ), - .sdram_resetn (sdram_rst_n ), - - /** Pad Interface **/ - .io_in ({io_in_29_,io_in[28:0]} ), - .io_oeb (io_oeb[29:0] ), - .io_out ({io_out_29_,io_out[28:0]} ), - - /* Parameters */ - .sdr_init_done (sdr_init_done ), - .cfg_req_depth (cfg_req_depth ), //how many req. buffer should hold - .cfg_sdr_en (cfg_sdr_en ), - .cfg_sdr_mode_reg (cfg_sdr_mode_reg ), - .cfg_sdr_tras_d (cfg_sdr_tras_d ), - .cfg_sdr_trp_d (cfg_sdr_trp_d ), - .cfg_sdr_trcd_d (cfg_sdr_trcd_d ), - .cfg_sdr_cas (cfg_sdr_cas ), - .cfg_sdr_trcar_d (cfg_sdr_trcar_d ), - .cfg_sdr_twr_d (cfg_sdr_twr_d ), - .cfg_sdr_rfsh (cfg_sdr_rfsh ), - .cfg_sdr_rfmax (cfg_sdr_rfmax ) - ); - wb_interconnect u_intercon ( - .clk_i (wbd_clk_wi ), + .clk_i (wbd_clk_int ), .rst_n (wbd_int_rst_n ), // Master 0 Interface @@ -611,229 +583,207 @@ // Slave 1 Interface // .s1_wbd_err_i (1'b0 ), - Moved inside IP - .s1_wbd_dat_i (wbd_sdram_dat_i ), - .s1_wbd_ack_i (wbd_sdram_ack_i ), - .s1_wbd_dat_o (wbd_sdram_dat_o ), - .s1_wbd_adr_o (wbd_sdram_adr_o ), - .s1_wbd_sel_o (wbd_sdram_sel_o ), - .s1_wbd_we_o (wbd_sdram_we_o ), - .s1_wbd_cyc_o (wbd_sdram_cyc_o ), - .s1_wbd_stb_o (wbd_sdram_stb_o ), + .s1_wbd_dat_i (wbd_uart_dat_i ), + .s1_wbd_ack_i (wbd_uart_ack_i ), + .s1_wbd_dat_o (wbd_uart_dat_o ), + .s1_wbd_adr_o (wbd_uart_adr_o ), + .s1_wbd_sel_o (wbd_uart_sel_o ), + .s1_wbd_we_o (wbd_uart_we_o ), + .s1_wbd_cyc_o (wbd_uart_cyc_o ), + .s1_wbd_stb_o (wbd_uart_stb_o ), // Slave 2 Interface // .s2_wbd_err_i (1'b0 ), - Moved inside IP - .s2_wbd_dat_i (wbd_glbl_dat_i ), - .s2_wbd_ack_i (wbd_glbl_ack_i ), - .s2_wbd_dat_o (wbd_glbl_dat_o ), - .s2_wbd_adr_o (wbd_glbl_adr_o ), - .s2_wbd_sel_o (wbd_glbl_sel_o ), - .s2_wbd_we_o (wbd_glbl_we_o ), - .s2_wbd_cyc_o (wbd_glbl_cyc_o ), - .s2_wbd_stb_o (wbd_glbl_stb_o ), + .s2_wbd_dat_i (wbd_adc_dat_i ), + .s2_wbd_ack_i (wbd_adc_ack_i ), + .s2_wbd_dat_o (wbd_adc_dat_o ), + .s2_wbd_adr_o (wbd_adc_adr_o ), + .s2_wbd_sel_o (wbd_adc_sel_o ), + .s2_wbd_we_o (wbd_adc_we_o ), + .s2_wbd_cyc_o (wbd_adc_cyc_o ), + .s2_wbd_stb_o (wbd_adc_stb_o ), // Slave 3 Interface // .s3_wbd_err_i (1'b0 ), - Moved inside IP - .s3_wbd_dat_i (wbd_uart_dat_i ), - .s3_wbd_ack_i (wbd_uart_ack_i ), - .s3_wbd_dat_o (wbd_uart_dat_o ), - .s3_wbd_adr_o (wbd_uart_adr_o ), - .s3_wbd_sel_o (wbd_uart_sel_o ), - .s3_wbd_we_o (wbd_uart_we_o ), - .s3_wbd_cyc_o (wbd_uart_cyc_o ), - .s3_wbd_stb_o (wbd_uart_stb_o ) + .s3_wbd_dat_i (wbd_glbl_dat_i ), + .s3_wbd_ack_i (wbd_glbl_ack_i ), + .s3_wbd_dat_o (wbd_glbl_dat_o ), + .s3_wbd_adr_o (wbd_glbl_adr_o ), + .s3_wbd_sel_o (wbd_glbl_sel_o ), + .s3_wbd_we_o (wbd_glbl_we_o ), + .s3_wbd_cyc_o (wbd_glbl_cyc_o ), + .s3_wbd_stb_o (wbd_glbl_stb_o ) ); -glbl_cfg u_glbl_cfg ( - - .mclk (wbd_clk_glbl ), - .reset_n (wbd_int_rst_n ), - - // Reg Bus Interface Signal - .reg_cs (wbd_glbl_stb_o ), - .reg_wr (wbd_glbl_we_o ), - .reg_addr (wbd_glbl_adr_o ), - .reg_wdata (wbd_glbl_dat_o ), - .reg_be (wbd_glbl_sel_o ), - - // Outputs - .reg_rdata (wbd_glbl_dat_i ), - .reg_ack (wbd_glbl_ack_i ), - - // Risc configuration - .fuse_mhartid (fuse_mhartid ), - .irq_lines (irq_lines ), - .soft_irq (soft_irq ), - .user_irq (user_irq ), - - // SDRAM Config - .cfg_sdr_width (cfg_sdr_width ), - .cfg_colbits (cfg_colbits ), - - /* Parameters */ - .sdr_init_done (sdr_init_done ), - .cfg_req_depth (cfg_req_depth ), //how many req. buffer should hold - .cfg_sdr_en (cfg_sdr_en ), - .cfg_sdr_mode_reg (cfg_sdr_mode_reg ), - .cfg_sdr_tras_d (cfg_sdr_tras_d ), - .cfg_sdr_trp_d (cfg_sdr_trp_d ), - .cfg_sdr_trcd_d (cfg_sdr_trcd_d ), - .cfg_sdr_cas (cfg_sdr_cas ), - .cfg_sdr_trcar_d (cfg_sdr_trcar_d ), - .cfg_sdr_twr_d (cfg_sdr_twr_d ), - .cfg_sdr_rfsh (cfg_sdr_rfsh ), - .cfg_sdr_rfmax (cfg_sdr_rfmax ) - - - ); uart_i2c_usb_top u_uart_i2c_usb ( .uart_rstn (uart_rst_n ), // uart reset .i2c_rstn (i2c_rst_n ), // i2c reset .usb_rstn (usb_rst_n ), // i2c reset .uart_i2c_usb_sel (uart_i2c_usb_sel ), // 0 - uart, 1 - I2C - .app_clk (wbd_clk_uart ), + .app_clk (wbd_clk_int ), .usb_clk (usb_clk ), // Reg Bus Interface Signal - .reg_cs (wbd_uart_stb_o ), - .reg_wr (wbd_uart_we_o ), - .reg_addr (wbd_uart_adr_o[5:2] ), - .reg_wdata (wbd_uart_dat_o ), - .reg_be (wbd_uart_sel_o ), + .reg_cs (wbd_uart_stb_o ), + .reg_wr (wbd_uart_we_o ), + .reg_addr (wbd_uart_adr_o[5:2] ), + .reg_wdata (wbd_uart_dat_o ), + .reg_be (wbd_uart_sel_o ), // Outputs - .reg_rdata (wbd_uart_dat_i ), - .reg_ack (wbd_uart_ack_i ), + .reg_rdata (wbd_uart_dat_i ), + .reg_ack (wbd_uart_ack_i ), // Pad interface - .io_in (io_in [37:36] ), - .io_oeb (io_oeb[37:36] ), - .io_out (io_out[37:36] ) + .scl_pad_i (i2cm_clk_i ), + .scl_pad_o (i2cm_clk_o ), + .scl_pad_oen_o (i2cm_clk_oen ), + + .sda_pad_i (i2cm_data_i ), + .sda_pad_o (i2cm_data_o ), + .sda_padoen_o (i2cm_data_oen ), + + .uart_rxd (uart_rxd ), + .uart_txd (uart_txd ), + + .usb_in_dp (usb_dp_i ), + .usb_in_dn (usb_dn_i ), + + .usb_out_dp (usb_dp_o ), + .usb_out_dn (usb_dn_o ), + .usb_out_tx_oen (usb_oen ) ); -//////////////////////////////////////////////////////////////// -// Clock Skew adjust module -// /////////////////////////////////////////////////////////// -// Wishbone interconnect clock skew control -clk_skew_adjust u_skew_wi - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_wi ), - .clk_out (wbd_clk_wi ) - ); +pinmux u_pinmux( + // System Signals + // Inputs + .mclk (wbd_clk_int ), + .h_reset_n (wbd_int_rst_n ), -// riscv clock skew control -clk_skew_adjust u_skew_riscv - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_riscv ), - .clk_out (wbd_clk_riscv ) - ); + // Reg Bus Interface Signal + .reg_cs (wbd_glbl_stb_o ), + .reg_wr (wbd_glbl_we_o ), + .reg_addr (wbd_glbl_adr_o ), + .reg_wdata (wbd_glbl_dat_o ), + .reg_be (wbd_glbl_sel_o ), -// uart clock skew control -clk_skew_adjust u_skew_uart - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_uart ), - .clk_out (wbd_clk_uart ) - ); + // Outputs + .reg_rdata (wbd_glbl_dat_i ), + .reg_ack (wbd_glbl_ack_i ), -// spi clock skew control -clk_skew_adjust u_skew_spi - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_spi ), - .clk_out (wbd_clk_spi ) - ); -// sdram clock skew control -clk_skew_adjust u_skew_sdram - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_sdram ), - .clk_out (wbd_clk_sdram ) - ); + // Risc configuration + .fuse_mhartid (fuse_mhartid ), + .irq_lines (irq_lines ), + .soft_irq (soft_irq ), + .user_irq (user_irq ), -// global clock skew control -clk_skew_adjust u_skew_glbl - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_glbl ), - .clk_out (wbd_clk_glbl ) - ); + // Digital IO + .digital_io_out (io_out ), + .digital_io_oen (io_oeb ), + .digital_io_in (io_in ), -// wb_host clock skew control -clk_skew_adjust u_skew_wh - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_wh ), - .clk_out (wbd_clk_wh ) - ); + // SFLASH I/F + .sflash_sck (sflash_sck ), + .sflash_ss (sflash_ss ), + .sflash_oen (sflash_oen ), + .sflash_do (sflash_do ), + .sflash_di (sflash_di ), -// SDRAM clock out clock skew control -clk_skew_adjust u_skew_sd_co - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (sdram_clk ), - .sel (cfg_cska_sd_co ), - .clk_out (io_out[29] ) - ); + // SSRAM I/F + .ssram_sck (sflash_sck ), + .ssram_ss (sflash_ss ), + .ssram_oen (sflash_oen ), + .ssram_do ( ), + .ssram_di (sflash_di ), -// Clock Skey for PAD SDRAM clock -clk_skew_adjust u_skew_sd_ci - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (io_in[29] ), - .sel (cfg_cska_sd_ci ), - .clk_out (io_in_29_ ) - ); + // USB I/F + .usb_dp_o (usb_dp_o ), + .usb_dn_o (usb_dn_o ), + .usb_oen (usb_oen ), + .usb_dp_i (usb_dp_i ), + .usb_dn_i (usb_dn_i ), -// Clock Skey for SPI clock out -clk_skew_adjust u_skew_sp_co - ( + // UART I/F + .uart_txd (uart_txd ), + .uart_rxd (uart_rxd ), + + // I2CM I/F + .i2cm_clk_o (i2cm_clk_o ), + .i2cm_clk_i (i2cm_clk_i ), + .i2cm_clk_oen (i2cm_clk_oen ), + .i2cm_data_oen (i2cm_data_oen ), + .i2cm_data_o (i2cm_data_o ), + .i2cm_data_i (i2cm_data_i ), + + // SPI MASTER + .spim_sck (sflash_sck ), + .spim_ss (sflash_ss ), + .spim_miso ( ), + .spim_mosi (sflash_di[0] ), + + .pulse1m_mclk (pulse1m_mclk ), + + .pinmux_debug (pinmux_debug ) + ); + +sar_adc u_adc ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1),// User area 1 1.8V supply + .vssd1 (vssd1),// User area 1 digital ground + .vccd2 (vccd2),// User area 2 1.8V supply (analog) + .vssd2 (vssd2),// User area 2 ground (analog) `endif - .clk_in (io_in_30_ ), - .sel (cfg_cska_sp_co ), - .clk_out (io_out[30] ) - ); + + + .clk (wbd_clk_int),// The clock (digital) + .reset_n (wbd_int_rst_n),// Active low reset (digital) + + // Reg Bus Interface Signal + .reg_cs (wbd_adc_stb_o ), + .reg_wr (wbd_adc_we_o ), + .reg_addr (wbd_adc_adr_o[7:0] ), + .reg_wdata (wbd_adc_dat_o ), + .reg_be (wbd_adc_sel_o ), + + // Outputs + .reg_rdata (wbd_adc_dat_i ), + .reg_ack (wbd_adc_ack_i ), + + .pulse1m_mclk (pulse1m_mclk), + + + // DAC I/F + .sar2dac (sar2dac ), + .analog_dac_out (analog_dac_out) , + + // ADC Input + .analog_din(analog_io[5:0]) // (Analog) + +); + + +DAC_8BIT u_dac ( + `ifdef USE_POWER_PINS + .vdd(vccd2), + .gnd(vssd2), + `endif + .d0(sar2dac[0]), + .d1(sar2dac[1]), + .d2(sar2dac[2]), + .d3(sar2dac[3]), + .d4(sar2dac[4]), + .d5(sar2dac[5]), + .d6(sar2dac[6]), + .d7(sar2dac[7]), + .inp1(analog_io[6]), + .out_v(analog_dac_out) + ); + + + endmodule : user_project_wrapper
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index 77a0163..05ed8f8 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -160,7 +160,7 @@ // input logic s3_wbd_err_i, output logic [31:0] s3_wbd_dat_o, output logic [7:0] s3_wbd_adr_o, - output logic s3_wbd_sel_o, + output logic [3:0] s3_wbd_sel_o, output logic s3_wbd_we_o, output logic s3_wbd_cyc_o, output logic s3_wbd_stb_o @@ -323,7 +323,7 @@ assign s3_wbd_dat_o = s3_wb_wr.wbd_dat[31:0] ; assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[7:0] ; // Global Reg Need 8 bit - assign s3_wbd_sel_o = s3_wb_wr.wbd_sel[0] ; + assign s3_wbd_sel_o = s3_wb_wr.wbd_sel[3:0] ; assign s3_wbd_we_o = s3_wb_wr.wbd_we ; assign s3_wbd_cyc_o = s3_wb_wr.wbd_cyc ; assign s3_wbd_stb_o = s3_wb_wr.wbd_stb ;