SRAM Magric DRC fix using metal blockage around SRAM
diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz
index 1acfa1b..d735a9b 100644
--- a/def/user_project_wrapper.def.gz
+++ b/def/user_project_wrapper.def.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 7810dd4..35153a1 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 8a87194..00ae0ef 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index cbcbb2c..059865a 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ
diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz
index c25b8ed..412c5b7 100644
--- a/maglef/user_project_wrapper.mag.gz
+++ b/maglef/user_project_wrapper.mag.gz
Binary files differ
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 56d0de3..42c15e0 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -104,10 +104,18 @@
# Add Blockage arond the SRAM to avoid Magic DRC &
# add signal routing blockage for met5
-set ::env(GLB_RT_OBS) "li1 300.00 1500.00 983.10 1916.54, \
- met1 300.00 1500.00 983.10 1916.54, \
- met2 300.00 1500.00 983.10 1916.54, \
- met3 300.00 1500.00 983.10 1916.54, \
+set ::env(GLB_RT_OBS) "met1 2000.00 800.00 2683.10 1216.54, \
+ met2 2000.00 800.00 2683.10 1216.54, \
+ met3 2000.00 800.00 2683.10 1216.54, \
+ met1 2000.00 1400.00 2683.10 1816.54, \
+ met2 2000.00 1400.00 2683.10 1816.54, \
+ met3 2000.00 1400.00 2683.10 1816.54, \
+ met1 2000.00 2000.00 2479.78 2397.5, \
+ met2 2000.00 2000.00 2479.78 2397.5, \
+ met3 2000.00 2000.00 2479.78 2397.5, \
+ met1 2000.00 2600.00 2479.78 2997.5, \
+ met2 2000.00 2600.00 2479.78 2997.5, \
+ met3 2000.00 2600.00 2479.78 2997.5, \
met5 0 0 2920 3520"
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 8892364..337164d 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h18m16s,-1,2.1404109589041096,10.2784,1.0702054794520548,-1,512.0,11,0,0,0,0,0,0,-1,0,0,-1,-1,996902,6096,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.05,2.28,2.21,0.08,0.13,-1,148,1674,148,1674,0,0,0,11,0,0,0,0,0,0,0,4,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h17m48s,-1,2.1404109589041096,10.2784,1.0702054794520548,-1,513.64,11,0,0,0,0,0,0,-1,0,0,-1,-1,997274,6085,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.05,2.19,2.14,0.11,0.14,-1,148,1674,148,1674,0,0,0,11,0,0,0,0,0,0,0,4,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 4841e2b..475c4d8 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ
