jobs/mpw_precheck/a93c4454-7440-44e7-833e-292d286b5c2e/logs/spdx_compliance_report.log

/root/logic_bist/Makefile
/root/logic_bist/docs/environment.yml
/root/logic_bist/docs/Makefile
/root/logic_bist/docs/source/index.rst
/root/logic_bist/docs/source/conf.py
/root/logic_bist/sta/Makefile
/root/logic_bist/sta/run_sta
/root/logic_bist/sta/scripts/or_write_verilog.tcl
/root/logic_bist/sta/scripts/sta.tcl
/root/logic_bist/sta/scripts/caravel_timing.tcl
/root/logic_bist/sta/scripts/sta_block.tcl
/root/logic_bist/sta/sdc/scan.sdc
/root/logic_bist/sta/sdc/func.sdc
/root/logic_bist/sta/sdc/caravel.sdc
/root/logic_bist/verilog/dv/Makefile
/root/logic_bist/verilog/dv/la_test2/la_test2_tb.v
/root/logic_bist/verilog/dv/la_test2/la_test2.c
/root/logic_bist/verilog/dv/la_test2/Makefile
/root/logic_bist/verilog/dv/agents/uart_master_tasks.sv
/root/logic_bist/verilog/dv/agents/uart_agent.v
/root/logic_bist/verilog/dv/uart_master/Makefile
/root/logic_bist/verilog/dv/uart_master/run_verilog
/root/logic_bist/verilog/dv/uart_master/uart_master_tb.v
/root/logic_bist/verilog/dv/uart_master/uart_master.c
/root/logic_bist/verilog/dv/la_test1/la_test1.c
/root/logic_bist/verilog/dv/la_test1/Makefile
/root/logic_bist/verilog/dv/la_test1/la_test1_tb.v
/root/logic_bist/verilog/dv/user_uart_master/Makefile
/root/logic_bist/verilog/dv/user_uart_master/user_uart_master_tb.v
/root/logic_bist/verilog/dv/user_uart_master/user_uart.c
/root/logic_bist/verilog/dv/user_uart_master/run_iverilog
/root/logic_bist/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
/root/logic_bist/verilog/dv/user_mbist_test1/Makefile
/root/logic_bist/verilog/dv/user_mbist_test1/run_iverilog
/root/logic_bist/verilog/dv/user_lbist/Makefile
/root/logic_bist/verilog/dv/user_lbist/user_lbist_tb.v
/root/logic_bist/verilog/dv/user_basic/user_basic_tb.v
/root/logic_bist/verilog/dv/user_basic/Makefile
/root/logic_bist/verilog/dv/wb_port/wb_port_tb.v
/root/logic_bist/verilog/dv/wb_port/Makefile
/root/logic_bist/verilog/dv/wb_port/wb_port.c
/root/logic_bist/verilog/dv/wb_port/run_iverilog
/root/logic_bist/verilog/rtl/uprj_netlists.v
/root/logic_bist/verilog/rtl/user_project_wrapper.v
/root/logic_bist/verilog/rtl/wb_interconnect/src/run_verilator
/root/logic_bist/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
/root/logic_bist/verilog/rtl/wb_interconnect/src/run_iverilog
/root/logic_bist/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
/root/logic_bist/verilog/rtl/sram_macros/sky130_sram_1kbyte_1rw1r_32x256_8.v
/root/logic_bist/verilog/rtl/wb_host/src/run_verilator
/root/logic_bist/verilog/rtl/wb_host/src/run_iverilog
/root/logic_bist/verilog/rtl/wb_host/src/wb_host.sv
/root/logic_bist/verilog/rtl/uart2wb/src/run_verilog
/root/logic_bist/verilog/rtl/uart2wb/src/uart2_core.sv
/root/logic_bist/verilog/rtl/uart2wb/src/uart_msg_handler.v
/root/logic_bist/verilog/rtl/uart2wb/src/uart2wb.sv
/root/logic_bist/verilog/rtl/mbist/run_verilator
/root/logic_bist/verilog/rtl/mbist/run_iverilog
/root/logic_bist/verilog/rtl/mbist/include/mbist_def.svh
/root/logic_bist/verilog/rtl/mbist/src/top/mbist_top2.sv
/root/logic_bist/verilog/rtl/mbist/src/top/mbist_top1.sv
/root/logic_bist/verilog/rtl/mbist/src/core/mbist_sti_sel.sv
/root/logic_bist/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
/root/logic_bist/verilog/rtl/mbist/src/core/mbist_fsm.sv
/root/logic_bist/verilog/rtl/mbist/src/core/mbist_pat_sel.sv
/root/logic_bist/verilog/rtl/mbist/src/core/mbist_addr_gen.sv
/root/logic_bist/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
/root/logic_bist/verilog/rtl/mbist/src/core/mbist_data_cmp.sv
/root/logic_bist/verilog/rtl/mbist/src/core/mbist_mux.sv
/root/logic_bist/verilog/rtl/mbist/src/core/mbist_op_sel.sv
/root/logic_bist/verilog/rtl/uart/src/uart_cfg.sv
/root/logic_bist/verilog/rtl/uart/src/uart_core.sv
/root/logic_bist/verilog/rtl/uart/src/uart_txfsm.sv
/root/logic_bist/verilog/rtl/uart/src/uart_rxfsm.sv
/root/logic_bist/verilog/rtl/clk_skew_adjust/synth/synth.tcl
/root/logic_bist/verilog/rtl/clk_skew_adjust/synth/Makefile
/root/logic_bist/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v
/root/logic_bist/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
/root/logic_bist/verilog/rtl/lib/pulse_gen_type1.sv
/root/logic_bist/verilog/rtl/lib/async_fifo.sv
/root/logic_bist/verilog/rtl/lib/clk_gate.sv
/root/logic_bist/verilog/rtl/lib/ctech_cells.sv
/root/logic_bist/verilog/rtl/lib/wb_interface.v
/root/logic_bist/verilog/rtl/lib/reset_sync.sv
/root/logic_bist/verilog/rtl/lib/ser_inf_32b.sv
/root/logic_bist/verilog/rtl/lib/async_reg_bus.sv
/root/logic_bist/verilog/rtl/lib/clk_buf.v
/root/logic_bist/verilog/rtl/lib/pulse_gen_type2.sv
/root/logic_bist/verilog/rtl/lib/registers.v
/root/logic_bist/verilog/rtl/lib/sync_fifo.sv
/root/logic_bist/verilog/rtl/lib/async_fifo_th.sv
/root/logic_bist/verilog/rtl/lib/wb_stagging.sv
/root/logic_bist/verilog/rtl/lib/wb_arb.sv
/root/logic_bist/verilog/rtl/lib/double_sync_low.v
/root/logic_bist/verilog/rtl/lib/crc_32.sv
/root/logic_bist/verilog/rtl/lib/async_wb.sv
/root/logic_bist/verilog/rtl/lib/double_sync_high.v
/root/logic_bist/verilog/rtl/lib/clk_ctl.v
/root/logic_bist/verilog/rtl/lbist/src/lbist_reg.sv
/root/logic_bist/verilog/rtl/lbist/src/lbist_core.sv
/root/logic_bist/verilog/rtl/lbist/src/run_compile
/root/logic_bist/verilog/rtl/lbist/src/lbist_top.sv
/root/logic_bist/hacks/src/OpenROAD/Resizer.cc
/root/logic_bist/hacks/src/openlane/synth.tcl
/root/logic_bist/hacks/src/openlane/io_place.py
/root/logic_bist/hacks/src/openlane/synth_top.tcl
/root/logic_bist/hacks/src/OpenSTA/tcl/Sta.tcl
/root/logic_bist/hacks/src/OpenSTA/tcl/NetworkEdit.tcl
/root/logic_bist/hacks/src/OpenSTA/network/ConcreteNetwork.cc
/root/logic_bist/hacks/patch/scan_swap.patch
/root/logic_bist/hacks/patch/resizer.patch
/root/logic_bist/openlane/Makefile
/root/logic_bist/openlane/wb_interconnect/pdn.tcl
/root/logic_bist/openlane/wb_interconnect/base.sdc
/root/logic_bist/openlane/wb_interconnect/sta.tcl
/root/logic_bist/openlane/wb_interconnect/config.tcl
/root/logic_bist/openlane/wb_interconnect/interactive.tcl
/root/logic_bist/openlane/mbist1/base.sdc
/root/logic_bist/openlane/mbist1/sta.tcl
/root/logic_bist/openlane/mbist1/config.tcl
/root/logic_bist/openlane/mbist1/interactive.tcl
/root/logic_bist/openlane/wb_host/base.sdc
/root/logic_bist/openlane/wb_host/config.tcl
/root/logic_bist/openlane/wb_host/interactive.tcl
/root/logic_bist/openlane/scripts/scan_connect.tcl
/root/logic_bist/openlane/scripts/scan_swap.tcl
/root/logic_bist/openlane/mbist2/base.sdc
/root/logic_bist/openlane/mbist2/sta.tcl
/root/logic_bist/openlane/mbist2/config.tcl
/root/logic_bist/openlane/mbist2/interactive.tcl
/root/logic_bist/openlane/user_project_wrapper/pdn.tcl
/root/logic_bist/openlane/user_project_wrapper/base.sdc
/root/logic_bist/openlane/user_project_wrapper/sta.tcl
/root/logic_bist/openlane/user_project_wrapper/config.tcl
/root/logic_bist/openlane/user_project_wrapper/interactive.tcl
/root/logic_bist/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
/root/logic_bist/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
/root/logic_bist/spef/mbist_top1.spef
/root/logic_bist/spef/user_project_wrapper.spef
/root/logic_bist/spef/wb_host.spef
/root/logic_bist/spef/glbl_cfg.spef
/root/logic_bist/spef/mbist_top2.spef
/root/logic_bist/spef/wb_interconnect.spef