26a9d65814f88b6dd3d28d74c40f85015c98566b - third_party/shuttle/sky130/mpw-004/slot-012 - Git at Google

commit	26a9d65814f88b6dd3d28d74c40f85015c98566b	[log] [tgz]
author	Klas Nordmark <klas.nordmark.se@ieee.org>	Thu Dec 30 21:23:53 2021 +0100
committer	Klas Nordmark <klas.nordmark.se@ieee.org>	Thu Dec 30 21:23:53 2021 +0100
tree	00e91b1496b17223ac1ea1408e60215cd57b0e38
parent	fc583ec64d0e153d10e4e28146342af0d0fecd6e [diff]

Initial commit, subservient for MPW4

README.md[diff]
def/user_project_wrapper.def[diff]
gds/subservient_wrapped.gds.gz[Added - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_proj_example.gds.gz[Added - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/subservient_wrapped.lef[Added - diff]
lef/user_project_wrapper.lef[diff]
mag/subservient_wrapped.mag[Added - diff]
mag/user_project_wrapper.mag[diff]
maglef/subservient_wrapped.mag[Added - diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_project_wrapper/config.tcl[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/subservient_blinky/Makefile[Renamed from verilog/dv/mprj_stimulus/Makefile - diff]
verilog/dv/subservient_blinky/subservient_blinky.c[Added - diff]
verilog/dv/subservient_blinky/subservient_blinky.hex[Added - diff]
verilog/dv/subservient_blinky/subservient_blinky.vcd.gz[Added - diff]
verilog/dv/subservient_blinky/subservient_blinky_tb.v[Added - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]
verilog/gl/defines.v[Added - diff]
verilog/gl/subservient_wrapped.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/ff_ram.v[Added - diff]
verilog/rtl/serv_alu.v[Added - diff]
verilog/rtl/serv_bufreg.v[Added - diff]
verilog/rtl/serv_csr.v[Added - diff]
verilog/rtl/serv_ctrl.v[Added - diff]
verilog/rtl/serv_decode.v[Added - diff]
verilog/rtl/serv_immdec.v[Added - diff]
verilog/rtl/serv_mem_if.v[Added - diff]
verilog/rtl/serv_rf_if.v[Added - diff]
verilog/rtl/serv_rf_ram.v[Added - diff]
verilog/rtl/serv_rf_ram_if.v[Added - diff]
verilog/rtl/serv_rf_top.v[Added - diff]
verilog/rtl/serv_state.v[Added - diff]
verilog/rtl/serv_top.v[Added - diff]
verilog/rtl/serving.v[Added - diff]
verilog/rtl/serving_arbiter.v[Added - diff]
verilog/rtl/serving_mux.v[Added - diff]
verilog/rtl/serving_ram.v[Added - diff]
verilog/rtl/subservient.v[Added - diff]
verilog/rtl/subservient_core.v[Added - diff]
verilog/rtl/subservient_debug_switch.v[Added - diff]
verilog/rtl/subservient_gpio.v[Added - diff]
verilog/rtl/subservient_ram.v[Added - diff]
verilog/rtl/subservient_rf_ram_if.v[Added - diff]
verilog/rtl/subservient_wrapped.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

67 files changed

tree: 00e91b1496b17223ac1ea1408e60215cd57b0e38

README.md

Subservient

This project constists of an ASIC-adapted version of the award-winning bit-serial RISC-V processor SERV. The macro was built from the subservient_wrapped repository linked later, which combines Subservient with 512 bytes of RAM (generated from RTL, as no satisfactory memory compiler was available in good time), used both as main memory and register file. For more information on subservient_wrapped, subservient and SERV, the original repositories can be accessed below. The repositories depend on each other through the Fusesoc packet management and tool abstraction system - this project was created to demonstrate Fusesoc in an ASIC context.

https://github.com/klasnordmark/subservient_wrapped

https://github.com/olofk/subservient

https://github.com/olofk/serv

Usage

Subservient has access to the outside world through io_out[1]. To access it from the Caravel management processor (which is how you would program Subservient), keep it in “debug” mode by holding la_data_in[0] low. In this state, the 512 byte memory is accessible by the Caravel management processor over the Wishbone interface and Subservient does not run. The subservient_blinky full chip test included under verilog/dv gives an example of this, programming Subservient with a small ‘blink’ program toggling io_out[1].