Merge branch 'main' of github.com:giraypultar/keyvalue_caravel
diff --git a/.github/scripts/build/run-set-id.sh b/.github/scripts/build/run-set-id.sh
index b6e9cfb..9cb87f8 100644
--- a/.github/scripts/build/run-set-id.sh
+++ b/.github/scripts/build/run-set-id.sh
@@ -24,7 +24,7 @@
cd $UPRJ_ROOT
# Install full version of caravel
-git clone https://github.com/efabless/caravel --branch develop --depth 1 $CARAVEL_ROOT
+git clone https://github.com/efabless/caravel --depth 1 $CARAVEL_ROOT
LOG_FILE=out.log
docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; export USER_ID=$USER_ID; make set_user_id | tee $LOG_FILE;"
@@ -35,4 +35,4 @@
exit 2;
fi
-exit 0
\ No newline at end of file
+exit 0
diff --git a/.github/scripts/build/run-ship.sh b/.github/scripts/build/run-ship.sh
index 0217dbc..d084c00 100644
--- a/.github/scripts/build/run-ship.sh
+++ b/.github/scripts/build/run-ship.sh
@@ -23,9 +23,11 @@
cd $UPRJ_ROOT
# Install full version of caravel
-git clone https://github.com/efabless/caravel --branch develop --depth 1 $CARAVEL_ROOT
+git clone https://github.com/efabless/caravel --depth 1 $CARAVEL_ROOT
-docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; make ship;"
+make install_mcw
+
+docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; make -f $CARAVEL_ROOT/Makefile ship;"
SHIP_FILE=$UPRJ_ROOT/gds/caravel.gds
diff --git a/.github/workflows/auto_update_submodule.yml b/.github/workflows/auto_update_submodule.yml
deleted file mode 100644
index 7219ddf..0000000
--- a/.github/workflows/auto_update_submodule.yml
+++ /dev/null
@@ -1,41 +0,0 @@
-
-name: 'Auto-update Submodules'
-
-on:
- workflow_dispatch:
- schedule:
- - cron: "0 0 * * *"
-
-jobs:
- sync:
- name: 'Auto-update Submodules'
- runs-on: ubuntu-latest
-
- # Use the Bash shell regardless whether the GitHub Actions runner is ubuntu-latest, macos-latest, or windows-latest
- defaults:
- run:
- shell: bash
-
- steps:
- # Checkout the repository to the GitHub Actions runner
- - name: Checkout
- uses: actions/checkout@v2
- with:
- submodules: true
-
- # Git config
- - name: Git Configurations
- run: |
- git config --global user.name 'Git bot'
- git config --global user.email 'bot@noreply.github.com'
-
- # Update references
- - name: Git Sumbodule Update
- run: |
- git submodule update --init --recursive
- git submodule update --remote --recursive
-
- - name: Commit update
- run: |
- git remote set-url origin https://x-access-token:${{ secrets.GITHUB_TOKEN }}@github.com/${{ github.repository }}
- git commit -am "Auto updated submodule references" && git push || echo "No changes to commit"
diff --git a/.github/workflows/caravel_build.yml b/.github/workflows/caravel_build.yml
index c615662..3978d7f 100644
--- a/.github/workflows/caravel_build.yml
+++ b/.github/workflows/caravel_build.yml
@@ -13,8 +13,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -25,19 +23,17 @@
- name: Install The PDK
run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/pdkBuild.sh
env:
- OPENLANE_TAG: 2021.09.16_03.28.21
+ OPENLANE_TAG: 2021.12.17_05.07.41
- name: Run make ship
run: bash ${GITHUB_WORKSPACE}/.github/scripts/build/run-ship.sh
env:
- OPENLANE_TAG: 2021.09.16_03.28.21
+ OPENLANE_TAG: 2021.12.17_05.07.41
set_user_id:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -59,8 +55,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml
index 5b8ea91..9196114 100644
--- a/.github/workflows/user_project_ci.yml
+++ b/.github/workflows/user_project_ci.yml
@@ -14,8 +14,6 @@
timeout-minutes: 720
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -34,8 +32,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -53,8 +49,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -78,8 +72,6 @@
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- with:
- submodules: 'true'
- name: Set up QEMU
uses: docker/setup-qemu-action@v1
@@ -97,4 +89,4 @@
- name: Run DV tests
# Run test number 0,1,2,3,4 in one job <test-ids> <sim-mode>
- run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0,1,2,3,4 GL
\ No newline at end of file
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0,1,2,3,4 GL
diff --git a/.gitmodules b/.gitmodules
index c73b442..0ba8b09 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,3 @@
-[submodule "caravel-lite"]
- path = caravel
- url = https://github.com/efabless/caravel-lite
+[submodule "verilog/rtl/wrapped_keyvalue"]
+ path = verilog/rtl/wrapped_keyvalue
+ url = https://github.com/giraypultar/wrapped_keyvalue
diff --git a/Makefile b/Makefile
index 188e997..9fc63bd 100644
--- a/Makefile
+++ b/Makefile
@@ -24,15 +24,13 @@
ifeq ($(CARAVEL_LITE),1)
CARAVEL_NAME := caravel-lite
CARAVEL_REPO := https://github.com/efabless/caravel-lite
- CARAVEL_BRANCH := main
+ CARAVEL_TAG := 'rc-8'
else
CARAVEL_NAME := caravel
CARAVEL_REPO := https://github.com/efabless/caravel
- CARAVEL_BRANCH := master
+ CARAVEL_TAG := 'rc-8'
endif
-# Install caravel as submodule, (1): submodule, (0): clone
-SUBMODULE?=1
# Include Caravel Makefile Targets
.PHONY: % : check-caravel
@@ -72,19 +70,8 @@
# Install caravel
.PHONY: install
install:
-ifeq ($(SUBMODULE),1)
- @echo "Installing $(CARAVEL_NAME) as a submodule.."
-# Convert CARAVEL_ROOT to relative path because .gitmodules doesn't accept '/'
- $(eval CARAVEL_PATH := $(shell realpath --relative-to=$(shell pwd) $(CARAVEL_ROOT)))
- @if [ ! -d $(CARAVEL_ROOT) ]; then git submodule add --name $(CARAVEL_NAME) $(CARAVEL_REPO) $(CARAVEL_PATH); fi
- @git submodule update --init
- @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
- $(MAKE) simlink
-else
@echo "Installing $(CARAVEL_NAME).."
- @git clone $(CARAVEL_REPO) $(CARAVEL_ROOT)
- @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
-endif
+ @git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
# Create symbolic links to caravel's main files
.PHONY: simlink
@@ -102,30 +89,12 @@
# Update Caravel
.PHONY: update_caravel
update_caravel: check-caravel
-ifeq ($(SUBMODULE),1)
- @git submodule update --init --recursive
- cd $(CARAVEL_ROOT) && \
- git checkout $(CARAVEL_BRANCH) && \
- git pull
-else
- cd $(CARAVEL_ROOT)/ && \
- git checkout $(CARAVEL_BRANCH) && \
- git pull
-endif
+ cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull
# Uninstall Caravel
.PHONY: uninstall
uninstall:
-ifeq ($(SUBMODULE),1)
- git config -f .gitmodules --remove-section "submodule.$(CARAVEL_NAME)"
- git add .gitmodules
- git submodule deinit -f $(CARAVEL_ROOT)
- git rm --cached $(CARAVEL_ROOT)
- rm -rf .git/modules/$(CARAVEL_NAME)
rm -rf $(CARAVEL_ROOT)
-else
- rm -rf $(CARAVEL_ROOT)
-endif
# Install Openlane
.PHONY: openlane
diff --git a/README.md b/README.md
index 17a85df..b156934 100644
--- a/README.md
+++ b/README.md
@@ -1,13 +1,7 @@
-# Caravel User Project
+# Key value store
[](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
-## Please fill in your project documentation in this README.md file
-
-
-Refer to [README](docs/source/index.rst) for this sample project documentation.
-
-
.. raw:: html
<!---
@@ -28,454 +22,25 @@
# SPDX-License-Identifier: Apache-2.0
-->
-Caravel User Project
+ASIC Key Value Store
====================
-|License| |User CI| |Caravel Build|
-
-Table of contents
-=================
-
-- `Overview <#overview>`__
-- `Install Caravel <#install-caravel>`__
-- `Caravel Integration <#caravel-integration>`__
-
- - `Repo Integration <#repo-integration>`__
- - `Verilog Integration <#verilog-integration>`__
- - `Layout Integration <#layout-integration>`__
-
-- `Running Full Chip Simulation <#running-full-chip-simulation>`__
-- `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__
-- `Hardening the User Project using
- Openlane <#hardening-the-user-project-using-openlane>`__
-- `Checklist for Open-MPW
- Submission <#checklist-for-open-mpw-submission>`__
-
Overview
-========
-
-This repo contains a sample user project that utilizes the
+-----------------
+This repo contains a key value store that utilizes the
`caravel <https://github.com/efabless/caravel.git>`__ chip user space.
-The user project is a simple counter that showcases how to make use of
-`caravel's <https://github.com/efabless/caravel.git>`__ user space
-utilities like IO pads, logic analyzer probes, and wishbone port. The
-repo also demonstrates the recommended structure for the open-mpw
-shuttle projects.
-Prerequisites
-=============
+This repo has been cloned from:
-- Docker
+https://github.com/efabless/caravel_user_project
-Install Caravel
-===============
+for MPW-3
-To setup caravel, run the following:
+More info on how to build and use this is in the caravel_user_project repo.
-.. code:: bash
+Source
+--------
- # If unset, CARAVEL_ROOT will be set to $(pwd)/caravel
- # If you want to install caravel at a different location, run "export CARAVEL_ROOT=<caravel-path>"
- export CARAVEL_ROOT=$(pwd)/caravel
+The migen and RTL source can be found in:
- # Disable submodule installation if needed by, run "export SUBMODULE=0"
-
- git clone https://github.com/efabless/caravel_user_project.git
- cd caravel_user_project
- make install
-
-To update the installed caravel to the latest, run:
-
-.. code:: bash
-
- make update_caravel
-
-To remove caravel, run
-
-.. code:: bash
-
- make uninstall
-
-By default
-`caravel-lite <https://github.com/efabless/caravel-lite.git>`__ is
-installed. To install the full version of caravel, run this prior to
-calling make install.
-
-.. code:: bash
-
- export CARAVEL_LITE=0
-
-Caravel Integration
-===================
-
-Repo Integration
-----------------
-
-Caravel files are kept separate from the user project by having caravel
-as submodule. The submodule commit should point to the latest of
-caravel/caravel-lite master/main branch. The following files should have a symbolic
-link to `caravel's <https://github.com/efabless/caravel.git>`__
-corresponding files:
-
-- `Openlane Makefile <../../openlane/Makefile>`__: This provides an easier
- way for running openlane to harden your macros. Refer to `Hardening
- the User Project Macro using
- Openlane <#hardening-the-user-project-macro-using-openlane>`__. Also,
- the makefile retains the openlane summary reports under the signoff
- directory.
-
-- `Pin order <../../openlane/user_project_wrapper/pin_order.cfg>`__ file for
- the user wrapper: The hardened user project wrapper macro must have
- the same pin order specified in caravel's repo. Failing to adhere to
- the same order will fail the gds integration of the macro with
- caravel's back-end.
-
-The symbolic links are automatically set when you run ``make install``.
-
-Verilog Integration
--------------------
-
-You need to create a wrapper around your macro that adheres to the
-template at
-`user\_project\_wrapper <https://github.com/efabless/caravel/blob/master/verilog/rtl/__user_project_wrapper.v>`__.
-The wrapper top module must be named ``user_project_wrapper`` and must
-have the same input and output ports as the golden wrapper `template <https://github.com/efabless/caravel/blob/master/verilog/rtl/__user_project_wrapper.v>`__. The wrapper gives access to the
-user space utilities provided by caravel like IO ports, logic analyzer
-probes, and wishbone bus connection to the management SoC.
-
-For this sample project, the user macro makes use of:
-
-- The IO ports for displaying the count register values on the IO pads.
-
-- The LA probes for supplying an optional reset and clock signals and
- for setting an initial value for the count register.
-
-- The wishbone port for reading/writing the count value through the
- management SoC.
-
-Refer to `user\_project\_wrapper <../../verilog/rtl/user_project_wrapper.v>`__
-for more information.
-
-.. raw:: html
-
- <p align="center">
- <img src="./_static/counter_32.png" width="50%" height="50%">
- </p>
-
-.. raw:: html
-
- </p>
-
-
-Layout Integration
--------------------
-
-The caravel layout is pre-designed with an empty golden wrapper in the user space. You only need to provide us with a valid ``user_project_wrapper`` GDS file. And, as part of the tapeout process, your hardened ``user_project_wrapper`` will be inserted into a vanilla caravel layout to get the final layout shipped for fabrication.
-
-.. raw:: html
-
- <p align="center">
- <img src="./_static/layout.png" width="80%" height="80%">
- </p>
-
-To make sure that this integration process goes smoothly without having any DRC or LVS issues, your hardened ``user_project_wrapper`` must adhere to a number of requirements listed at `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__ .
-
-
-Building the PDK
-================
-
-You have two options for building the pdk:
-
-- Build the pdk natively.
-
-Make sure you have `Magic VLSI Layout Tool <http://opencircuitdesign.com/magic/index.html>`__ installed on your machine before building the pdk.
-The pdk build is tested with magic version ``8.3.209``.
-
-.. code:: bash
-
- # set PDK_ROOT to the path you wish to use for the pdk
- export PDK_ROOT=<pdk-installation-path>
-
- # you can optionally specify skywater-pdk and open-pdks commit used
- # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
- # if you do not set them, they default to the last verfied commits tested for this project
-
- make pdk
-
-- Build the pdk using openlane's docker image which has magic installed.
-
-.. code:: bash
-
- # set PDK_ROOT to the path you wish to use for the pdk
- export PDK_ROOT=<pdk-installation-path>
-
- # you can optionally specify skywater-pdk and open-pdks commit used
- # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
- # if you do not set them, they default to the last verfied commits tested for this project
-
- make pdk-nonnative
-
-Running Full Chip Simulation
-============================
-
-First, you will need to install the simulation environment, by
-
-.. code:: bash
-
- make simenv
-
-This will pull a docker image with the needed tools installed.
-
-Then, run the RTL simulation by
-
-.. code:: bash
-
- export PDK_ROOT=<pdk-installation-path>
- export CARAVEL_ROOT=$(pwd)/caravel
- # specify simulation mode: RTL/GL
- export SIM=RTL
- # Run RTL simulation on IO ports testbench, make verify-io_ports
- make verify-<testbench-name>
-
-Once you have the physical implementation done and you have the gate-level netlists ready, it is crucial to run full gate-level simulations to make sure that your design works as intended after running the physical implementation.
-
-Run the gate-level simulation by:
-
-.. code:: bash
-
- export PDK_ROOT=<pdk-installation-path>
- export CARAVEL_ROOT=$(pwd)/caravel
- # specify simulation mode: RTL/GL
- export SIM=GL
- # Run RTL simulation on IO ports testbench, make verify-io_ports
- make verify-<testbench-name>
-
-
-This sample project comes with four example testbenches to test the IO port connection, wishbone interface, and logic analyzer. The test-benches are under the
-`verilog/dv <https://github.com/efabless/caravel_user_project/tree/main/verilog/dv>`__ directory. For more information on setting up the
-simulation environment and the available testbenches for this sample
-project, refer to `README <https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/README.md>`__.
-
-
-User Project Wrapper Requirements
-=================================
-
-Your hardened ``user_project_wrapper`` must match the `golden user_project_wrapper <https://github.com/efabless/caravel/blob/master/gds/user_project_wrapper_empty.gds.gz>`__ in the following:
-
-- Area ``(2.920um x 3.520um)``
-- Top module name ``"user_project_wrapper"``
-- Pin Placement
-- Pin Sizes
-- Core Rings Width and Offset
-- PDN Vertical and Horizontal Straps Width
-
-
-.. raw:: html
-
- <p align="center">
- <img src="./_static/empty.png" width="40%" height="40%">
- </p>
-
-
-These fixed configurations are specified `here <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>`__ .
-
-However, you are allowed to change the following if you need to:
-
-- PDN Vertical and Horizontal Pitch & Offset
-
-.. raw:: html
-
- <p align="center">
- <img src="./_static/pitch.png" width="30%" height="30%">
- </p>
-
-To make sure that you adhere to these requirements, we run an exclusive-or (XOR) check between your hardened ``user_project_wrapper`` GDS and the golden wrapper GDS after processing both layouts to include only the boundary (pins and core rings). This check is done as part of the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__ tool.
-
-
-Hardening the User Project using OpenLane
-==========================================
-
-OpenLane Installation
----------------------
-
-You will need to install openlane by running the following
-
-.. code:: bash
-
- export OPENLANE_ROOT=<openlane-installation-path>
-
- # you can optionally specify the openlane tag to use
- # by running: export OPENLANE_TAG=<openlane-tag>
- # if you do not set the tag, it defaults to the last verfied tag tested for this project
-
- make openlane
-
-For detailed instructions on the openlane and the pdk installation refer
-to
-`README <https://github.com/The-OpenROAD-Project/OpenLane#setting-up-openlane>`__.
-
-Hardening Options
------------------
-
-There are three options for hardening the user project macro using
-openlane:
-
-+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-| Option 1 | Option 2 | Option 3 |
-+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-| Hardening the user macro(s) first, then inserting it in the | Flattening the user macro(s) with the | Placing multiple macros in the wrapper |
-| user project wrapper with no standard cells on the top level | user_project_wrapper | along with standard cells on the top level |
-+==============================================================+============================================+============================================+
-| |pic1| | |pic2| | |pic3| |
-| | | |
-+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-| ex: |link1| | | ex: |link2| |
-+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-
-.. |link1| replace:: `caravel_user_project <https://github.com/efabless/caravel_user_project>`__
-
-.. |link2| replace:: `caravel_ibex <https://github.com/efabless/caravel_ibex>`__
-
-
-.. |pic1| image:: ./_static/option1.png
- :width: 48%
-
-.. |pic2| image:: ./_static/option2.png
- :width: 140%
-
-.. |pic3| image:: ./_static/option3.png
- :width: 72%
-
-For more details on hardening macros using openlane, refer to `README <https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/hardening_macros.md>`__.
-
-
-Running OpenLane
------------------
-
-For this sample project, we went for the first option where the user
-macro is hardened first, then it is inserted in the user project
-wrapper without having any standard cells on the top level.
-
-.. raw:: html
-
- <p align="center">
- <img src="./_static/wrapper.png" width="30%" height="30%">
- </p>
-
-.. raw:: html
-
- </p>
-
-To reproduce hardening this project, run the following:
-
-.. code:: bash
-
- # Run openlane to harden user_proj_example
- make user_proj_example
- # Run openlane to harden user_project_wrapper
- make user_project_wrapper
-
-
-For more information on the openlane flow, check `README <https://github.com/The-OpenROAD-Project/OpenLane#readme>`__.
-
-Running MPW Precheck Locally
-=================================
-
-You can install the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__ by running
-
-.. code:: bash
-
- # By default, this install the precheck in your home directory
- # To change the installtion path, run "export PRECHECK_ROOT=<precheck installation path>"
- make precheck
-
-This will clone the precheck repo and pull the latest precheck docker image.
-
-
-Then, you can run the precheck by running
-Specify CARAVEL_ROOT before running any of the following,
-
-.. code:: bash
-
- # export CARAVEL_ROOT=$(pwd)/caravel
- export CARAVEL_ROOT=<path-to-caravel>
- make run-precheck
-
-This will run all the precheck checks on your project and will produce the logs under the ``checks`` directory.
-
-
-Other Miscellaneous Targets
-============================
-
-The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane's flow.
-
-Run ``make help`` to display available targets.
-
-Specify CARAVEL_ROOT before running any of the following,
-
-.. code:: bash
-
- # export CARAVEL_ROOT=$(pwd)/caravel
- export CARAVEL_ROOT=<path-to-caravel>
-
-Run lvs on the mag view,
-
-.. code:: bash
-
- make lvs-<macro_name>
-
-Run lvs on the gds,
-
-.. code:: bash
-
- make lvs-gds-<macro_name>
-
-Run lvs on the maglef,
-
-.. code:: bash
-
- make lvs-maglef-<macro_name>
-
-Run drc using magic,
-
-.. code:: bash
-
- make drc-<macro_name>
-
-Run antenna check using magic,
-
-.. code:: bash
-
- make antenna-<macro_name>
-
-Run XOR check,
-
-.. code:: bash
-
- make xor-wrapper
-
-
-Checklist for Open-MPW Submission
-=================================
-
-- ✔️ The project repo adheres to the same directory structure in this
- repo.
-- ✔️ The project repo contain info.yaml at the project root.
-- ✔️ Top level macro is named ``user_project_wrapper``.
-- ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
-- ✔️ The hardened Macros are LVS and DRC clean
-- ✔️ The project contains a gate-level netlist for ``user_project_wrapper`` at verilog/gl/user_project_wrapper.v
-- ✔️ The hardened ``user_project_wrapper`` adheres to the same pin
- order specified at
- `pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>`__
-- ✔️ The hardened ``user_project_wrapper`` adheres to the fixed wrapper configuration specified at `fixed_wrapper_cfgs <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>`__
-- ✔️ XOR check passes with zero total difference.
-- ✔️ Openlane summary reports are retained under ./signoff/
-- ✔️ The design passes the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__
-
-.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg
- :target: https://opensource.org/licenses/Apache-2.0
-.. |User CI| image:: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg
- :target: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml
-.. |Caravel Build| image:: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg
- :target: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml
+https://github.com/giraypultar/wrapped_keyvalue/
diff --git a/docs/source/_static/empty.png b/docs/source/_static/empty.png
deleted file mode 100644
index 4b7ae67..0000000
--- a/docs/source/_static/empty.png
+++ /dev/null
Binary files differ
diff --git a/docs/source/_static/layout.png b/docs/source/_static/layout.png
deleted file mode 100644
index 71ffad0..0000000
--- a/docs/source/_static/layout.png
+++ /dev/null
Binary files differ
diff --git a/docs/source/_static/option1.png b/docs/source/_static/option1.png
deleted file mode 100644
index a88350b..0000000
--- a/docs/source/_static/option1.png
+++ /dev/null
Binary files differ
diff --git a/docs/source/_static/option2.png b/docs/source/_static/option2.png
deleted file mode 100644
index 5c604d6..0000000
--- a/docs/source/_static/option2.png
+++ /dev/null
Binary files differ
diff --git a/docs/source/_static/option3.png b/docs/source/_static/option3.png
deleted file mode 100644
index 7e346b3..0000000
--- a/docs/source/_static/option3.png
+++ /dev/null
Binary files differ
diff --git a/docs/source/_static/pitch.png b/docs/source/_static/pitch.png
deleted file mode 100644
index 2efc7a9..0000000
--- a/docs/source/_static/pitch.png
+++ /dev/null
Binary files differ
diff --git a/docs/source/index.rst b/docs/source/index.rst
index 15a0a03..fa3f806 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -32,12 +32,10 @@
- `Repo Integration <#repo-integration>`__
- `Verilog Integration <#verilog-integration>`__
- - `Layout Integration <#layout-integration>`__
- `Running Full Chip Simulation <#running-full-chip-simulation>`__
-- `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__
-- `Hardening the User Project using
- Openlane <#hardening-the-user-project-using-openlane>`__
+- `Hardening the User Project Macro using
+ Openlane <#hardening-the-user-project-macro-using-openlane>`__
- `Checklist for Open-MPW
Submission <#checklist-for-open-mpw-submission>`__
@@ -103,7 +101,7 @@
Caravel files are kept separate from the user project by having caravel
as submodule. The submodule commit should point to the latest of
-caravel/caravel-lite master/main branch. The following files should have a symbolic
+caravel/caravel-lite master. The following files should have a symbolic
link to `caravel's <https://github.com/efabless/caravel.git>`__
corresponding files:
@@ -156,21 +154,6 @@
</p>
-
-Layout Integration
--------------------
-
-The caravel layout is pre-designed with an empty golden wrapper in the user space. You only need to provide us with a valid ``user_project_wrapper`` GDS file. And, as part of the tapeout process, your hardened ``user_project_wrapper`` will be inserted into a vanilla caravel layout to get the final layout shipped for fabrication.
-
-.. raw:: html
-
- <p align="center">
- <img src="./_static/layout.png" width="80%" height="80%">
- </p>
-
-To make sure that this integration process goes smoothly without having any DRC or LVS issues, your hardened ``user_project_wrapper`` must adhere to a number of requirements listed at `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__ .
-
-
Building the PDK
================
@@ -179,7 +162,7 @@
- Build the pdk natively.
Make sure you have `Magic VLSI Layout Tool <http://opencircuitdesign.com/magic/index.html>`__ installed on your machine before building the pdk.
-The pdk build is tested with magic version ``8.3.209``.
+The pdk build is tested with magic version `8.3.209`.
.. code:: bash
@@ -216,7 +199,7 @@
This will pull a docker image with the needed tools installed.
-Then, run the RTL simulation by
+Then, run the RTL and GL simulation by
.. code:: bash
@@ -224,69 +207,16 @@
export CARAVEL_ROOT=$(pwd)/caravel
# specify simulation mode: RTL/GL
export SIM=RTL
- # Run RTL simulation on IO ports testbench, make verify-io_ports
- make verify-<testbench-name>
+ # Run IO ports testbench, make verify-io_ports
+ make verify-<dv-pattern>
-Once you have the physical implementation done and you have the gate-level netlists ready, it is crucial to run full gate-level simulations to make sure that your design works as intended after running the physical implementation.
-
-Run the gate-level simulation by:
-
-.. code:: bash
-
- export PDK_ROOT=<pdk-installation-path>
- export CARAVEL_ROOT=$(pwd)/caravel
- # specify simulation mode: RTL/GL
- export SIM=GL
- # Run RTL simulation on IO ports testbench, make verify-io_ports
- make verify-<testbench-name>
-
-
-This sample project comes with four example testbenches to test the IO port connection, wishbone interface, and logic analyzer. The test-benches are under the
-`verilog/dv <https://github.com/efabless/caravel_user_project/tree/main/verilog/dv>`__ directory. For more information on setting up the
+The verilog test-benches are under this directory
+`verilog/dv <https://github.com/efabless/caravel_user_project/tree/main/verilog/dv>`__. For more information on setting up the
simulation environment and the available testbenches for this sample
project, refer to `README <https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/README.md>`__.
-
-User Project Wrapper Requirements
-=================================
-
-Your hardened ``user_project_wrapper`` must match the `golden user_project_wrapper <https://github.com/efabless/caravel/blob/master/gds/user_project_wrapper_empty.gds.gz>`__ in the following:
-
-- Area ``(2.920um x 3.520um)``
-- Top module name ``"user_project_wrapper"``
-- Pin Placement
-- Pin Sizes
-- Core Rings Width and Offset
-- PDN Vertical and Horizontal Straps Width
-
-
-.. raw:: html
-
- <p align="center">
- <img src="./_static/empty.png" width="40%" height="40%">
- </p>
-
-
-These fixed configurations are specified `here <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>`__ .
-
-However, you are allowed to change the following if you need to:
-
-- PDN Vertical and Horizontal Pitch & Offset
-
-.. raw:: html
-
- <p align="center">
- <img src="./_static/pitch.png" width="30%" height="30%">
- </p>
-
-To make sure that you adhere to these requirements, we run an exclusive-or (XOR) check between your hardened ``user_project_wrapper`` GDS and the golden wrapper GDS after processing both layouts to include only the boundary (pins and core rings). This check is done as part of the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__ tool.
-
-
-Hardening the User Project using OpenLane
-==========================================
-
-OpenLane Installation
----------------------
+Hardening the User Project Macro using Openlane
+===============================================
You will need to install openlane by running the following
@@ -302,45 +232,16 @@
For detailed instructions on the openlane and the pdk installation refer
to
-`README <https://github.com/The-OpenROAD-Project/OpenLane#setting-up-openlane>`__.
-
-Hardening Options
------------------
+`README <https://github.com/efabless/openlane/blob/master/README.md>`__.
There are three options for hardening the user project macro using
openlane:
-+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-| Option 1 | Option 2 | Option 3 |
-+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-| Hardening the user macro(s) first, then inserting it in the | Flattening the user macro(s) with the | Placing multiple macros in the wrapper |
-| user project wrapper with no standard cells on the top level | user_project_wrapper | along with standard cells on the top level |
-+==============================================================+============================================+============================================+
-| |pic1| | |pic2| | |pic3| |
-| | | |
-+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
-| ex: |link1| | | ex: |link2| |
-+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
+1. Hardening the user macro, then embedding it in the wrapper
+2. Flattening the user macro with the wrapper.
+3. Placing multiple macros in the wrapper along with standard cells on the top level.
-.. |link1| replace:: `caravel_user_project <https://github.com/efabless/caravel_user_project>`__
-
-.. |link2| replace:: `caravel_ibex <https://github.com/efabless/caravel_ibex>`__
-
-
-.. |pic1| image:: ./_static/option1.png
- :width: 48%
-
-.. |pic2| image:: ./_static/option2.png
- :width: 140%
-
-.. |pic3| image:: ./_static/option3.png
- :width: 72%
-
-For more details on hardening macros using openlane, refer to `README <https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/hardening_macros.md>`__.
-
-
-Running OpenLane
------------------
+For more details on hardening the user project macro using openlane, refer to `README <https://github.com/efabless/caravel/blob/master/openlane/README.rst>`__.
For this sample project, we went for the first option where the user
macro is hardened first, then it is inserted in the user project
@@ -349,13 +250,13 @@
.. raw:: html
<p align="center">
- <img src="./_static/wrapper.png" width="30%" height="30%">
+ <img src="./_static/wrapper.png" width="50%" height="50%">
</p>
.. raw:: html
</p>
-
+
To reproduce hardening this project, run the following:
.. code:: bash
@@ -366,12 +267,10 @@
make user_project_wrapper
-For more information on the openlane flow, check `README <https://github.com/The-OpenROAD-Project/OpenLane#readme>`__.
-
Running MPW Precheck Locally
=================================
-You can install the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__ by running
+You can install the precheck by running
.. code:: bash
@@ -454,7 +353,6 @@
- ✔️ Top level macro is named ``user_project_wrapper``.
- ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
- ✔️ The hardened Macros are LVS and DRC clean
-- ✔️ The project contains a gate-level netlist for ``user_project_wrapper`` at verilog/gl/user_project_wrapper.v
- ✔️ The hardened ``user_project_wrapper`` adheres to the same pin
order specified at
`pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>`__
diff --git a/gds/both.gds b/gds/both.gds
new file mode 100644
index 0000000..4f6869d
--- /dev/null
+++ b/gds/both.gds
Binary files differ
diff --git a/info.yaml b/info.yaml
new file mode 100644
index 0000000..7c24223
--- /dev/null
+++ b/info.yaml
@@ -0,0 +1,19 @@
+---
+project:
+ description: "A key value store for Google sponsored Open MPW shuttles for SKY130."
+ foundry: "SkyWater"
+ git_url: "https://github.com/giraypultar/keyvalue_caravel.git"
+ organization: "Efabless"
+ organization_url: "http://efabless.com"
+ owner: "Giray Pultar"
+ process: "SKY130"
+ project_name: "keyvalue"
+ project_id: "00000509"
+ tags:
+ - "Open MPW"
+ - "Test Harness"
+ category: "Test Harness"
+ top_level_netlist: "caravel/verilog/gl/caravel.v"
+ user_level_netlist: "verilog/gl/user_project_wrapper.v"
+ version: "1.00"
+ cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
deleted file mode 100644
index c3de8af..0000000
--- a/openlane/user_proj_example/config.json
+++ /dev/null
@@ -1,21 +0,0 @@
-{
- "PDK" : "sky130A",
- "STD_CELL_LIBRARY" : "sky130_fd_sc_hd",
- "CARAVEL_ROOT" : "../../caravel",
- "CLOCK_NET" : "counter.clk",
- "CLOCK_PERIOD" : "10",
- "CLOCK_PORT" : "wb_clk_i",
- "DESIGN_IS_CORE" : "0",
- "DESIGN_NAME" : "user_proj_example",
- "DIE_AREA" : "0 0 900 600",
- "DIODE_INSERTION_STRATEGY" : "4",
- "FP_PIN_ORDER_CFG" : "pin_order.cfg",
- "FP_SIZING" : "absolute",
- "GLB_RT_MAXLAYER" : "5",
- "GND_NETS" : "vssd1",
- "PL_BASIC_PLACEMENT" : "1",
- "PL_TARGET_DENSITY" : "0.05",
- "RUN_CVC" : "1",
- "VDD_NETS" : "vccd1",
- "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v"]
-}
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 94af8ba..2aa188c 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -13,9 +13,6 @@
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
-set ::env(PDK) "sky130A"
-set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
-
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_proj_example
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
deleted file mode 100644
index d83d5bb..0000000
--- a/openlane/user_project_wrapper/config.json
+++ /dev/null
@@ -1,58 +0,0 @@
-{
- "PDK" : "sky130A",
- "STD_CELL_LIBRARY" : "sky130_fd_sc_hd",
- "CARAVEL_ROOT" : "../../caravel",
- "CLOCK_NET" : "mprj.clk",
- "CLOCK_PERIOD" : "10",
- "CLOCK_PORT" : "user_clock2",
- "CLOCK_TREE_SYNTH" : "0",
- "DESIGN_NAME" : "user_project_wrapper",
- "DIE_AREA" : "0 0 2920 3520",
- "DIODE_INSERTION_STRATEGY" : "0",
- "EXTRA_GDS_FILES" : "../../gds/user_proj_example.gds",
- "EXTRA_LEFS" : "../../lef/user_proj_example.lef",
- "FILL_INSERTION" : "0",
- "FP_IO_HEXTEND" : "4.8",
- "FP_IO_HLENGTH" : "2.4",
- "FP_IO_HTHICKNESS_MULT" : "4",
- "FP_IO_VEXTEND" : "4.8",
- "FP_IO_VLENGTH" : "2.4",
- "FP_IO_VTHICKNESS_MULT" : "4",
- "FP_PDN_CHECK_NODES" : "0",
- "FP_PDN_CORE_RING" : "1",
- "FP_PDN_CORE_RING_HOFFSET" : "14",
- "FP_PDN_CORE_RING_HSPACING" : "1.7",
- "FP_PDN_CORE_RING_HWIDTH" : "3.1",
- "FP_PDN_CORE_RING_VOFFSET" : "14",
- "FP_PDN_CORE_RING_VSPACING" : "1.7",
- "FP_PDN_CORE_RING_VWIDTH" : "3.1",
- "FP_PDN_ENABLE_RAILS" : "0",
- "FP_PDN_HOFFSET" : "5",
- "FP_PDN_HPITCH" : "180",
- "FP_PDN_HSPACING" : "15.5",
- "FP_PDN_HWIDTH" : "3.1",
- "FP_PDN_MACRO_HOOKS" : "mprj vccd1 vssd1",
- "FP_PDN_VOFFSET" : "5",
- "FP_PDN_VPITCH" : "180",
- "FP_PDN_VSPACING" : "15.5",
- "FP_PDN_VWIDTH" : "3.1",
- "FP_PIN_ORDER_CFG" : "../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg",
- "FP_SIZING" : "absolute",
- "GLB_RT_MAXLAYER" : "5",
- "GND_NETS" : "vssd1 vssd2 vssa1 vssa2",
- "MACRO_PLACEMENT_CFG" : "macro.cfg",
- "MAGIC_ZEROIZE_ORIGIN" : "0",
- "PL_RANDOM_GLB_PLACEMENT" : "1",
- "PL_RESIZER_BUFFER_INPUT_PORTS" : "0",
- "PL_RESIZER_BUFFER_OUTPUT_PORTS" : "0",
- "PL_RESIZER_DESIGN_OPTIMIZATIONS" : "0",
- "PL_RESIZER_TIMING_OPTIMIZATIONS" : "0",
- "RUN_CVC" : "0",
- "SYNTH_TOP_LEVEL" : "1",
- "SYNTH_USE_PG_PINS_DEFINES" : "USE_POWER_PINS",
- "TAP_DECAP_INSERTION" : "0",
- "VDD_NETS" : "vccd1 vccd2 vdda1 vdda2",
- "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"],
- "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_proj_example.v"]
-}
-
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 2d0583e..3b762ee 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -16,9 +16,6 @@
# Base Configurations. Don't Touch
# section begin
-set ::env(PDK) "sky130A"
-set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
-
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
@@ -27,7 +24,7 @@
set script_dir [file dirname [file normalize [info script]]]
-set ::env(DESIGN_NAME) user_project_wrapper
+set ::env(DESIGN_NAME) both
#section end
# User Configurations
@@ -35,7 +32,9 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_wrapper.v"
+ $script_dir/../../verilog/rtl/src/both.v \
+ $script_dir/../../verilog/rtl/src/keyvalue_3.v \
+ $script_dir/../../verilog/rtl/src/keyvalue_4.v"
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
diff --git a/openlane/user_project_wrapper/config.tcl.orig b/openlane/user_project_wrapper/config.tcl.orig
new file mode 100755
index 0000000..c94b7a0
--- /dev/null
+++ b/openlane/user_project_wrapper/config.tcl.orig
@@ -0,0 +1,82 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Base Configurations. Don't Touch
+# section begin
+
+# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
+
+# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) user_project_wrapper
+#section end
+
+# User Configurations
+
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/user_project_wrapper.v"
+
+## Clock configurations
+set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_NET) "mprj.clk"
+
+set ::env(CLOCK_PERIOD) "10"
+
+## Internal Macros
+### Macro PDN Connections
+set ::env(FP_PDN_MACRO_HOOKS) "\
+ mprj vccd1 vssd1"
+
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+
+### Black-box verilog and views
+set ::env(VERILOG_FILES_BLACKBOX) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/user_proj_example.v"
+
+set ::env(EXTRA_LEFS) "\
+ $script_dir/../../lef/user_proj_example.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+ $script_dir/../../gds/user_proj_example.gds"
+
+set ::env(GLB_RT_MAXLAYER) 5
+
+# disable pdn check nodes becuase it hangs with multiple power domains.
+# any issue with pdn connections will be flagged with LVS so it is not a critical check.
+set ::env(FP_PDN_CHECK_NODES) 0
+
+# The following is because there are no std cells in the example wrapper project.
+set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+
+set ::env(FP_PDN_ENABLE_RAILS) 0
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(FILL_INSERTION) 0
+set ::env(TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
deleted file mode 120000
index 7293cef..0000000
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ /dev/null
@@ -1 +0,0 @@
-pin_order.cfg
\ No newline at end of file
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index 3a73b99..b0e4051 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -25,6 +25,11 @@
CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+## Management SoC Pointers
+MGMT_SOC_PATH ?= ../../../../caravel_pico
+MGMT_SOC_VERILOG_PATH = $(MGMT_SOC_PATH)/verilog
+MGMT_SOC_RTL_PATH = $(MGMT_SOC_PATH)/verilog/rtl
+
## User Project Pointers
UPRJ_VERILOG_PATH ?= ../../../verilog
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
@@ -50,12 +55,12 @@
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(MGMT_SOC_RTL_PATH) \
$< -o $@
else
iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) -I $(MGMT_SOC_VERILOG_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
index e4d0a2d..7d2c29a 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -31,19 +31,21 @@
// designed to read the project count through the
// logic analyzer probes.
// I/O 6 is configured for the UART Tx line
+
uint32_t testval;
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2
+ reg_hkspi_disable = 1; // Shut off the housekeeping SPI,
+ // so we can use the pins.
reg_mprj_datal = 0x00000000;
reg_mprj_datah = 0x00000000;
- reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;;
- reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;;
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
@@ -71,18 +73,13 @@
reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Set UART clock to 64 kbaud (enable before I/O configuration)
- reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUT_MONITORED;
/* Apply configuration */
reg_mprj_xfer = 1;
@@ -116,17 +113,24 @@
// Test ability to force data on channel 37
// NOTE: Only the low 6 bits of reg_mprj_datah are meaningful
- reg_mprj_datah = 0xffffffca;
+
+ reg_mprj_datah = 0x0f0f0fc0;
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datah = 0x0f0f0fca;
+ reg_mprj_datah = 0x0000000a;
+ reg_mprj_datah = 0x0f0f0fc0;
reg_mprj_datah = 0x00000000;
reg_mprj_datah = 0x0f0f0fc5;
- reg_mprj_datah = 0x00000000;
+ reg_mprj_datah = 0x00000005;
// Test ability to read back data generated by the user project
// on the "monitored" outputs. Read from the lower 16 bits and
// copy the value to the upper 16 bits.
testval = reg_mprj_datal;
- reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000;
+ reg_mprj_datal = (testval << 16);
+ testval = reg_mprj_datal;
+ reg_mprj_datal = (testval << 16);
// Flag end of the test
reg_mprj_datal = 0xAB510000;
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index 1409015..0ac0b42 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -28,17 +28,8 @@
reg RSTB;
reg CSB;
reg power1, power2;
- reg power3, power4;
-
- wire HIGH;
- wire LOW;
- wire TRI;
- assign HIGH = 1'b1;
- assign LOW = 1'b0;
- assign TRI = 1'bz;
wire gpio;
- wire uart_tx;
wire [37:0] mprj_io;
wire [15:0] checkbits;
wire [3:0] status;
@@ -46,8 +37,10 @@
// Signals Assignment
assign checkbits = mprj_io[31:16];
assign status = mprj_io[35:32];
- assign uart_tx = mprj_io[6];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // Force CSB high until simulation is underway
+ // Note: The CSB GPIO pin default needs to be set to a pull-up. . .
+ assign mprj_io[3] = CSB;
always #12.5 clock <= (clock === 1'b0);
@@ -74,23 +67,29 @@
$display("Monitor: mprj_stimulus test started");
wait(status == 4'ha);
wait(status == 4'h5);
- // Value 0009 reflects copying user-controlled outputs to memory and back
- // to management-controlled outputs.
- wait(checkbits == 16'h0009);
+
+ // Values reflect copying user-controlled outputs to memory and back
+ // to management-controlled outputs. Note that there is a slight
+ // discrepancy in timing when using gate level simulation; either
+ // of the specified values is okay.
+
+ wait(checkbits == 16'h0840 || checkbits == 16'h0841);
+ wait(checkbits == 16'h0a00 || checkbits == 16'h0a01);
+
wait(checkbits == 16'hAB51);
$display("Monitor: mprj_stimulus test Passed");
#10000;
$finish;
end
- // Reset Operation
+ // Reset Operation
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
+ CSB <= 1'b1;
#2000;
- RSTB <= 1'b1; // Release reset
- #170000;
- CSB = 1'b0; // CSB can be released
+ RSTB <= 1'b1; // Release reset
+ #200000;
+ CSB <= 1'bz; // Stop driving CSB
end
initial begin // Power-up sequence
@@ -148,10 +147,5 @@
.io3() // not used
);
- // Testbench UART
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
endmodule
`default_nettype wire
diff --git a/verilog/rtl/src b/verilog/rtl/src
new file mode 120000
index 0000000..a1cbd1f
--- /dev/null
+++ b/verilog/rtl/src
@@ -0,0 +1 @@
+wrapped_keyvalue/src
\ No newline at end of file
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index af0bcd6..319c613 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -21,10 +21,8 @@
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
`include "gl/user_project_wrapper.v"
- `include "gl/keyvalue_1.v"
- `include "gl/keyvalue_2.v"
+ `include "gl/both.lvs.powered.v"
`else
`include "user_project_wrapper.v"
- `include "wrapped_keyvalue/src/keyvalue_1.v"
- `include "wrapped_keyvalue/src/keyvalue_2.v"
+ `include "wrapped_keyvalue/src/both.v"
`endif
