README.md

# Caravel User Project

[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)

ICESOC is a Heterogeneous Multicore SoC, integrating a customised embedded FPGA fabric and two RISC-V cores dedecating for Cryptographical applications. 

   <p align="center">
   <img src="./docs/source/ICESOC.png" width="50%" height="50%">
   </p>