tree: b6773b9f9b507c6e0418e496e565d8bb09ad0a69 [path history] [tgz]
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. jobs/
  6. lef/
  7. mag/
  8. maglef/
  9. oas/
  10. openlane/
  11. signoff/
  12. spi/
  13. verilog/
  14. .gitignore
  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

ICESOC is a Heterogeneous Multicore SoC, integrating a customised embedded FPGA fabric and two RISC-V cores dedecating for Cryptographical applications.