| commit | d841699460698902e91d559b33f0fb34c3550914 | [log] [tgz] |
|---|---|---|
| author | Muhammed Çelik <celikmuhammed@outlook.com.tr> | Wed Dec 29 15:23:52 2021 +0300 |
| committer | Muhammed Çelik <celikmuhammed@outlook.com.tr> | Wed Dec 29 15:23:52 2021 +0300 |
| tree | 49c3ab491e4b08b70e7093e4a9e8ac7809c342eb | |
| parent | fecfe7ac86ed13399d037731abcca64051f99e6e [diff] |
encoder_schematic edited
Turbo Encoder is used for FEC encoding for linear modulation.
Encoder takes 2 bits of input (namely A and B) and generates 6 bits of output in the form (AB Y1W1 Y2W2)
First couple of parity bits (Y1W1) are generated from linearly ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.
The design involves two paths:
-Input Data is stored at dual channel rams.
-AGU's (Address Generator Unit) generate data indices for linearly ordered and interleaved data inputs.
-Pre Encoder unit identifies initial state of the encoder.
-Encoder Core produces outputs according to the state and the inputs.
-Reports are based on Xilinx Spartan-7 xc7s6ftgb196-1
‘N’ = input data block size in couple number ranging from 56 to 2396.
‘f’ = frequency in Mhz.
For 50 Mhz clock speed and N = 56, throughput equals 31.5 Mbps.
For 50 Mhz clock speed and N = 2396, throughput equals 33.3 Mbps.
TBA
TBA
TBA
In alphabetical order:
