Merge pull request #2 from muhammed-celik/main_
Main
diff --git a/README.md b/README.md
index 7bf02e5..18d65b5 100644
--- a/README.md
+++ b/README.md
@@ -13,21 +13,24 @@
Overview
========
+#### DVB-RCS2 Turbo Encoder
-The Turbo Encoder is used for FEC encoding for linear modulation.
+Turbo Encoder is used for FEC encoding for linear modulation.
Encoder takes 2 bits of input (namely A and B) and generates 6 bits of output in the form (AB Y1W1 Y2W2)
-First couple of parity bits (Y1W1) are generated from normal ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.
+First couple of parity bits (Y1W1) are generated from linearly ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.
-The design involves two paths one of which is used for interleaved input data.
+The design involves two paths:
+1) Linear order path
+2) Interleaved path
#### Top-Level Diagram
-Input Data is stored at dual channel rams.
--AGU (Address Generator Unit) generates data indices for interleaving.
+-AGU's (Address Generator Unit) generate data indices for linearly ordered and interleaved data inputs.
-Pre Encoder unit identifies initial state of the encoder.
@@ -49,9 +52,9 @@
'f' = frequency in Mhz.
-For 50 Mhz clock speed and N = 56, throughput equals 31.5 Mbps.
+For 50 Mhz clock speed and N = 56, throughput equals to 31.5 Mbps.
-For 50 Mhz clock speed and N = 2396, throughput equals 33.3 Mbps.
+For 50 Mhz clock speed and N = 2396, throughput equals to 33.3 Mbps.
Setup
========
diff --git a/docs/images/encoder_schematic.png b/docs/images/encoder_schematic.png
index 71a7722..a18021a 100644
--- a/docs/images/encoder_schematic.png
+++ b/docs/images/encoder_schematic.png
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