commit 70a2c0bf072c6163cb0a4448639b6e605e99e87b
author Muhammed Çelik <celikmuhammed@outlook.com.tr> Wed Dec 29 13:52:37 2021 +0300
committer Muhammed Çelik <celikmuhammed@outlook.com.tr> Wed Dec 29 13:52:37 2021 +0300
tree fe5d0756c211a4c8cd98a275b9d26aeb6d10eb7a
parent e2e302a79707fb085c8e3e9097487808f074f845

Update README.md

README.md

diff --git a/README.md b/README.md
index 5c3dd59..8885f12 100644
--- a/README.md
+++ b/README.md
@@ -20,7 +20,7 @@
 
 First couple of parity bits (Y1W1) are generated from normal ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.
 
-The design involves 2 paths one of which is used for interleaved input data.
+The design involves two paths one of which is used for interleaved input data.
 
 #### Top-Level Diagram
 ![alt text](docs/encoder_schematic.png)