commit	4b4bad91ff099b38a5f81ea3cfe6bdecd080847d	[log] [tgz]
author	Abdullah YILDIZ <abdullahyildiz@users.noreply.github.com>	Tue Dec 28 12:44:06 2021 +0300
committer	Abdullah YILDIZ <abdullahyildiz@users.noreply.github.com>	Tue Dec 28 12:44:06 2021 +0300
tree	6aa9c34532a84b33666c2c7993bf4c3e2addd3e2

Initial commit

.gitattributes[Added - diff]
.github/scripts/build/run-set-id.sh[Added - diff]
.github/scripts/build/run-ship.sh[Added - diff]
.github/scripts/build/run-xor.sh[Added - diff]
.github/scripts/dv/pdkBuild.sh[Added - diff]
.github/scripts/dv/run-dv-wrapper.sh[Added - diff]
.github/scripts/dv/run-dv.sh[Added - diff]
.github/scripts/precheck/precheckBuild.sh[Added - diff]
.github/scripts/precheck/run-precheck-drc.sh[Added - diff]
.github/scripts/precheck/run-precheck.sh[Added - diff]
.github/workflows/auto_update_submodule.yml[Added - diff]
.github/workflows/caravel_build.yml[Added - diff]
.github/workflows/user_project_ci.yml[Added - diff]
.gitignore[Added - diff]
.gitmodules[Added - diff]
LICENSE[Added - diff]
Makefile[Added - diff]
README.md[Added - diff]
def/user_proj_example.def[Added - diff]
def/user_project_wrapper.def[Added - diff]
docs/Makefile[Added - diff]
docs/environment.yml[Added - diff]
docs/requirements.txt[Added - diff]
docs/source/_static/counter_32.png[Added - diff]
docs/source/_static/wrapper.png[Added - diff]
docs/source/conf.py[Added - diff]
docs/source/index.rst[Added - diff]
gds/user_proj_example.gds[Added - diff]
gds/user_project_wrapper.gds[Added - diff]
info.yaml[Added - diff]
lef/user_proj_example.lef[Added - diff]
lef/user_project_wrapper.lef[Added - diff]
mag/user_proj_example.mag[Added - diff]
mag/user_project_wrapper.mag[Added - diff]
maglef/user_proj_example.mag[Added - diff]
maglef/user_project_wrapper.mag[Added - diff]
openlane/.gitignore[Added - diff]
openlane/Makefile[Added - diff]
openlane/user_proj_example/config.tcl[Added - diff]
openlane/user_proj_example/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[Added - diff]
signoff/user_proj_example/PDK_SOURCES[Added - diff]
signoff/user_proj_example/final_summary_report.csv[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[Added - diff]
signoff/user_project_wrapper/final_summary_report.csv[Added - diff]
spi/lvs/user_proj_example.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/io_ports/Makefile[Added - diff]
verilog/dv/io_ports/io_ports.c[Added - diff]
verilog/dv/io_ports/io_ports_tb.v[Added - diff]
verilog/dv/la_test1/Makefile[Added - diff]
verilog/dv/la_test1/la_test1.c[Added - diff]
verilog/dv/la_test1/la_test1_tb.v[Added - diff]
verilog/dv/la_test2/Makefile[Added - diff]
verilog/dv/la_test2/la_test2.c[Added - diff]
verilog/dv/la_test2/la_test2_tb.v[Added - diff]
verilog/dv/mprj_stimulus/Makefile[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Added - diff]
verilog/dv/wb_port/Makefile[Added - diff]
verilog/dv/wb_port/wb_port.c[Added - diff]
verilog/dv/wb_port/wb_port_tb.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
verilog/gl/user_project_wrapper.v[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/user_proj_example.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]

73 files changed

tree: 6aa9c34532a84b33666c2c7993bf4c3e2addd3e2

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.