| commit | 8a21e395af90c1d6e721d07e7b661e9336ed39fd | [log] [tgz] |
|---|---|---|
| author | Muhammed Çelik <celikmuhammed@outlook.com.tr> | Wed Dec 29 14:02:23 2021 +0300 |
| committer | Muhammed Çelik <celikmuhammed@outlook.com.tr> | Wed Dec 29 14:02:23 2021 +0300 |
| tree | 7e1bfd073f5eca6ed04293140b2bef0d086bb180 | |
| parent | 70a2c0bf072c6163cb0a4448639b6e605e99e87b [diff] |
Update encoder_schematic.png
The Turbo Encoder is used for FEC encoding for linear modulation.
Encoder takes 2 bits of input (namely A and B) and generates 6 bits of output in the form (AB Y1W1 Y2W2)
First couple of parity bits (Y1W1) are generated from normal ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.
The design involves two paths one of which is used for interleaved input data.
-Input Data is stored at dual channel rams.
-AGU (Address Generator Unit) generates data indices for interleaving.
-Pre Encoder unit identifies initial state of the encoder.
-Encoder Core produces outputs according to the state and the inputs.
-Reports are based on Xilinx Spartan-7 xc7s6ftgb196-1
‘N’ = input data block size in couple number ranging from 56 to 2396.
‘f’ = frequency in Mhz.
For 50 Mhz clock speed and N = 56, throughput equals 31.5 Mbps.
For 50 Mhz clock speed and N = 2396, throughput equals 33.3 Mbps.
TBA
TBA
TBA
In alphabetical order:
