commit: 6cc06b23e5ddb70abd4c1cdcf993b64f7735357b
[log] [tgz]
author: Ganesh Gore <goreganesh007@gmail.com>
Tue Dec 14 04:09:02 2021 -0700
committer: Ganesh Gore <goreganesh007@gmail.com>
Tue Dec 14 04:09:02 2021 -0700
tree: f5a8c914985da1ab7e8d9ae26339634ab2f5343d
parent: 0c2d157e51d56a5975368860b7dab3db2c78d1f2 [diff]

added SPICE netlist

.github/scripts/precheck/precheckBuild.sh[diff]
.gitignore[diff]
info.yaml[diff]
netgen/comp.out[Added - diff]
netgen/example_por.spice[Added - diff]
netgen/run_lvs_por.sh[Added - diff]
netgen/run_lvs_wrapper_verilog.sh[Added - diff]
netgen/run_lvs_wrapper_xschem.sh[Added - diff]
netgen/user_analog_project_wrapper.spice[Added - diff]

9 files changed

tree: f5a8c914985da1ab7e8d9ae26339634ab2f5343d

README.md

RRAM_4T1R

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.