Adding third party wb components
diff --git a/ip/third_party/picorv32_wb/gpio32_wb.v b/ip/third_party/picorv32_wb/gpio32_wb.v
new file mode 100644
index 0000000..735758f
--- /dev/null
+++ b/ip/third_party/picorv32_wb/gpio32_wb.v
@@ -0,0 +1,134 @@
+// Simple 32-bit GPIO peripheral.
+//
+// Derived from gpio_wb.v from Caravel.
+
+`default_nettype none
+module gpio32_wb # (
+ parameter GPIO_DATA = 8'h 00,
+ parameter GPIO_ENA = 8'h 04,
+ parameter GPIO_PU = 8'h 08,
+ parameter GPIO_PD = 8'h 0c
+) (
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input [31:0] wb_dat_i,
+ input [31:0] wb_adr_i,
+ input [3:0] wb_sel_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+ input wb_we_i,
+
+ output [31:0] wb_dat_o,
+ output wb_ack_o,
+
+ input [31:0] gpio_in,
+ output [31:0] gpio_out,
+ output [31:0] gpio_oeb
+);
+
+ wire resetn;
+ wire valid;
+ wire ready;
+ wire [3:0] iomem_we;
+
+ assign resetn = ~wb_rst_i;
+ assign valid = wb_stb_i && wb_cyc_i;
+
+ assign iomem_we = wb_sel_i & {4{wb_we_i}};
+ assign wb_ack_o = ready;
+
+ gpio32 #(
+ .GPIO_DATA(GPIO_DATA),
+ .GPIO_ENA(GPIO_ENA),
+ .GPIO_PD(GPIO_PD),
+ .GPIO_PU(GPIO_PU)
+ ) gpio_ctrl (
+ .clk(wb_clk_i),
+ .resetn(resetn),
+
+ .iomem_addr(wb_adr_i),
+ .iomem_valid(valid),
+ .iomem_wstrb(iomem_we[0]),
+ .iomem_wdata(wb_dat_i),
+ .iomem_rdata(wb_dat_o),
+ .iomem_ready(ready),
+
+ .gpio_in(gpio_in),
+ .gpio_out(gpio_out),
+ .gpio_oeb(gpio_oeb)
+ );
+
+endmodule
+
+module gpio32 #(
+ parameter GPIO_DATA = 8'h 00,
+ parameter GPIO_ENA = 8'h 04,
+ parameter GPIO_PU = 8'h 08,
+ parameter GPIO_PD = 8'h 0c
+) (
+ input clk,
+ input resetn,
+
+ input gpio_in_pad,
+
+ input [31:0] iomem_addr,
+ input iomem_valid,
+ input iomem_wstrb,
+ input [31:0] iomem_wdata,
+ output reg [31:0] iomem_rdata,
+ output reg iomem_ready,
+
+ input [31:0] gpio_in,
+ output [31:0] gpio_out,
+ output [31:0] gpio_oeb
+);
+
+ reg [31:0] gpio_out; // GPIO output data
+ reg [31:0] gpio_pu; // GPIO pull-up enable
+ reg [31:0] gpio_pd; // GPIO pull-down enable
+ reg [31:0] gpio_oeb; // GPIO output enable (sense negative)
+
+ wire gpio_sel;
+ wire gpio_oeb_sel;
+ wire gpio_pu_sel;
+ wire gpio_pd_sel;
+
+ assign gpio_sel = (iomem_addr[7:0] == GPIO_DATA);
+ assign gpio_oeb_sel = (iomem_addr[7:0] == GPIO_ENA);
+ assign gpio_pu_sel = (iomem_addr[7:0] == GPIO_PU);
+ assign gpio_pd_sel = (iomem_addr[7:0] == GPIO_PD);
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ gpio_out <= 32'h0;
+ gpio_oeb <= 32'hffff_ffff;
+ end else begin
+ iomem_ready <= 0;
+ if (iomem_valid && !iomem_ready) begin
+ iomem_ready <= 1'b 1;
+
+ if (gpio_sel) begin
+ iomem_rdata <= gpio_in;
+ if (iomem_wstrb) gpio_out <= iomem_wdata;
+
+ end else if (gpio_oeb_sel) begin
+ iomem_rdata <= ~gpio_oeb;
+ if (iomem_wstrb) gpio_oeb <= ~iomem_wdata;
+
+ end else if (gpio_pu_sel) begin
+ iomem_rdata <= gpio_pu;
+ if (iomem_wstrb) gpio_pu <= iomem_wdata;
+
+ end else if (gpio_pd_sel) begin
+ iomem_rdata <= gpio_pd;
+ if (iomem_wstrb) gpio_pd <= iomem_wdata;
+
+ end
+
+ end
+ end
+ end
+
+endmodule
+`default_nettype wire
diff --git a/ip/third_party/picorv32_wb/gpio_wb.v b/ip/third_party/picorv32_wb/gpio_wb.v
new file mode 100644
index 0000000..70bf65e
--- /dev/null
+++ b/ip/third_party/picorv32_wb/gpio_wb.v
@@ -0,0 +1,141 @@
+`default_nettype none
+module gpio_wb # (
+ parameter BASE_ADR = 32'h 2100_0000,
+ parameter GPIO_DATA = 8'h 00,
+ parameter GPIO_ENA = 8'h 04,
+ parameter GPIO_PU = 8'h 08,
+ parameter GPIO_PD = 8'h 0c
+) (
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input [31:0] wb_dat_i,
+ input [31:0] wb_adr_i,
+ input [3:0] wb_sel_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+ input wb_we_i,
+
+ output [31:0] wb_dat_o,
+ output wb_ack_o,
+
+ input gpio_in_pad,
+ output gpio,
+ output gpio_oeb,
+ output gpio_pu,
+ output gpio_pd
+);
+
+ wire resetn;
+ wire valid;
+ wire ready;
+ wire [3:0] iomem_we;
+
+ assign resetn = ~wb_rst_i;
+ assign valid = wb_stb_i && wb_cyc_i;
+
+ assign iomem_we = wb_sel_i & {4{wb_we_i}};
+ assign wb_ack_o = ready;
+
+ gpio #(
+ .BASE_ADR(BASE_ADR),
+ .GPIO_DATA(GPIO_DATA),
+ .GPIO_ENA(GPIO_ENA),
+ .GPIO_PD(GPIO_PD),
+ .GPIO_PU(GPIO_PU)
+ ) gpio_ctrl (
+ .clk(wb_clk_i),
+ .resetn(resetn),
+
+ .gpio_in_pad(gpio_in_pad),
+
+ .iomem_addr(wb_adr_i),
+ .iomem_valid(valid),
+ .iomem_wstrb(iomem_we[0]),
+ .iomem_wdata(wb_dat_i),
+ .iomem_rdata(wb_dat_o),
+ .iomem_ready(ready),
+
+ .gpio(gpio),
+ .gpio_oeb(gpio_oeb),
+ .gpio_pu(gpio_pu),
+ .gpio_pd(gpio_pd)
+ );
+
+endmodule
+
+module gpio #(
+ parameter BASE_ADR = 32'h 2100_0000,
+ parameter GPIO_DATA = 8'h 00,
+ parameter GPIO_ENA = 8'h 04,
+ parameter GPIO_PU = 8'h 08,
+ parameter GPIO_PD = 8'h 0c
+) (
+ input clk,
+ input resetn,
+
+ input gpio_in_pad,
+
+ input [31:0] iomem_addr,
+ input iomem_valid,
+ input iomem_wstrb,
+ input [31:0] iomem_wdata,
+ output reg [31:0] iomem_rdata,
+ output reg iomem_ready,
+
+ output gpio,
+ output gpio_oeb,
+ output gpio_pu,
+ output gpio_pd
+);
+
+ reg gpio; // GPIO output data
+ reg gpio_pu; // GPIO pull-up enable
+ reg gpio_pd; // GPIO pull-down enable
+ reg gpio_oeb; // GPIO output enable (sense negative)
+
+ wire gpio_sel;
+ wire gpio_oeb_sel;
+ wire gpio_pu_sel;
+ wire gpio_pd_sel;
+
+ assign gpio_sel = (iomem_addr[7:0] == GPIO_DATA);
+ assign gpio_oeb_sel = (iomem_addr[7:0] == GPIO_ENA);
+ assign gpio_pu_sel = (iomem_addr[7:0] == GPIO_PU);
+ assign gpio_pd_sel = (iomem_addr[7:0] == GPIO_PD);
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ gpio <= 0;
+ gpio_oeb <= 16'hffff;
+ gpio_pu <= 0;
+ gpio_pd <= 0;
+ end else begin
+ iomem_ready <= 0;
+ if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
+ iomem_ready <= 1'b 1;
+
+ if (gpio_sel) begin
+ iomem_rdata <= {30'd0, gpio, gpio_in_pad};
+ if (iomem_wstrb) gpio <= iomem_wdata[0];
+
+ end else if (gpio_oeb_sel) begin
+ iomem_rdata <= {31'd0, gpio_oeb};
+ if (iomem_wstrb) gpio_oeb <= iomem_wdata[0];
+
+ end else if (gpio_pu_sel) begin
+ iomem_rdata <= {31'd0, gpio_pu};
+ if (iomem_wstrb) gpio_pu <= iomem_wdata[0];
+
+ end else if (gpio_pd_sel) begin
+ iomem_rdata <= {31'd0, gpio_pd};
+ if (iomem_wstrb) gpio_pd <= iomem_wdata[0];
+
+ end
+
+ end
+ end
+ end
+
+endmodule
+`default_nettype wire
diff --git a/ip/third_party/picorv32_wb/la_wb.v b/ip/third_party/picorv32_wb/la_wb.v
new file mode 100644
index 0000000..07dfc90
--- /dev/null
+++ b/ip/third_party/picorv32_wb/la_wb.v
@@ -0,0 +1,206 @@
+`default_nettype none
+module la_wb # (
+ parameter BASE_ADR = 32'h 2200_0000,
+ parameter LA_DATA_0 = 8'h00,
+ parameter LA_DATA_1 = 8'h04,
+ parameter LA_DATA_2 = 8'h08,
+ parameter LA_DATA_3 = 8'h0c,
+ parameter LA_ENA_0 = 8'h10,
+ parameter LA_ENA_1 = 8'h14,
+ parameter LA_ENA_2 = 8'h18,
+ parameter LA_ENA_3 = 8'h1c
+) (
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input [31:0] wb_dat_i,
+ input [31:0] wb_adr_i,
+ input [3:0] wb_sel_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+ input wb_we_i,
+
+ output [31:0] wb_dat_o,
+ output wb_ack_o,
+
+ input [127:0] la_data_in, // From MPRJ
+ output [127:0] la_data,
+ output [127:0] la_oen
+);
+
+ wire resetn;
+ wire valid;
+ wire ready;
+ wire [3:0] iomem_we;
+
+ assign resetn = ~wb_rst_i;
+ assign valid = wb_stb_i && wb_cyc_i;
+
+ assign iomem_we = wb_sel_i & {4{wb_we_i}};
+ assign wb_ack_o = ready;
+
+ la #(
+ .BASE_ADR(BASE_ADR),
+ .LA_DATA_0(LA_DATA_0),
+ .LA_DATA_1(LA_DATA_1),
+ .LA_DATA_2(LA_DATA_2),
+ .LA_DATA_3(LA_DATA_3),
+ .LA_ENA_0(LA_ENA_0),
+ .LA_ENA_1(LA_ENA_1),
+ .LA_ENA_2(LA_ENA_2),
+ .LA_ENA_3(LA_ENA_3)
+ ) la_ctrl (
+ .clk(wb_clk_i),
+ .resetn(resetn),
+ .iomem_addr(wb_adr_i),
+ .iomem_valid(valid),
+ .iomem_wstrb(iomem_we),
+ .iomem_wdata(wb_dat_i),
+ .iomem_rdata(wb_dat_o),
+ .iomem_ready(ready),
+ .la_data_in(la_data_in),
+ .la_data(la_data),
+ .la_oen(la_oen)
+ );
+
+endmodule
+
+module la #(
+ parameter BASE_ADR = 32'h 2200_0000,
+ parameter LA_DATA_0 = 8'h00,
+ parameter LA_DATA_1 = 8'h04,
+ parameter LA_DATA_2 = 8'h08,
+ parameter LA_DATA_3 = 8'h0c,
+ parameter LA_ENA_0 = 8'h10,
+ parameter LA_ENA_1 = 8'h14,
+ parameter LA_ENA_2 = 8'h18,
+ parameter LA_ENA_3 = 8'h1c
+) (
+ input clk,
+ input resetn,
+
+ input [31:0] iomem_addr,
+ input iomem_valid,
+ input [3:0] iomem_wstrb,
+ input [31:0] iomem_wdata,
+
+ output reg [31:0] iomem_rdata,
+ output reg iomem_ready,
+
+ input [127:0] la_data_in, // From MPRJ
+ output [127:0] la_data, // To MPRJ
+ output [127:0] la_oen
+);
+
+ reg [31:0] la_data_0;
+ reg [31:0] la_data_1;
+ reg [31:0] la_data_2;
+ reg [31:0] la_data_3;
+
+ reg [31:0] la_ena_0;
+ reg [31:0] la_ena_1;
+ reg [31:0] la_ena_2;
+ reg [31:0] la_ena_3;
+
+ wire [3:0] la_data_sel;
+ wire [3:0] la_ena_sel;
+
+ assign la_data = {la_data_3, la_data_2, la_data_1, la_data_0};
+ assign la_oen = {la_ena_3, la_ena_2, la_ena_1, la_ena_0};
+
+ assign la_data_sel = {
+ (iomem_addr[7:0] == LA_DATA_3),
+ (iomem_addr[7:0] == LA_DATA_2),
+ (iomem_addr[7:0] == LA_DATA_1),
+ (iomem_addr[7:0] == LA_DATA_0)
+ };
+
+ assign la_ena_sel = {
+ (iomem_addr[7:0] == LA_ENA_3),
+ (iomem_addr[7:0] == LA_ENA_2),
+ (iomem_addr[7:0] == LA_ENA_1),
+ (iomem_addr[7:0] == LA_ENA_0)
+ };
+
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ la_data_0 <= 0;
+ la_data_1 <= 0;
+ la_data_2 <= 0;
+ la_data_3 <= 0;
+ la_ena_0 <= 32'hFFFF_FFFF; // default is tri-state buff disabled
+ la_ena_1 <= 32'hFFFF_FFFF;
+ la_ena_2 <= 32'hFFFF_FFFF;
+ la_ena_3 <= 32'hFFFF_FFFF;
+ end else begin
+ iomem_ready <= 0;
+ if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
+ iomem_ready <= 1'b 1;
+
+ if (la_data_sel[0]) begin
+ iomem_rdata <= la_data_0 | (la_data_in[31:0] & la_ena_0);
+
+ if (iomem_wstrb[0]) la_data_0[ 7: 0] <= iomem_wdata[ 7: 0];
+ if (iomem_wstrb[1]) la_data_0[15: 8] <= iomem_wdata[15: 8];
+ if (iomem_wstrb[2]) la_data_0[23:16] <= iomem_wdata[23:16];
+ if (iomem_wstrb[3]) la_data_0[31:24] <= iomem_wdata[31:24];
+
+ end else if (la_data_sel[1]) begin
+ iomem_rdata <= la_data_1 | (la_data_in[63:32] & la_ena_1);
+
+ if (iomem_wstrb[0]) la_data_1[ 7: 0] <= iomem_wdata[ 7: 0];
+ if (iomem_wstrb[1]) la_data_1[15: 8] <= iomem_wdata[15: 8];
+ if (iomem_wstrb[2]) la_data_1[23:16] <= iomem_wdata[23:16];
+ if (iomem_wstrb[3]) la_data_1[31:24] <= iomem_wdata[31:24];
+
+ end else if (la_data_sel[2]) begin
+ iomem_rdata <= la_data_2 | (la_data_in[95:64] & la_ena_2);
+
+ if (iomem_wstrb[0]) la_data_2[ 7: 0] <= iomem_wdata[ 7: 0];
+ if (iomem_wstrb[1]) la_data_2[15: 8] <= iomem_wdata[15: 8];
+ if (iomem_wstrb[2]) la_data_2[23:16] <= iomem_wdata[23:16];
+ if (iomem_wstrb[3]) la_data_2[31:24] <= iomem_wdata[31:24];
+
+ end else if (la_data_sel[3]) begin
+ iomem_rdata <= la_data_3 | (la_data_in[127:96] & la_ena_3);
+
+ if (iomem_wstrb[0]) la_data_3[ 7: 0] <= iomem_wdata[ 7: 0];
+ if (iomem_wstrb[1]) la_data_3[15: 8] <= iomem_wdata[15: 8];
+ if (iomem_wstrb[2]) la_data_3[23:16] <= iomem_wdata[23:16];
+ if (iomem_wstrb[3]) la_data_3[31:24] <= iomem_wdata[31:24];
+ end else if (la_ena_sel[0]) begin
+ iomem_rdata <= la_ena_0;
+
+ if (iomem_wstrb[0]) la_ena_0[ 7: 0] <= iomem_wdata[ 7: 0];
+ if (iomem_wstrb[1]) la_ena_0[15: 8] <= iomem_wdata[15: 8];
+ if (iomem_wstrb[2]) la_ena_0[23:16] <= iomem_wdata[23:16];
+ if (iomem_wstrb[3]) la_ena_0[31:24] <= iomem_wdata[31:24];
+ end else if (la_ena_sel[1]) begin
+ iomem_rdata <= la_ena_1;
+
+ if (iomem_wstrb[0]) la_ena_1[ 7: 0] <= iomem_wdata[ 7: 0];
+ if (iomem_wstrb[1]) la_ena_1[15: 8] <= iomem_wdata[15: 8];
+ if (iomem_wstrb[2]) la_ena_1[23:16] <= iomem_wdata[23:16];
+ if (iomem_wstrb[3]) la_ena_1[31:24] <= iomem_wdata[31:24];
+ end else if (la_ena_sel[2]) begin
+ iomem_rdata <= la_ena_2;
+
+ if (iomem_wstrb[0]) la_ena_2[ 7: 0] <= iomem_wdata[ 7: 0];
+ if (iomem_wstrb[1]) la_ena_2[15: 8] <= iomem_wdata[15: 8];
+ if (iomem_wstrb[2]) la_ena_2[23:16] <= iomem_wdata[23:16];
+ if (iomem_wstrb[3]) la_ena_2[31:24] <= iomem_wdata[31:24];
+ end else if (la_ena_sel[3]) begin
+ iomem_rdata <= la_ena_3;
+
+ if (iomem_wstrb[0]) la_ena_3[ 7: 0] <= iomem_wdata[ 7: 0];
+ if (iomem_wstrb[1]) la_ena_3[15: 8] <= iomem_wdata[15: 8];
+ if (iomem_wstrb[2]) la_ena_3[23:16] <= iomem_wdata[23:16];
+ if (iomem_wstrb[3]) la_ena_3[31:24] <= iomem_wdata[31:24];
+ end
+ end
+ end
+ end
+
+endmodule
+`default_nettype wire
diff --git a/ip/third_party/picorv32_wb/mem_ff_wb.v b/ip/third_party/picorv32_wb/mem_ff_wb.v
new file mode 100644
index 0000000..250dc8e
--- /dev/null
+++ b/ip/third_party/picorv32_wb/mem_ff_wb.v
@@ -0,0 +1,122 @@
+// Inferred RAM to work around limitations in Openlane.
+//
+// Wishbone interface based on mem_wb.v from Caravel.
+
+`default_nettype none
+module mem_ff_wb #(
+ parameter MEM_WORDS = 256
+)(
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input [31:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ input [3:0] wb_sel_i,
+ input wb_we_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+
+ output wb_ack_o,
+ output [31:0] wb_dat_o
+);
+
+ localparam ADR_WIDTH = $clog2(MEM_WORDS);
+
+ wire valid;
+ wire ram_wen;
+ wire [3:0] wen; // write enable
+
+ assign valid = wb_cyc_i & wb_stb_i;
+ assign ram_wen = wb_we_i && valid;
+
+ assign wen = wb_sel_i & {4{ram_wen}} ;
+
+ /*
+ Ack Generation
+ - write transaction: asserted upon receiving adr_i & dat_i
+ - read transaction : asserted one clock cycle after receiving the adr_i & dat_i
+ */
+
+ reg wb_ack_read;
+ reg wb_ack_o;
+
+ always @(posedge wb_clk_i) begin
+ if (wb_rst_i == 1'b 1) begin
+ wb_ack_read <= 1'b0;
+ wb_ack_o <= 1'b0;
+ end else begin
+ // wb_ack_read <= {2{valid}} & {1'b1, wb_ack_read[1]};
+ wb_ack_o <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
+ wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
+ end
+ end
+
+ ff32_ram #(
+ .ADDR_WIDTH(ADR_WIDTH)
+ ) ram (
+ .clk(wb_clk_i),
+
+ .addr(wb_adr_i[ADR_WIDTH+1:2]),
+ .din(wb_dat_i),
+ .dout(wb_dat_o),
+
+ .en(valid),
+ .wmask(wen)
+ );
+endmodule
+`default_nettype wire
+
+// Single port 32-bit inferred RAM.
+module ff32_ram #(
+ parameter ADDR_WIDTH = 8
+)(
+ input clk,
+
+ input [ADDR_WIDTH-1:0] addr,
+ input [31:0] din,
+ output reg [31:0] dout,
+
+ input en,
+ input [3:0] wmask
+);
+ reg [7:0] ram0 [(1<<ADDR_WIDTH)-1:0];
+ reg [7:0] ram1 [(1<<ADDR_WIDTH)-1:0];
+ reg [7:0] ram2 [(1<<ADDR_WIDTH)-1:0];
+ reg [7:0] ram3 [(1<<ADDR_WIDTH)-1:0];
+
+`ifdef SIM
+ integer i;
+ initial begin
+ for (i = 0; i < (1<<ADDR_WIDTH); i = i + 1) begin
+ ram0[i] = 8'b0;
+ ram1[i] = 8'b0;
+ ram2[i] = 8'b0;
+ ram3[i] = 8'b0;
+ end
+ end
+`endif
+
+ // Write.
+ always @(posedge clk) begin
+ if (en) begin
+ if (wmask[0])
+ ram0[addr] <= din[7:0];
+ if (wmask[1])
+ ram1[addr] <= din[15:8];
+ if (wmask[2])
+ ram2[addr] <= din[23:16];
+ if (wmask[3])
+ ram3[addr] <= din[31:24];
+ end
+ end
+
+ // Read.
+ always @(posedge clk) begin
+ if (en) begin
+ dout[7:0] <= ram0[addr];
+ dout[15:8] <= ram1[addr];
+ dout[23:16] <= ram2[addr];
+ dout[31:24] <= ram3[addr];
+ end
+ end
+endmodule // module ff32_ram
diff --git a/ip/third_party/picorv32_wb/mem_wb.v b/ip/third_party/picorv32_wb/mem_wb.v
new file mode 100644
index 0000000..06fb2f0
--- /dev/null
+++ b/ip/third_party/picorv32_wb/mem_wb.v
@@ -0,0 +1,126 @@
+`default_nettype none
+module mem_wb (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input [31:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ input [3:0] wb_sel_i,
+ input wb_we_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+
+ output wb_ack_o,
+ output [31:0] wb_dat_o
+
+);
+
+ localparam ADR_WIDTH = $clog2(`MEM_WORDS);
+
+ wire valid;
+ wire ram_wen;
+ wire [3:0] wen; // write enable
+
+ assign valid = wb_cyc_i & wb_stb_i;
+ assign ram_wen = wb_we_i && valid;
+
+ assign wen = wb_sel_i & {4{ram_wen}} ;
+
+ /*
+ Ack Generation
+ - write transaction: asserted upon receiving adr_i & dat_i
+ - read transaction : asserted one clock cycle after receiving the adr_i & dat_i
+ */
+
+ reg wb_ack_read;
+ reg wb_ack_o;
+
+ always @(posedge wb_clk_i) begin
+ if (wb_rst_i == 1'b 1) begin
+ wb_ack_read <= 1'b0;
+ wb_ack_o <= 1'b0;
+ end else begin
+ // wb_ack_read <= {2{valid}} & {1'b1, wb_ack_read[1]};
+ wb_ack_o <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
+ wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
+ end
+ end
+
+ soc_mem
+`ifndef USE_OPENRAM
+ #(
+ .WORDS(`MEM_WORDS),
+ .ADR_WIDTH(ADR_WIDTH)
+ )
+`endif
+ mem (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .clk(wb_clk_i),
+ .ena(valid),
+ .wen(wen),
+ .addr(wb_adr_i[ADR_WIDTH+1:2]),
+ .wdata(wb_dat_i),
+ .rdata(wb_dat_o)
+ );
+
+endmodule
+
+module soc_mem
+#(
+`ifndef USE_OPENRAM
+ parameter integer WORDS = 256,
+`endif
+ parameter ADR_WIDTH = 8
+)
+ (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input clk,
+ input ena,
+ input [3:0] wen,
+ input [ADR_WIDTH-1:0] addr,
+ input [31:0] wdata,
+ output[31:0] rdata
+);
+
+`ifndef USE_OPENRAM
+ DFFRAM #(.COLS(`COLS)) SRAM (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(clk),
+ .WE(wen),
+ .EN(ena),
+ .Di(wdata),
+ .Do(rdata),
+ // 8-bit address if using the default custom DFF RAM
+ .A(addr)
+ );
+`else
+
+ /* Using Port 0 Only - Size: 1KB, 256x32 bits */
+ //sram_1rw1r_32_256_8_scn4m_subm
+ sram_1rw1r_32_256_8_sky130 SRAM(
+ .clk0(clk),
+ .csb0(~ena),
+ .web0(~|wen),
+ .wmask0(wen),
+ .addr0(addr[7:0]),
+ .din0(wdata),
+ .dout0(rdata)
+ );
+
+`endif
+
+endmodule
+`default_nettype wire
diff --git a/ip/third_party/picorv32_wb/picorv32.v b/ip/third_party/picorv32_wb/picorv32.v
new file mode 100644
index 0000000..17969b5
--- /dev/null
+++ b/ip/third_party/picorv32_wb/picorv32.v
@@ -0,0 +1,3046 @@
+`default_nettype none
+/*
+ * PicoRV32 -- A Small RISC-V (RV32I) Processor Core
+ *
+ * Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+/* verilator lint_off WIDTH */
+/* verilator lint_off PINMISSING */
+/* verilator lint_off CASEOVERLAP */
+/* verilator lint_off CASEINCOMPLETE */
+
+`timescale 1 ns / 1 ps
+// `define DEBUGNETS
+// `define DEBUGREGS
+// `define DEBUGASM
+// `define DEBUG
+
+`ifdef DEBUG
+ `define debug(debug_command) debug_command
+`else
+ `define debug(debug_command)
+`endif
+
+`ifdef FORMAL
+ `define FORMAL_KEEP (* keep *)
+ `define assert(assert_expr) assert(assert_expr)
+`else
+ `ifdef DEBUGNETS
+ `define FORMAL_KEEP (* keep *)
+ `else
+ `define FORMAL_KEEP
+ `endif
+ `define assert(assert_expr) empty_statement
+`endif
+
+// uncomment this for register file in extra module
+// `define PICORV32_REGS picorv32_regs
+
+// this macro can be used to check if the verilog files in your
+// design are read in the correct order.
+`define PICORV32_V
+
+
+/***************************************************************
+ * picorv32
+ ***************************************************************/
+
+module picorv32 #(
+ parameter [ 0:0] ENABLE_COUNTERS = 1,
+ parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+ parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+ parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+ parameter [ 0:0] LATCHED_MEM_RDATA = 0,
+ parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+ parameter [ 0:0] BARREL_SHIFTER = 0,
+ parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+ parameter [ 0:0] TWO_CYCLE_ALU = 0,
+ parameter [ 0:0] COMPRESSED_ISA = 0,
+ parameter [ 0:0] CATCH_MISALIGN = 1,
+ parameter [ 0:0] CATCH_ILLINSN = 1,
+ parameter [ 0:0] ENABLE_PCPI = 0,
+ parameter [ 0:0] ENABLE_MUL = 0,
+ parameter [ 0:0] ENABLE_FAST_MUL = 0,
+ parameter [ 0:0] ENABLE_DIV = 0,
+ parameter [ 0:0] ENABLE_IRQ = 0,
+ parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+ parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+ parameter [ 0:0] ENABLE_TRACE = 0,
+ parameter [ 0:0] REGS_INIT_ZERO = 0,
+ parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+ parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+ parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+ parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+ parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+ input clk, resetn,
+ output reg trap,
+
+ output reg mem_valid,
+ output reg mem_instr,
+ input mem_ready,
+
+ output reg [31:0] mem_addr,
+ output reg [31:0] mem_wdata,
+ output reg [ 3:0] mem_wstrb,
+ input [31:0] mem_rdata,
+
+ // Look-Ahead Interface
+ output mem_la_read,
+ output mem_la_write,
+ output [31:0] mem_la_addr,
+ output reg [31:0] mem_la_wdata,
+ output reg [ 3:0] mem_la_wstrb,
+
+ // Pico Co-Processor Interface (PCPI)
+ output reg pcpi_valid,
+ output reg [31:0] pcpi_insn,
+ output [31:0] pcpi_rs1,
+ output [31:0] pcpi_rs2,
+ input pcpi_wr,
+ input [31:0] pcpi_rd,
+ input pcpi_wait,
+ input pcpi_ready,
+
+ // IRQ Interface
+ input [31:0] irq,
+ output reg [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+ output reg rvfi_valid,
+ output reg [63:0] rvfi_order,
+ output reg [31:0] rvfi_insn,
+ output reg rvfi_trap,
+ output reg rvfi_halt,
+ output reg rvfi_intr,
+ output reg [ 1:0] rvfi_mode,
+ output reg [ 1:0] rvfi_ixl,
+ output reg [ 4:0] rvfi_rs1_addr,
+ output reg [ 4:0] rvfi_rs2_addr,
+ output reg [31:0] rvfi_rs1_rdata,
+ output reg [31:0] rvfi_rs2_rdata,
+ output reg [ 4:0] rvfi_rd_addr,
+ output reg [31:0] rvfi_rd_wdata,
+ output reg [31:0] rvfi_pc_rdata,
+ output reg [31:0] rvfi_pc_wdata,
+ output reg [31:0] rvfi_mem_addr,
+ output reg [ 3:0] rvfi_mem_rmask,
+ output reg [ 3:0] rvfi_mem_wmask,
+ output reg [31:0] rvfi_mem_rdata,
+ output reg [31:0] rvfi_mem_wdata,
+
+ output reg [63:0] rvfi_csr_mcycle_rmask,
+ output reg [63:0] rvfi_csr_mcycle_wmask,
+ output reg [63:0] rvfi_csr_mcycle_rdata,
+ output reg [63:0] rvfi_csr_mcycle_wdata,
+
+ output reg [63:0] rvfi_csr_minstret_rmask,
+ output reg [63:0] rvfi_csr_minstret_wmask,
+ output reg [63:0] rvfi_csr_minstret_rdata,
+ output reg [63:0] rvfi_csr_minstret_wdata,
+`endif
+
+ // Trace Interface
+ output reg trace_valid,
+ output reg [35:0] trace_data
+);
+ localparam integer irq_timer = 0;
+ localparam integer irq_ebreak = 1;
+ localparam integer irq_buserror = 2;
+
+ localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
+ localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
+ localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
+
+ localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
+
+ localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
+ localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
+ localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
+
+ reg [63:0] count_cycle, count_instr;
+ reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
+ reg [4:0] reg_sh;
+
+ reg [31:0] next_insn_opcode;
+ reg [31:0] dbg_insn_opcode;
+ reg [31:0] dbg_insn_addr;
+
+ wire dbg_mem_valid = mem_valid;
+ wire dbg_mem_instr = mem_instr;
+ wire dbg_mem_ready = mem_ready;
+ wire [31:0] dbg_mem_addr = mem_addr;
+ wire [31:0] dbg_mem_wdata = mem_wdata;
+ wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
+ wire [31:0] dbg_mem_rdata = mem_rdata;
+
+ assign pcpi_rs1 = reg_op1;
+ assign pcpi_rs2 = reg_op2;
+
+ wire [31:0] next_pc;
+
+ reg irq_delay;
+ reg irq_active;
+ reg [31:0] irq_mask;
+ reg [31:0] irq_pending;
+ reg [31:0] timer;
+
+`ifndef PICORV32_REGS
+ reg [31:0] cpuregs [0:regfile_size-1];
+
+ integer i;
+ initial begin
+ if (REGS_INIT_ZERO) begin
+ for (i = 0; i < regfile_size; i = i+1)
+ cpuregs[i] = 0;
+ end
+ end
+`endif
+
+ task empty_statement;
+ // This task is used by the `assert directive in non-formal mode to
+ // avoid empty statement (which are unsupported by plain Verilog syntax).
+ begin end
+ endtask
+
+`ifdef DEBUGREGS
+ wire [31:0] dbg_reg_x0 = 0;
+ wire [31:0] dbg_reg_x1 = cpuregs[1];
+ wire [31:0] dbg_reg_x2 = cpuregs[2];
+ wire [31:0] dbg_reg_x3 = cpuregs[3];
+ wire [31:0] dbg_reg_x4 = cpuregs[4];
+ wire [31:0] dbg_reg_x5 = cpuregs[5];
+ wire [31:0] dbg_reg_x6 = cpuregs[6];
+ wire [31:0] dbg_reg_x7 = cpuregs[7];
+ wire [31:0] dbg_reg_x8 = cpuregs[8];
+ wire [31:0] dbg_reg_x9 = cpuregs[9];
+ wire [31:0] dbg_reg_x10 = cpuregs[10];
+ wire [31:0] dbg_reg_x11 = cpuregs[11];
+ wire [31:0] dbg_reg_x12 = cpuregs[12];
+ wire [31:0] dbg_reg_x13 = cpuregs[13];
+ wire [31:0] dbg_reg_x14 = cpuregs[14];
+ wire [31:0] dbg_reg_x15 = cpuregs[15];
+ wire [31:0] dbg_reg_x16 = cpuregs[16];
+ wire [31:0] dbg_reg_x17 = cpuregs[17];
+ wire [31:0] dbg_reg_x18 = cpuregs[18];
+ wire [31:0] dbg_reg_x19 = cpuregs[19];
+ wire [31:0] dbg_reg_x20 = cpuregs[20];
+ wire [31:0] dbg_reg_x21 = cpuregs[21];
+ wire [31:0] dbg_reg_x22 = cpuregs[22];
+ wire [31:0] dbg_reg_x23 = cpuregs[23];
+ wire [31:0] dbg_reg_x24 = cpuregs[24];
+ wire [31:0] dbg_reg_x25 = cpuregs[25];
+ wire [31:0] dbg_reg_x26 = cpuregs[26];
+ wire [31:0] dbg_reg_x27 = cpuregs[27];
+ wire [31:0] dbg_reg_x28 = cpuregs[28];
+ wire [31:0] dbg_reg_x29 = cpuregs[29];
+ wire [31:0] dbg_reg_x30 = cpuregs[30];
+ wire [31:0] dbg_reg_x31 = cpuregs[31];
+`endif
+
+ // Internal PCPI Cores
+
+ wire pcpi_mul_wr;
+ wire [31:0] pcpi_mul_rd;
+ wire pcpi_mul_wait;
+ wire pcpi_mul_ready;
+
+ wire pcpi_div_wr;
+ wire [31:0] pcpi_div_rd;
+ wire pcpi_div_wait;
+ wire pcpi_div_ready;
+
+ reg pcpi_int_wr;
+ reg [31:0] pcpi_int_rd;
+ reg pcpi_int_wait;
+ reg pcpi_int_ready;
+
+ generate if (ENABLE_FAST_MUL) begin
+ picorv32_pcpi_fast_mul pcpi_mul (
+ .clk (clk ),
+ .resetn (resetn ),
+ .pcpi_valid(pcpi_valid ),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_mul_wr ),
+ .pcpi_rd (pcpi_mul_rd ),
+ .pcpi_wait (pcpi_mul_wait ),
+ .pcpi_ready(pcpi_mul_ready )
+ );
+ end else if (ENABLE_MUL) begin
+ picorv32_pcpi_mul pcpi_mul (
+ .clk (clk ),
+ .resetn (resetn ),
+ .pcpi_valid(pcpi_valid ),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_mul_wr ),
+ .pcpi_rd (pcpi_mul_rd ),
+ .pcpi_wait (pcpi_mul_wait ),
+ .pcpi_ready(pcpi_mul_ready )
+ );
+ end else begin
+ assign pcpi_mul_wr = 0;
+ assign pcpi_mul_rd = 32'bx;
+ assign pcpi_mul_wait = 0;
+ assign pcpi_mul_ready = 0;
+ end endgenerate
+
+ generate if (ENABLE_DIV) begin
+ picorv32_pcpi_div pcpi_div (
+ .clk (clk ),
+ .resetn (resetn ),
+ .pcpi_valid(pcpi_valid ),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_div_wr ),
+ .pcpi_rd (pcpi_div_rd ),
+ .pcpi_wait (pcpi_div_wait ),
+ .pcpi_ready(pcpi_div_ready )
+ );
+ end else begin
+ assign pcpi_div_wr = 0;
+ assign pcpi_div_rd = 32'bx;
+ assign pcpi_div_wait = 0;
+ assign pcpi_div_ready = 0;
+ end endgenerate
+
+ always @* begin
+ pcpi_int_wr = 0;
+ pcpi_int_rd = 32'bx;
+ pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
+ pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
+
+ (* parallel_case *)
+ case (1'b1)
+ ENABLE_PCPI && pcpi_ready: begin
+ pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
+ pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
+ end
+ (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
+ pcpi_int_wr = pcpi_mul_wr;
+ pcpi_int_rd = pcpi_mul_rd;
+ end
+ ENABLE_DIV && pcpi_div_ready: begin
+ pcpi_int_wr = pcpi_div_wr;
+ pcpi_int_rd = pcpi_div_rd;
+ end
+ endcase
+ end
+
+
+ // Memory Interface
+
+ reg [1:0] mem_state;
+ reg [1:0] mem_wordsize;
+ reg [31:0] mem_rdata_word;
+ reg [31:0] mem_rdata_q;
+ reg mem_do_prefetch;
+ reg mem_do_rinst;
+ reg mem_do_rdata;
+ reg mem_do_wdata;
+
+ wire mem_xfer;
+ reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
+ wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
+ wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
+
+ reg prefetched_high_word;
+ reg clear_prefetched_high_word;
+ reg [15:0] mem_16bit_buffer;
+
+ wire [31:0] mem_rdata_latched_noshuffle;
+ wire [31:0] mem_rdata_latched;
+
+ wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
+ assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
+
+ wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
+ wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
+ (!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
+
+ assign mem_la_write = resetn && !mem_state && mem_do_wdata;
+ assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
+ (COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
+ assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
+
+ assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
+
+ assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
+ COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
+ COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ mem_la_firstword_reg <= 0;
+ last_mem_valid <= 0;
+ end else begin
+ if (!last_mem_valid)
+ mem_la_firstword_reg <= mem_la_firstword;
+ last_mem_valid <= mem_valid && !mem_ready;
+ end
+ end
+
+ always @* begin
+ (* full_case *)
+ case (mem_wordsize)
+ 0: begin
+ mem_la_wdata = reg_op2;
+ mem_la_wstrb = 4'b1111;
+ mem_rdata_word = mem_rdata;
+ end
+ 1: begin
+ mem_la_wdata = {2{reg_op2[15:0]}};
+ mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
+ case (reg_op1[1])
+ 1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
+ 1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
+ endcase
+ end
+ 2: begin
+ mem_la_wdata = {4{reg_op2[7:0]}};
+ mem_la_wstrb = 4'b0001 << reg_op1[1:0];
+ case (reg_op1[1:0])
+ 2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
+ 2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
+ 2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
+ 2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
+ endcase
+ end
+ endcase
+ end
+
+ always @(posedge clk) begin
+ if (mem_xfer) begin
+ mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+ next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+ end
+
+ if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
+ case (mem_rdata_latched[1:0])
+ 2'b00: begin // Quadrant 0
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.ADDI4SPN
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
+ end
+ 3'b010: begin // C.LW
+ mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+ mem_rdata_q[14:12] <= 3'b 010;
+ end
+ 3'b 110: begin // C.SW
+ {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+ mem_rdata_q[14:12] <= 3'b 010;
+ end
+ endcase
+ end
+ 2'b01: begin // Quadrant 1
+ case (mem_rdata_latched[15:13])
+ 3'b 000: begin // C.ADDI
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+ end
+ 3'b 010: begin // C.LI
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+ end
+ 3'b 011: begin
+ if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
+ mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
+ end else begin // C.LUI
+ mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+ end
+ end
+ 3'b100: begin
+ if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
+ mem_rdata_q[31:25] <= 7'b0000000;
+ mem_rdata_q[14:12] <= 3'b 101;
+ end
+ if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
+ mem_rdata_q[31:25] <= 7'b0100000;
+ mem_rdata_q[14:12] <= 3'b 101;
+ end
+ if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+ mem_rdata_q[14:12] <= 3'b111;
+ mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+ end
+ if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+ if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
+ if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
+ if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
+ if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
+ mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
+ end
+ end
+ 3'b 110: begin // C.BEQZ
+ mem_rdata_q[14:12] <= 3'b000;
+ { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+ $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+ mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+ end
+ 3'b 111: begin // C.BNEZ
+ mem_rdata_q[14:12] <= 3'b001;
+ { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+ $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+ mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+ end
+ endcase
+ end
+ 2'b10: begin // Quadrant 2
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.SLLI
+ mem_rdata_q[31:25] <= 7'b0000000;
+ mem_rdata_q[14:12] <= 3'b 001;
+ end
+ 3'b010: begin // C.LWSP
+ mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
+ mem_rdata_q[14:12] <= 3'b 010;
+ end
+ 3'b100: begin
+ if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= 12'b0;
+ end
+ if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:25] <= 7'b0000000;
+ end
+ if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= 12'b0;
+ end
+ if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:25] <= 7'b0000000;
+ end
+ end
+ 3'b110: begin // C.SWSP
+ {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
+ mem_rdata_q[14:12] <= 3'b 010;
+ end
+ endcase
+ end
+ endcase
+ end
+ end
+
+ always @(posedge clk) begin
+ if (resetn && !trap) begin
+ if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
+ `assert(!mem_do_wdata);
+
+ if (mem_do_prefetch || mem_do_rinst)
+ `assert(!mem_do_rdata);
+
+ if (mem_do_rdata)
+ `assert(!mem_do_prefetch && !mem_do_rinst);
+
+ if (mem_do_wdata)
+ `assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
+
+ if (mem_state == 2 || mem_state == 3)
+ `assert(mem_valid || mem_do_prefetch);
+ end
+ end
+
+ always @(posedge clk) begin
+ if (!resetn || trap) begin
+ if (!resetn)
+ mem_state <= 0;
+ if (!resetn || mem_ready)
+ mem_valid <= 0;
+ mem_la_secondword <= 0;
+ prefetched_high_word <= 0;
+ end else begin
+ if (mem_la_read || mem_la_write) begin
+ mem_addr <= mem_la_addr;
+ mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
+ end
+ if (mem_la_write) begin
+ mem_wdata <= mem_la_wdata;
+ end
+ case (mem_state)
+ 0: begin
+ if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
+ mem_valid <= !mem_la_use_prefetched_high_word;
+ mem_instr <= mem_do_prefetch || mem_do_rinst;
+ mem_wstrb <= 0;
+ mem_state <= 1;
+ end
+ if (mem_do_wdata) begin
+ mem_valid <= 1;
+ mem_instr <= 0;
+ mem_state <= 2;
+ end
+ end
+ 1: begin
+ `assert(mem_wstrb == 0);
+ `assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
+ `assert(mem_valid == !mem_la_use_prefetched_high_word);
+ `assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
+ if (mem_xfer) begin
+ if (COMPRESSED_ISA && mem_la_read) begin
+ mem_valid <= 1;
+ mem_la_secondword <= 1;
+ if (!mem_la_use_prefetched_high_word)
+ mem_16bit_buffer <= mem_rdata[31:16];
+ end else begin
+ mem_valid <= 0;
+ mem_la_secondword <= 0;
+ if (COMPRESSED_ISA && !mem_do_rdata) begin
+ if (~&mem_rdata[1:0] || mem_la_secondword) begin
+ mem_16bit_buffer <= mem_rdata[31:16];
+ prefetched_high_word <= 1;
+ end else begin
+ prefetched_high_word <= 0;
+ end
+ end
+ mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
+ end
+ end
+ end
+ 2: begin
+ `assert(mem_wstrb != 0);
+ `assert(mem_do_wdata);
+ if (mem_xfer) begin
+ mem_valid <= 0;
+ mem_state <= 0;
+ end
+ end
+ 3: begin
+ `assert(mem_wstrb == 0);
+ `assert(mem_do_prefetch);
+ if (mem_do_rinst) begin
+ mem_state <= 0;
+ end
+ end
+ endcase
+ end
+
+ if (clear_prefetched_high_word)
+ prefetched_high_word <= 0;
+ end
+
+
+ // Instruction Decoder
+
+ reg instr_lui, instr_auipc, instr_jal, instr_jalr;
+ reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
+ reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
+ reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
+ reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
+ reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
+ reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
+ wire instr_trap;
+
+ reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
+ reg [31:0] decoded_imm, decoded_imm_j;
+ reg decoder_trigger;
+ reg decoder_trigger_q;
+ reg decoder_pseudo_trigger;
+ reg decoder_pseudo_trigger_q;
+ reg compressed_instr;
+
+ reg is_lui_auipc_jal;
+ reg is_lb_lh_lw_lbu_lhu;
+ reg is_slli_srli_srai;
+ reg is_jalr_addi_slti_sltiu_xori_ori_andi;
+ reg is_sb_sh_sw;
+ reg is_sll_srl_sra;
+ reg is_lui_auipc_jal_jalr_addi_add_sub;
+ reg is_slti_blt_slt;
+ reg is_sltiu_bltu_sltu;
+ reg is_beq_bne_blt_bge_bltu_bgeu;
+ reg is_lbu_lhu_lw;
+ reg is_alu_reg_imm;
+ reg is_alu_reg_reg;
+ reg is_compare;
+
+ assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
+ instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
+ instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
+ instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
+ instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
+ instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
+ instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
+
+ wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
+ assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
+
+ reg [63:0] new_ascii_instr;
+ `FORMAL_KEEP reg [63:0] dbg_ascii_instr;
+ `FORMAL_KEEP reg [31:0] dbg_insn_imm;
+ `FORMAL_KEEP reg [4:0] dbg_insn_rs1;
+ `FORMAL_KEEP reg [4:0] dbg_insn_rs2;
+ `FORMAL_KEEP reg [4:0] dbg_insn_rd;
+ `FORMAL_KEEP reg [31:0] dbg_rs1val;
+ `FORMAL_KEEP reg [31:0] dbg_rs2val;
+ `FORMAL_KEEP reg dbg_rs1val_valid;
+ `FORMAL_KEEP reg dbg_rs2val_valid;
+
+ always @* begin
+ new_ascii_instr = "";
+
+ if (instr_lui) new_ascii_instr = "lui";
+ if (instr_auipc) new_ascii_instr = "auipc";
+ if (instr_jal) new_ascii_instr = "jal";
+ if (instr_jalr) new_ascii_instr = "jalr";
+
+ if (instr_beq) new_ascii_instr = "beq";
+ if (instr_bne) new_ascii_instr = "bne";
+ if (instr_blt) new_ascii_instr = "blt";
+ if (instr_bge) new_ascii_instr = "bge";
+ if (instr_bltu) new_ascii_instr = "bltu";
+ if (instr_bgeu) new_ascii_instr = "bgeu";
+
+ if (instr_lb) new_ascii_instr = "lb";
+ if (instr_lh) new_ascii_instr = "lh";
+ if (instr_lw) new_ascii_instr = "lw";
+ if (instr_lbu) new_ascii_instr = "lbu";
+ if (instr_lhu) new_ascii_instr = "lhu";
+ if (instr_sb) new_ascii_instr = "sb";
+ if (instr_sh) new_ascii_instr = "sh";
+ if (instr_sw) new_ascii_instr = "sw";
+
+ if (instr_addi) new_ascii_instr = "addi";
+ if (instr_slti) new_ascii_instr = "slti";
+ if (instr_sltiu) new_ascii_instr = "sltiu";
+ if (instr_xori) new_ascii_instr = "xori";
+ if (instr_ori) new_ascii_instr = "ori";
+ if (instr_andi) new_ascii_instr = "andi";
+ if (instr_slli) new_ascii_instr = "slli";
+ if (instr_srli) new_ascii_instr = "srli";
+ if (instr_srai) new_ascii_instr = "srai";
+
+ if (instr_add) new_ascii_instr = "add";
+ if (instr_sub) new_ascii_instr = "sub";
+ if (instr_sll) new_ascii_instr = "sll";
+ if (instr_slt) new_ascii_instr = "slt";
+ if (instr_sltu) new_ascii_instr = "sltu";
+ if (instr_xor) new_ascii_instr = "xor";
+ if (instr_srl) new_ascii_instr = "srl";
+ if (instr_sra) new_ascii_instr = "sra";
+ if (instr_or) new_ascii_instr = "or";
+ if (instr_and) new_ascii_instr = "and";
+
+ if (instr_rdcycle) new_ascii_instr = "rdcycle";
+ if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
+ if (instr_rdinstr) new_ascii_instr = "rdinstr";
+ if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
+
+ if (instr_getq) new_ascii_instr = "getq";
+ if (instr_setq) new_ascii_instr = "setq";
+ if (instr_retirq) new_ascii_instr = "retirq";
+ if (instr_maskirq) new_ascii_instr = "maskirq";
+ if (instr_waitirq) new_ascii_instr = "waitirq";
+ if (instr_timer) new_ascii_instr = "timer";
+ end
+
+ reg [63:0] q_ascii_instr;
+ reg [31:0] q_insn_imm;
+ reg [31:0] q_insn_opcode;
+ reg [4:0] q_insn_rs1;
+ reg [4:0] q_insn_rs2;
+ reg [4:0] q_insn_rd;
+ reg dbg_next;
+
+ wire launch_next_insn;
+ reg dbg_valid_insn;
+
+ reg [63:0] cached_ascii_instr;
+ reg [31:0] cached_insn_imm;
+ reg [31:0] cached_insn_opcode;
+ reg [4:0] cached_insn_rs1;
+ reg [4:0] cached_insn_rs2;
+ reg [4:0] cached_insn_rd;
+
+ always @(posedge clk) begin
+ q_ascii_instr <= dbg_ascii_instr;
+ q_insn_imm <= dbg_insn_imm;
+ q_insn_opcode <= dbg_insn_opcode;
+ q_insn_rs1 <= dbg_insn_rs1;
+ q_insn_rs2 <= dbg_insn_rs2;
+ q_insn_rd <= dbg_insn_rd;
+ dbg_next <= launch_next_insn;
+
+ if (!resetn || trap)
+ dbg_valid_insn <= 0;
+ else if (launch_next_insn)
+ dbg_valid_insn <= 1;
+
+ if (decoder_trigger_q) begin
+ cached_ascii_instr <= new_ascii_instr;
+ cached_insn_imm <= decoded_imm;
+ if (&next_insn_opcode[1:0])
+ cached_insn_opcode <= next_insn_opcode;
+ else
+ cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
+ cached_insn_rs1 <= decoded_rs1;
+ cached_insn_rs2 <= decoded_rs2;
+ cached_insn_rd <= decoded_rd;
+ end
+
+ if (launch_next_insn) begin
+ dbg_insn_addr <= next_pc;
+ end
+ end
+
+ always @* begin
+ dbg_ascii_instr = q_ascii_instr;
+ dbg_insn_imm = q_insn_imm;
+ dbg_insn_opcode = q_insn_opcode;
+ dbg_insn_rs1 = q_insn_rs1;
+ dbg_insn_rs2 = q_insn_rs2;
+ dbg_insn_rd = q_insn_rd;
+
+ if (dbg_next) begin
+ if (decoder_pseudo_trigger_q) begin
+ dbg_ascii_instr = cached_ascii_instr;
+ dbg_insn_imm = cached_insn_imm;
+ dbg_insn_opcode = cached_insn_opcode;
+ dbg_insn_rs1 = cached_insn_rs1;
+ dbg_insn_rs2 = cached_insn_rs2;
+ dbg_insn_rd = cached_insn_rd;
+ end else begin
+ dbg_ascii_instr = new_ascii_instr;
+ if (&next_insn_opcode[1:0])
+ dbg_insn_opcode = next_insn_opcode;
+ else
+ dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
+ dbg_insn_imm = decoded_imm;
+ dbg_insn_rs1 = decoded_rs1;
+ dbg_insn_rs2 = decoded_rs2;
+ dbg_insn_rd = decoded_rd;
+ end
+ end
+ end
+
+`ifdef DEBUGASM
+ always @(posedge clk) begin
+ if (dbg_next) begin
+ $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
+ end
+ end
+`endif
+
+`ifdef DEBUG
+ always @(posedge clk) begin
+ if (dbg_next) begin
+ if (&dbg_insn_opcode[1:0])
+ $display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+ else
+ $display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+ end
+ end
+`endif
+
+ always @(posedge clk) begin
+ is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
+ is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
+ is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
+ is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
+ is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
+ is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
+
+ if (mem_do_rinst && mem_done) begin
+ instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
+ instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
+ instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
+ instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
+ instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
+ instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
+
+ is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
+ is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
+ is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
+ is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
+ is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
+
+ { decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
+
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[19:15];
+ decoded_rs2 <= mem_rdata_latched[24:20];
+
+ if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
+ decoded_rs1[regindex_bits-1] <= 1; // instr_getq
+
+ if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
+ decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
+
+ compressed_instr <= 0;
+ if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
+ compressed_instr <= 1;
+ decoded_rd <= 0;
+ decoded_rs1 <= 0;
+ decoded_rs2 <= 0;
+
+ { decoded_imm_j[31:11], decoded_imm_j[4], decoded_imm_j[9:8], decoded_imm_j[10], decoded_imm_j[6],
+ decoded_imm_j[7], decoded_imm_j[3:1], decoded_imm_j[5], decoded_imm_j[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
+
+ case (mem_rdata_latched[1:0])
+ 2'b00: begin // Quadrant 0
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.ADDI4SPN
+ is_alu_reg_imm <= |mem_rdata_latched[12:5];
+ decoded_rs1 <= 2;
+ decoded_rd <= 8 + mem_rdata_latched[4:2];
+ end
+ 3'b010: begin // C.LW
+ is_lb_lh_lw_lbu_lhu <= 1;
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rd <= 8 + mem_rdata_latched[4:2];
+ end
+ 3'b110: begin // C.SW
+ is_sb_sh_sw <= 1;
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+ end
+ endcase
+ end
+ 2'b01: begin // Quadrant 1
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.NOP / C.ADDI
+ is_alu_reg_imm <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ end
+ 3'b001: begin // C.JAL
+ instr_jal <= 1;
+ decoded_rd <= 1;
+ end
+ 3'b 010: begin // C.LI
+ is_alu_reg_imm <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= 0;
+ end
+ 3'b 011: begin
+ if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
+ if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+ is_alu_reg_imm <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ end else begin // C.LUI
+ instr_lui <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= 0;
+ end
+ end
+ end
+ 3'b100: begin
+ if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
+ is_alu_reg_imm <= 1;
+ decoded_rd <= 8 + mem_rdata_latched[9:7];
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+ end
+ if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+ is_alu_reg_imm <= 1;
+ decoded_rd <= 8 + mem_rdata_latched[9:7];
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ end
+ if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+ is_alu_reg_reg <= 1;
+ decoded_rd <= 8 + mem_rdata_latched[9:7];
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+ end
+ end
+ 3'b101: begin // C.J
+ instr_jal <= 1;
+ end
+ 3'b110: begin // C.BEQZ
+ is_beq_bne_blt_bge_bltu_bgeu <= 1;
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= 0;
+ end
+ 3'b111: begin // C.BNEZ
+ is_beq_bne_blt_bge_bltu_bgeu <= 1;
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= 0;
+ end
+ endcase
+ end
+ 2'b10: begin // Quadrant 2
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.SLLI
+ if (!mem_rdata_latched[12]) begin
+ is_alu_reg_imm <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+ end
+ end
+ 3'b010: begin // C.LWSP
+ if (mem_rdata_latched[11:7]) begin
+ is_lb_lh_lw_lbu_lhu <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= 2;
+ end
+ end
+ 3'b100: begin
+ if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+ instr_jalr <= 1;
+ decoded_rd <= 0;
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ end
+ if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+ is_alu_reg_reg <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= 0;
+ decoded_rs2 <= mem_rdata_latched[6:2];
+ end
+ if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+ instr_jalr <= 1;
+ decoded_rd <= 1;
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ end
+ if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+ is_alu_reg_reg <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ decoded_rs2 <= mem_rdata_latched[6:2];
+ end
+ end
+ 3'b110: begin // C.SWSP
+ is_sb_sh_sw <= 1;
+ decoded_rs1 <= 2;
+ decoded_rs2 <= mem_rdata_latched[6:2];
+ end
+ endcase
+ end
+ endcase
+ end
+ end
+
+ if (decoder_trigger && !decoder_pseudo_trigger) begin
+ pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
+
+ instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
+ instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
+ instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
+ instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
+ instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
+ instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
+
+ instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
+ instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
+ instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
+ instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
+ instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
+
+ instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
+ instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
+ instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
+
+ instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
+ instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
+ instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
+ instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
+ instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
+ instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
+
+ instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+
+ instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
+ instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+ instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
+
+ instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
+ (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
+ instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
+ (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+ instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
+ instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+
+ instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
+ (COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
+
+ instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+ instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+ instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
+ instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
+
+ is_slli_srli_srai <= is_alu_reg_imm && |{
+ mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+ mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+ mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+ };
+
+ is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
+ mem_rdata_q[14:12] == 3'b000,
+ mem_rdata_q[14:12] == 3'b010,
+ mem_rdata_q[14:12] == 3'b011,
+ mem_rdata_q[14:12] == 3'b100,
+ mem_rdata_q[14:12] == 3'b110,
+ mem_rdata_q[14:12] == 3'b111
+ };
+
+ is_sll_srl_sra <= is_alu_reg_reg && |{
+ mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+ mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+ mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+ };
+
+ is_lui_auipc_jal_jalr_addi_add_sub <= 0;
+ is_compare <= 0;
+
+ (* parallel_case *)
+ case (1'b1)
+ instr_jal:
+ decoded_imm <= decoded_imm_j;
+ |{instr_lui, instr_auipc}:
+ decoded_imm <= mem_rdata_q[31:12] << 12;
+ |{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
+ decoded_imm <= $signed(mem_rdata_q[31:20]);
+ is_beq_bne_blt_bge_bltu_bgeu:
+ decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
+ is_sb_sh_sw:
+ decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
+ default:
+ decoded_imm <= 1'bx;
+ endcase
+ end
+
+ if (!resetn) begin
+ is_beq_bne_blt_bge_bltu_bgeu <= 0;
+ is_compare <= 0;
+
+ instr_beq <= 0;
+ instr_bne <= 0;
+ instr_blt <= 0;
+ instr_bge <= 0;
+ instr_bltu <= 0;
+ instr_bgeu <= 0;
+
+ instr_addi <= 0;
+ instr_slti <= 0;
+ instr_sltiu <= 0;
+ instr_xori <= 0;
+ instr_ori <= 0;
+ instr_andi <= 0;
+
+ instr_add <= 0;
+ instr_sub <= 0;
+ instr_sll <= 0;
+ instr_slt <= 0;
+ instr_sltu <= 0;
+ instr_xor <= 0;
+ instr_srl <= 0;
+ instr_sra <= 0;
+ instr_or <= 0;
+ instr_and <= 0;
+ end
+ end
+
+
+ // Main State Machine
+
+ localparam cpu_state_trap = 8'b10000000;
+ localparam cpu_state_fetch = 8'b01000000;
+ localparam cpu_state_ld_rs1 = 8'b00100000;
+ localparam cpu_state_ld_rs2 = 8'b00010000;
+ localparam cpu_state_exec = 8'b00001000;
+ localparam cpu_state_shift = 8'b00000100;
+ localparam cpu_state_stmem = 8'b00000010;
+ localparam cpu_state_ldmem = 8'b00000001;
+
+ reg [7:0] cpu_state;
+ reg [1:0] irq_state;
+
+ `FORMAL_KEEP reg [127:0] dbg_ascii_state;
+
+ always @* begin
+ dbg_ascii_state = "";
+ if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
+ if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
+ if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
+ if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
+ if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
+ if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
+ if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
+ if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
+ end
+
+ reg set_mem_do_rinst;
+ reg set_mem_do_rdata;
+ reg set_mem_do_wdata;
+
+ reg latched_store;
+ reg latched_stalu;
+ reg latched_branch;
+ reg latched_compr;
+ reg latched_trace;
+ reg latched_is_lu;
+ reg latched_is_lh;
+ reg latched_is_lb;
+ reg [regindex_bits-1:0] latched_rd;
+
+ reg [31:0] current_pc;
+ assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
+
+ reg [3:0] pcpi_timeout_counter;
+ reg pcpi_timeout;
+
+ reg [31:0] next_irq_pending;
+ reg do_waitirq;
+
+ reg [31:0] alu_out, alu_out_q;
+ reg alu_out_0, alu_out_0_q;
+ reg alu_wait, alu_wait_2;
+
+ reg [31:0] alu_add_sub;
+ reg [31:0] alu_shl, alu_shr;
+ reg alu_eq, alu_ltu, alu_lts;
+
+ generate if (TWO_CYCLE_ALU) begin
+ always @(posedge clk) begin
+ alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+ alu_eq <= reg_op1 == reg_op2;
+ alu_lts <= $signed(reg_op1) < $signed(reg_op2);
+ alu_ltu <= reg_op1 < reg_op2;
+ alu_shl <= reg_op1 << reg_op2[4:0];
+ alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+ end
+ end else begin
+ always @* begin
+ alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+ alu_eq = reg_op1 == reg_op2;
+ alu_lts = $signed(reg_op1) < $signed(reg_op2);
+ alu_ltu = reg_op1 < reg_op2;
+ alu_shl = reg_op1 << reg_op2[4:0];
+ alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+ end
+ end endgenerate
+
+ always @* begin
+ alu_out_0 = 'bx;
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_beq:
+ alu_out_0 = alu_eq;
+ instr_bne:
+ alu_out_0 = !alu_eq;
+ instr_bge:
+ alu_out_0 = !alu_lts;
+ instr_bgeu:
+ alu_out_0 = !alu_ltu;
+ is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+ alu_out_0 = alu_lts;
+ is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+ alu_out_0 = alu_ltu;
+ endcase
+
+ alu_out = 'bx;
+ (* parallel_case, full_case *)
+ case (1'b1)
+ is_lui_auipc_jal_jalr_addi_add_sub:
+ alu_out = alu_add_sub;
+ is_compare:
+ alu_out = alu_out_0;
+ instr_xori || instr_xor:
+ alu_out = reg_op1 ^ reg_op2;
+ instr_ori || instr_or:
+ alu_out = reg_op1 | reg_op2;
+ instr_andi || instr_and:
+ alu_out = reg_op1 & reg_op2;
+ BARREL_SHIFTER && (instr_sll || instr_slli):
+ alu_out = alu_shl;
+ BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
+ alu_out = alu_shr;
+ endcase
+
+`ifdef RISCV_FORMAL_BLACKBOX_ALU
+ alu_out_0 = $anyseq;
+ alu_out = $anyseq;
+`endif
+ end
+
+ reg clear_prefetched_high_word_q;
+ always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
+
+ always @* begin
+ clear_prefetched_high_word = clear_prefetched_high_word_q;
+ if (!prefetched_high_word)
+ clear_prefetched_high_word = 0;
+ if (latched_branch || irq_state || !resetn)
+ clear_prefetched_high_word = COMPRESSED_ISA;
+ end
+
+ reg cpuregs_write;
+ reg [31:0] cpuregs_wrdata;
+ reg [31:0] cpuregs_rs1;
+ reg [31:0] cpuregs_rs2;
+ reg [regindex_bits-1:0] decoded_rs;
+
+ always @* begin
+ cpuregs_write = 0;
+ cpuregs_wrdata = 'bx;
+
+ if (cpu_state == cpu_state_fetch) begin
+ (* parallel_case *)
+ case (1'b1)
+ latched_branch: begin
+ cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
+ cpuregs_write = 1;
+ end
+ latched_store && !latched_branch: begin
+ cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
+ cpuregs_write = 1;
+ end
+ ENABLE_IRQ && irq_state[0]: begin
+ cpuregs_wrdata = reg_next_pc | latched_compr;
+ cpuregs_write = 1;
+ end
+ ENABLE_IRQ && irq_state[1]: begin
+ cpuregs_wrdata = irq_pending & ~irq_mask;
+ cpuregs_write = 1;
+ end
+ endcase
+ end
+ end
+
+`ifndef PICORV32_REGS
+ always @(posedge clk) begin
+ if (resetn && cpuregs_write && latched_rd)
+`ifdef PICORV32_TESTBUG_001
+ cpuregs[latched_rd ^ 1] <= cpuregs_wrdata;
+`elsif PICORV32_TESTBUG_002
+ cpuregs[latched_rd] <= cpuregs_wrdata ^ 1;
+`else
+ cpuregs[latched_rd] <= cpuregs_wrdata;
+`endif
+ end
+
+ always @* begin
+ decoded_rs = 'bx;
+ if (ENABLE_REGS_DUALPORT) begin
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+ cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
+ cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
+`else
+ cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
+ cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
+`endif
+ end else begin
+ decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+ cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
+`else
+ cpuregs_rs1 = decoded_rs ? $anyseq : 0;
+`endif
+ cpuregs_rs2 = cpuregs_rs1;
+ end
+ end
+`else
+ wire[31:0] cpuregs_rdata1;
+ wire[31:0] cpuregs_rdata2;
+
+ wire [5:0] cpuregs_waddr = latched_rd;
+ wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
+ wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
+
+ `PICORV32_REGS cpuregs (
+ .clk(clk),
+ .wen(resetn && cpuregs_write && latched_rd),
+ .waddr(cpuregs_waddr),
+ .raddr1(cpuregs_raddr1),
+ .raddr2(cpuregs_raddr2),
+ .wdata(cpuregs_wrdata),
+ .rdata1(cpuregs_rdata1),
+ .rdata2(cpuregs_rdata2)
+ );
+
+ always @* begin
+ decoded_rs = 'bx;
+ if (ENABLE_REGS_DUALPORT) begin
+ cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
+ cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
+ end else begin
+ decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+ cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
+ cpuregs_rs2 = cpuregs_rs1;
+ end
+ end
+`endif
+
+ assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
+
+ always @(posedge clk) begin
+ trap <= 0;
+ reg_sh <= 'bx;
+ reg_out <= 'bx;
+ set_mem_do_rinst = 0;
+ set_mem_do_rdata = 0;
+ set_mem_do_wdata = 0;
+
+ alu_out_0_q <= alu_out_0;
+ alu_out_q <= alu_out;
+
+ alu_wait <= 0;
+ alu_wait_2 <= 0;
+
+ if (launch_next_insn) begin
+ dbg_rs1val <= 'bx;
+ dbg_rs2val <= 'bx;
+ dbg_rs1val_valid <= 0;
+ dbg_rs2val_valid <= 0;
+ end
+
+ if (WITH_PCPI && CATCH_ILLINSN) begin
+ if (resetn && pcpi_valid && !pcpi_int_wait) begin
+ if (pcpi_timeout_counter)
+ pcpi_timeout_counter <= pcpi_timeout_counter - 1;
+ end else
+ pcpi_timeout_counter <= ~0;
+ pcpi_timeout <= !pcpi_timeout_counter;
+ end
+
+ if (ENABLE_COUNTERS) begin
+ count_cycle <= resetn ? count_cycle + 1 : 0;
+ if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
+ end else begin
+ count_cycle <= 'bx;
+ count_instr <= 'bx;
+ end
+
+ next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
+
+ if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
+ timer <= timer - 1;
+ end
+
+ decoder_trigger <= mem_do_rinst && mem_done;
+ decoder_trigger_q <= decoder_trigger;
+ decoder_pseudo_trigger <= 0;
+ decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
+ do_waitirq <= 0;
+
+ trace_valid <= 0;
+
+ if (!ENABLE_TRACE)
+ trace_data <= 'bx;
+
+ if (!resetn) begin
+ reg_pc <= PROGADDR_RESET;
+ reg_next_pc <= PROGADDR_RESET;
+ if (ENABLE_COUNTERS)
+ count_instr <= 0;
+ latched_store <= 0;
+ latched_stalu <= 0;
+ latched_branch <= 0;
+ latched_trace <= 0;
+ latched_is_lu <= 0;
+ latched_is_lh <= 0;
+ latched_is_lb <= 0;
+ pcpi_valid <= 0;
+ pcpi_timeout <= 0;
+ irq_active <= 0;
+ irq_delay <= 0;
+ irq_mask <= ~0;
+ next_irq_pending = 0;
+ irq_state <= 0;
+ eoi <= 0;
+ timer <= 0;
+ if (~STACKADDR) begin
+ latched_store <= 1;
+ latched_rd <= 2;
+ reg_out <= STACKADDR;
+ end
+ cpu_state <= cpu_state_fetch;
+ end else
+ (* parallel_case, full_case *)
+ case (cpu_state)
+ cpu_state_trap: begin
+ trap <= 1;
+ end
+
+ cpu_state_fetch: begin
+ mem_do_rinst <= !decoder_trigger && !do_waitirq;
+ mem_wordsize <= 0;
+
+ current_pc = reg_next_pc;
+
+ (* parallel_case *)
+ case (1'b1)
+ latched_branch: begin
+ current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
+ `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
+ end
+ latched_store && !latched_branch: begin
+ `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
+ end
+ ENABLE_IRQ && irq_state[0]: begin
+ current_pc = PROGADDR_IRQ;
+ irq_active <= 1;
+ mem_do_rinst <= 1;
+ end
+ ENABLE_IRQ && irq_state[1]: begin
+ eoi <= irq_pending & ~irq_mask;
+ next_irq_pending = next_irq_pending & irq_mask;
+ end
+ endcase
+
+ if (ENABLE_TRACE && latched_trace) begin
+ latched_trace <= 0;
+ trace_valid <= 1;
+ if (latched_branch)
+ trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
+ else
+ trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
+ end
+
+ reg_pc <= current_pc;
+ reg_next_pc <= current_pc;
+
+ latched_store <= 0;
+ latched_stalu <= 0;
+ latched_branch <= 0;
+ latched_is_lu <= 0;
+ latched_is_lh <= 0;
+ latched_is_lb <= 0;
+ latched_rd <= decoded_rd;
+ latched_compr <= compressed_instr;
+
+ if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
+ irq_state <=
+ irq_state == 2'b00 ? 2'b01 :
+ irq_state == 2'b01 ? 2'b10 : 2'b00;
+ latched_compr <= latched_compr;
+ if (ENABLE_IRQ_QREGS)
+ latched_rd <= irqregs_offset | irq_state[0];
+ else
+ latched_rd <= irq_state[0] ? 4 : 3;
+ end else
+ if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
+ if (irq_pending) begin
+ latched_store <= 1;
+ reg_out <= irq_pending;
+ reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+ mem_do_rinst <= 1;
+ end else
+ do_waitirq <= 1;
+ end else
+ if (decoder_trigger) begin
+ `debug($display("-- %-0t", $time);)
+ irq_delay <= irq_active;
+ reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+ if (ENABLE_TRACE)
+ latched_trace <= 1;
+ if (ENABLE_COUNTERS) begin
+ count_instr <= count_instr + 1;
+ if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
+ end
+ if (instr_jal) begin
+ mem_do_rinst <= 1;
+ reg_next_pc <= current_pc + decoded_imm_j;
+ latched_branch <= 1;
+ end else begin
+ mem_do_rinst <= 0;
+ mem_do_prefetch <= !instr_jalr && !instr_retirq;
+ cpu_state <= cpu_state_ld_rs1;
+ end
+ end
+ end
+
+ cpu_state_ld_rs1: begin
+ reg_op1 <= 'bx;
+ reg_op2 <= 'bx;
+
+ (* parallel_case *)
+ case (1'b1)
+ (CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
+ if (WITH_PCPI) begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ if (ENABLE_REGS_DUALPORT) begin
+ pcpi_valid <= 1;
+ `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+ reg_sh <= cpuregs_rs2;
+ reg_op2 <= cpuregs_rs2;
+ dbg_rs2val <= cpuregs_rs2;
+ dbg_rs2val_valid <= 1;
+ if (pcpi_int_ready) begin
+ mem_do_rinst <= 1;
+ pcpi_valid <= 0;
+ reg_out <= pcpi_int_rd;
+ latched_store <= pcpi_int_wr;
+ cpu_state <= cpu_state_fetch;
+ end else
+ if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+ pcpi_valid <= 0;
+ `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+ if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+ next_irq_pending[irq_ebreak] = 1;
+ cpu_state <= cpu_state_fetch;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ end else begin
+ cpu_state <= cpu_state_ld_rs2;
+ end
+ end else begin
+ `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+ if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+ next_irq_pending[irq_ebreak] = 1;
+ cpu_state <= cpu_state_fetch;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ end
+ ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_rdcycle:
+ reg_out <= count_cycle[31:0];
+ instr_rdcycleh && ENABLE_COUNTERS64:
+ reg_out <= count_cycle[63:32];
+ instr_rdinstr:
+ reg_out <= count_instr[31:0];
+ instr_rdinstrh && ENABLE_COUNTERS64:
+ reg_out <= count_instr[63:32];
+ endcase
+ latched_store <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ is_lui_auipc_jal: begin
+ reg_op1 <= instr_lui ? 0 : reg_pc;
+ reg_op2 <= decoded_imm;
+ if (TWO_CYCLE_ALU)
+ alu_wait <= 1;
+ else
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_exec;
+ end
+ ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_out <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ latched_store <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_out <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ latched_rd <= latched_rd | irqregs_offset;
+ latched_store <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ ENABLE_IRQ && instr_retirq: begin
+ eoi <= 0;
+ irq_active <= 0;
+ latched_branch <= 1;
+ latched_store <= 1;
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ ENABLE_IRQ && instr_maskirq: begin
+ latched_store <= 1;
+ reg_out <= irq_mask;
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ irq_mask <= cpuregs_rs1 | MASKED_IRQ;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
+ latched_store <= 1;
+ reg_out <= timer;
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ timer <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ is_lb_lh_lw_lbu_lhu && !instr_trap: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ cpu_state <= cpu_state_ldmem;
+ mem_do_rinst <= 1;
+ end
+ is_slli_srli_srai && !BARREL_SHIFTER: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ reg_sh <= decoded_rs2;
+ cpu_state <= cpu_state_shift;
+ end
+ is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
+ if (TWO_CYCLE_ALU)
+ alu_wait <= 1;
+ else
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_exec;
+ end
+ default: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ if (ENABLE_REGS_DUALPORT) begin
+ `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+ reg_sh <= cpuregs_rs2;
+ reg_op2 <= cpuregs_rs2;
+ dbg_rs2val <= cpuregs_rs2;
+ dbg_rs2val_valid <= 1;
+ (* parallel_case *)
+ case (1'b1)
+ is_sb_sh_sw: begin
+ cpu_state <= cpu_state_stmem;
+ mem_do_rinst <= 1;
+ end
+ is_sll_srl_sra && !BARREL_SHIFTER: begin
+ cpu_state <= cpu_state_shift;
+ end
+ default: begin
+ if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+ alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+ alu_wait <= 1;
+ end else
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_exec;
+ end
+ endcase
+ end else
+ cpu_state <= cpu_state_ld_rs2;
+ end
+ endcase
+ end
+
+ cpu_state_ld_rs2: begin
+ `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+ reg_sh <= cpuregs_rs2;
+ reg_op2 <= cpuregs_rs2;
+ dbg_rs2val <= cpuregs_rs2;
+ dbg_rs2val_valid <= 1;
+
+ (* parallel_case *)
+ case (1'b1)
+ WITH_PCPI && instr_trap: begin
+ pcpi_valid <= 1;
+ if (pcpi_int_ready) begin
+ mem_do_rinst <= 1;
+ pcpi_valid <= 0;
+ reg_out <= pcpi_int_rd;
+ latched_store <= pcpi_int_wr;
+ cpu_state <= cpu_state_fetch;
+ end else
+ if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+ pcpi_valid <= 0;
+ `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+ if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+ next_irq_pending[irq_ebreak] = 1;
+ cpu_state <= cpu_state_fetch;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ end
+ is_sb_sh_sw: begin
+ cpu_state <= cpu_state_stmem;
+ mem_do_rinst <= 1;
+ end
+ is_sll_srl_sra && !BARREL_SHIFTER: begin
+ cpu_state <= cpu_state_shift;
+ end
+ default: begin
+ if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+ alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+ alu_wait <= 1;
+ end else
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_exec;
+ end
+ endcase
+ end
+
+ cpu_state_exec: begin
+ reg_out <= reg_pc + decoded_imm;
+ if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
+ mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
+ alu_wait <= alu_wait_2;
+ end else
+ if (is_beq_bne_blt_bge_bltu_bgeu) begin
+ latched_rd <= 0;
+ latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+ latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+ if (mem_done)
+ cpu_state <= cpu_state_fetch;
+ if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
+ decoder_trigger <= 0;
+ set_mem_do_rinst = 1;
+ end
+ end else begin
+ latched_branch <= instr_jalr;
+ latched_store <= 1;
+ latched_stalu <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ end
+
+ cpu_state_shift: begin
+ latched_store <= 1;
+ if (reg_sh == 0) begin
+ reg_out <= reg_op1;
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_fetch;
+ end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
+ instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
+ instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
+ endcase
+ reg_sh <= reg_sh - 4;
+ end else begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
+ instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
+ instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
+ endcase
+ reg_sh <= reg_sh - 1;
+ end
+ end
+
+ cpu_state_stmem: begin
+ if (ENABLE_TRACE)
+ reg_out <= reg_op2;
+ if (!mem_do_prefetch || mem_done) begin
+ if (!mem_do_wdata) begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_sb: mem_wordsize <= 2;
+ instr_sh: mem_wordsize <= 1;
+ instr_sw: mem_wordsize <= 0;
+ endcase
+ if (ENABLE_TRACE) begin
+ trace_valid <= 1;
+ trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+ end
+ reg_op1 <= reg_op1 + decoded_imm;
+ set_mem_do_wdata = 1;
+ end
+ if (!mem_do_prefetch && mem_done) begin
+ cpu_state <= cpu_state_fetch;
+ decoder_trigger <= 1;
+ decoder_pseudo_trigger <= 1;
+ end
+ end
+ end
+
+ cpu_state_ldmem: begin
+ latched_store <= 1;
+ if (!mem_do_prefetch || mem_done) begin
+ if (!mem_do_rdata) begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_lb || instr_lbu: mem_wordsize <= 2;
+ instr_lh || instr_lhu: mem_wordsize <= 1;
+ instr_lw: mem_wordsize <= 0;
+ endcase
+ latched_is_lu <= is_lbu_lhu_lw;
+ latched_is_lh <= instr_lh;
+ latched_is_lb <= instr_lb;
+ if (ENABLE_TRACE) begin
+ trace_valid <= 1;
+ trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+ end
+ reg_op1 <= reg_op1 + decoded_imm;
+ set_mem_do_rdata = 1;
+ end
+ if (!mem_do_prefetch && mem_done) begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ latched_is_lu: reg_out <= mem_rdata_word;
+ latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
+ latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
+ endcase
+ decoder_trigger <= 1;
+ decoder_pseudo_trigger <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ end
+ end
+ endcase
+
+ if (ENABLE_IRQ) begin
+ next_irq_pending = next_irq_pending | irq;
+ if(ENABLE_IRQ_TIMER && timer)
+ if (timer - 1 == 0)
+ next_irq_pending[irq_timer] = 1;
+ end
+
+ if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
+ if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
+ `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
+ if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+ next_irq_pending[irq_buserror] = 1;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ if (mem_wordsize == 1 && reg_op1[0] != 0) begin
+ `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
+ if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+ next_irq_pending[irq_buserror] = 1;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ end
+ if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
+ `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
+ if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+ next_irq_pending[irq_buserror] = 1;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
+ cpu_state <= cpu_state_trap;
+ end
+
+ if (!resetn || mem_done) begin
+ mem_do_prefetch <= 0;
+ mem_do_rinst <= 0;
+ mem_do_rdata <= 0;
+ mem_do_wdata <= 0;
+ end
+
+ if (set_mem_do_rinst)
+ mem_do_rinst <= 1;
+ if (set_mem_do_rdata)
+ mem_do_rdata <= 1;
+ if (set_mem_do_wdata)
+ mem_do_wdata <= 1;
+
+ irq_pending <= next_irq_pending & ~MASKED_IRQ;
+
+ if (!CATCH_MISALIGN) begin
+ if (COMPRESSED_ISA) begin
+ reg_pc[0] <= 0;
+ reg_next_pc[0] <= 0;
+ end else begin
+ reg_pc[1:0] <= 0;
+ reg_next_pc[1:0] <= 0;
+ end
+ end
+ current_pc = 'bx;
+ end
+
+`ifdef RISCV_FORMAL
+ reg dbg_irq_call;
+ reg dbg_irq_enter;
+ reg [31:0] dbg_irq_ret;
+ always @(posedge clk) begin
+ rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
+ rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
+
+ rvfi_insn <= dbg_insn_opcode;
+ rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
+ rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
+ rvfi_pc_rdata <= dbg_insn_addr;
+ rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
+ rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
+ rvfi_trap <= trap;
+ rvfi_halt <= trap;
+ rvfi_intr <= dbg_irq_enter;
+ rvfi_mode <= 3;
+ rvfi_ixl <= 1;
+
+ if (!resetn) begin
+ dbg_irq_call <= 0;
+ dbg_irq_enter <= 0;
+ end else
+ if (rvfi_valid) begin
+ dbg_irq_call <= 0;
+ dbg_irq_enter <= dbg_irq_call;
+ end else
+ if (irq_state == 1) begin
+ dbg_irq_call <= 1;
+ dbg_irq_ret <= next_pc;
+ end
+
+ if (!resetn) begin
+ rvfi_rd_addr <= 0;
+ rvfi_rd_wdata <= 0;
+ end else
+ if (cpuregs_write && !irq_state) begin
+`ifdef PICORV32_TESTBUG_003
+ rvfi_rd_addr <= latched_rd ^ 1;
+`else
+ rvfi_rd_addr <= latched_rd;
+`endif
+`ifdef PICORV32_TESTBUG_004
+ rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata ^ 1 : 0;
+`else
+ rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
+`endif
+ end else
+ if (rvfi_valid) begin
+ rvfi_rd_addr <= 0;
+ rvfi_rd_wdata <= 0;
+ end
+
+ casez (dbg_insn_opcode)
+ 32'b 0000000_?????_000??_???_?????_0001011: begin // getq
+ rvfi_rs1_addr <= 0;
+ rvfi_rs1_rdata <= 0;
+ end
+ 32'b 0000001_?????_?????_???_000??_0001011: begin // setq
+ rvfi_rd_addr <= 0;
+ rvfi_rd_wdata <= 0;
+ end
+ 32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
+ rvfi_rs1_addr <= 0;
+ rvfi_rs1_rdata <= 0;
+ end
+ endcase
+
+ if (!dbg_irq_call) begin
+ if (dbg_mem_instr) begin
+ rvfi_mem_addr <= 0;
+ rvfi_mem_rmask <= 0;
+ rvfi_mem_wmask <= 0;
+ rvfi_mem_rdata <= 0;
+ rvfi_mem_wdata <= 0;
+ end else
+ if (dbg_mem_valid && dbg_mem_ready) begin
+ rvfi_mem_addr <= dbg_mem_addr;
+ rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
+ rvfi_mem_wmask <= dbg_mem_wstrb;
+ rvfi_mem_rdata <= dbg_mem_rdata;
+ rvfi_mem_wdata <= dbg_mem_wdata;
+ end
+ end
+ end
+
+ always @* begin
+`ifdef PICORV32_TESTBUG_005
+ rvfi_pc_wdata = (dbg_irq_call ? dbg_irq_ret : dbg_insn_addr) ^ 4;
+`else
+ rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
+`endif
+
+ rvfi_csr_mcycle_rmask = 0;
+ rvfi_csr_mcycle_wmask = 0;
+ rvfi_csr_mcycle_rdata = 0;
+ rvfi_csr_mcycle_wdata = 0;
+
+ rvfi_csr_minstret_rmask = 0;
+ rvfi_csr_minstret_wmask = 0;
+ rvfi_csr_minstret_rdata = 0;
+ rvfi_csr_minstret_wdata = 0;
+
+ if (rvfi_valid && rvfi_insn[6:0] == 7'b 1110011 && rvfi_insn[13:12] == 3'b010) begin
+ if (rvfi_insn[31:20] == 12'h C00) begin
+ rvfi_csr_mcycle_rmask = 64'h 0000_0000_FFFF_FFFF;
+ rvfi_csr_mcycle_rdata = {32'h 0000_0000, rvfi_rd_wdata};
+ end
+ if (rvfi_insn[31:20] == 12'h C80) begin
+ rvfi_csr_mcycle_rmask = 64'h FFFF_FFFF_0000_0000;
+ rvfi_csr_mcycle_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
+ end
+ if (rvfi_insn[31:20] == 12'h C02) begin
+ rvfi_csr_minstret_rmask = 64'h 0000_0000_FFFF_FFFF;
+ rvfi_csr_minstret_rdata = {32'h 0000_0000, rvfi_rd_wdata};
+ end
+ if (rvfi_insn[31:20] == 12'h C82) begin
+ rvfi_csr_minstret_rmask = 64'h FFFF_FFFF_0000_0000;
+ rvfi_csr_minstret_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
+ end
+ end
+ end
+`endif
+
+ // Formal Verification
+`ifdef FORMAL
+ reg [3:0] last_mem_nowait;
+ always @(posedge clk)
+ last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
+
+ // stall the memory interface for max 4 cycles
+ restrict property (|last_mem_nowait || mem_ready || !mem_valid);
+
+ // resetn low in first cycle, after that resetn high
+ restrict property (resetn != $initstate);
+
+ // this just makes it much easier to read traces. uncomment as needed.
+ // assume property (mem_valid || !mem_ready);
+
+ reg ok;
+ always @* begin
+ if (resetn) begin
+ // instruction fetches are read-only
+ if (mem_valid && mem_instr)
+ assert (mem_wstrb == 0);
+
+ // cpu_state must be valid
+ ok = 0;
+ if (cpu_state == cpu_state_trap) ok = 1;
+ if (cpu_state == cpu_state_fetch) ok = 1;
+ if (cpu_state == cpu_state_ld_rs1) ok = 1;
+ if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
+ if (cpu_state == cpu_state_exec) ok = 1;
+ if (cpu_state == cpu_state_shift) ok = 1;
+ if (cpu_state == cpu_state_stmem) ok = 1;
+ if (cpu_state == cpu_state_ldmem) ok = 1;
+ assert (ok);
+ end
+ end
+
+ reg last_mem_la_read = 0;
+ reg last_mem_la_write = 0;
+ reg [31:0] last_mem_la_addr;
+ reg [31:0] last_mem_la_wdata;
+ reg [3:0] last_mem_la_wstrb = 0;
+
+ always @(posedge clk) begin
+ last_mem_la_read <= mem_la_read;
+ last_mem_la_write <= mem_la_write;
+ last_mem_la_addr <= mem_la_addr;
+ last_mem_la_wdata <= mem_la_wdata;
+ last_mem_la_wstrb <= mem_la_wstrb;
+
+ if (last_mem_la_read) begin
+ assert(mem_valid);
+ assert(mem_addr == last_mem_la_addr);
+ assert(mem_wstrb == 0);
+ end
+ if (last_mem_la_write) begin
+ assert(mem_valid);
+ assert(mem_addr == last_mem_la_addr);
+ assert(mem_wdata == last_mem_la_wdata);
+ assert(mem_wstrb == last_mem_la_wstrb);
+ end
+ if (mem_la_read || mem_la_write) begin
+ assert(!mem_valid || mem_ready);
+ end
+ end
+`endif
+endmodule
+
+// This is a simple example implementation of PICORV32_REGS.
+// Use the PICORV32_REGS mechanism if you want to use custom
+// memory resources to implement the processor register file.
+// Note that your implementation must match the requirements of
+// the PicoRV32 configuration. (e.g. QREGS, etc)
+module picorv32_regs (
+ input clk, wen,
+ input [5:0] waddr,
+ input [5:0] raddr1,
+ input [5:0] raddr2,
+ input [31:0] wdata,
+ output [31:0] rdata1,
+ output [31:0] rdata2
+);
+ reg [31:0] regs [0:30];
+
+ always @(posedge clk)
+ if (wen) regs[~waddr[4:0]] <= wdata;
+
+ assign rdata1 = regs[~raddr1[4:0]];
+ assign rdata2 = regs[~raddr2[4:0]];
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_mul
+ ***************************************************************/
+
+module picorv32_pcpi_mul #(
+ parameter STEPS_AT_ONCE = 1,
+ parameter CARRY_CHAIN = 4
+) (
+ input clk, resetn,
+
+ input pcpi_valid,
+ input [31:0] pcpi_insn,
+ input [31:0] pcpi_rs1,
+ input [31:0] pcpi_rs2,
+ output reg pcpi_wr,
+ output reg [31:0] pcpi_rd,
+ output reg pcpi_wait,
+ output reg pcpi_ready
+);
+ reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+ wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+ wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+ wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+ wire instr_rs2_signed = |{instr_mulh};
+
+ reg pcpi_wait_q;
+ wire mul_start = pcpi_wait && !pcpi_wait_q;
+
+ always @(posedge clk) begin
+ instr_mul <= 0;
+ instr_mulh <= 0;
+ instr_mulhsu <= 0;
+ instr_mulhu <= 0;
+
+ if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+ case (pcpi_insn[14:12])
+ 3'b000: instr_mul <= 1;
+ 3'b001: instr_mulh <= 1;
+ 3'b010: instr_mulhsu <= 1;
+ 3'b011: instr_mulhu <= 1;
+ endcase
+ end
+
+ pcpi_wait <= instr_any_mul;
+ pcpi_wait_q <= pcpi_wait;
+ end
+
+ reg [63:0] rs1, rs2, rd, rdx;
+ reg [63:0] next_rs1, next_rs2, this_rs2;
+ reg [63:0] next_rd, next_rdx, next_rdt;
+ reg [6:0] mul_counter;
+ reg mul_waiting;
+ reg mul_finish;
+ integer i, j;
+
+ // carry save accumulator
+ always @* begin
+ next_rd = rd;
+ next_rdx = rdx;
+ next_rs1 = rs1;
+ next_rs2 = rs2;
+
+ for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
+ this_rs2 = next_rs1[0] ? next_rs2 : 0;
+ if (CARRY_CHAIN == 0) begin
+ next_rdt = next_rd ^ next_rdx ^ this_rs2;
+ next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
+ next_rd = next_rdt;
+ end else begin
+ next_rdt = 0;
+ for (j = 0; j < 64; j = j + CARRY_CHAIN)
+ {next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
+ next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
+ next_rdx = next_rdt << 1;
+ end
+ next_rs1 = next_rs1 >> 1;
+ next_rs2 = next_rs2 << 1;
+ end
+ end
+
+ always @(posedge clk) begin
+ mul_finish <= 0;
+ if (!resetn) begin
+ mul_waiting <= 1;
+ mul_counter <= 0;
+ end else
+ if (mul_waiting) begin
+ if (instr_rs1_signed)
+ rs1 <= $signed(pcpi_rs1);
+ else
+ rs1 <= $unsigned(pcpi_rs1);
+
+ if (instr_rs2_signed)
+ rs2 <= $signed(pcpi_rs2);
+ else
+ rs2 <= $unsigned(pcpi_rs2);
+
+ rd <= 0;
+ rdx <= 0;
+ mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
+ mul_waiting <= !mul_start;
+ end else begin
+ rd <= next_rd;
+ rdx <= next_rdx;
+ rs1 <= next_rs1;
+ rs2 <= next_rs2;
+
+ mul_counter <= mul_counter - STEPS_AT_ONCE;
+ if (mul_counter[6]) begin
+ mul_finish <= 1;
+ mul_waiting <= 1;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ pcpi_wr <= 0;
+ pcpi_ready <= 0;
+ if (mul_finish && resetn) begin
+ pcpi_wr <= 1;
+ pcpi_ready <= 1;
+ pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
+ end
+ end
+endmodule
+
+module picorv32_pcpi_fast_mul #(
+ parameter EXTRA_MUL_FFS = 0,
+ parameter EXTRA_INSN_FFS = 0,
+ parameter MUL_CLKGATE = 0
+) (
+ input clk, resetn,
+
+ input pcpi_valid,
+ input [31:0] pcpi_insn,
+ input [31:0] pcpi_rs1,
+ input [31:0] pcpi_rs2,
+ output pcpi_wr,
+ output [31:0] pcpi_rd,
+ output pcpi_wait,
+ output pcpi_ready
+);
+ reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+ wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+ wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+ wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+ wire instr_rs2_signed = |{instr_mulh};
+
+ reg shift_out;
+ reg [3:0] active;
+ reg [32:0] rs1, rs2, rs1_q, rs2_q;
+ reg [63:0] rd, rd_q;
+
+ wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
+ reg pcpi_insn_valid_q;
+
+ always @* begin
+ instr_mul = 0;
+ instr_mulh = 0;
+ instr_mulhsu = 0;
+ instr_mulhu = 0;
+
+ if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
+ case (pcpi_insn[14:12])
+ 3'b000: instr_mul = 1;
+ 3'b001: instr_mulh = 1;
+ 3'b010: instr_mulhsu = 1;
+ 3'b011: instr_mulhu = 1;
+ endcase
+ end
+ end
+
+ always @(posedge clk) begin
+ pcpi_insn_valid_q <= pcpi_insn_valid;
+ if (!MUL_CLKGATE || active[0]) begin
+ rs1_q <= rs1;
+ rs2_q <= rs2;
+ end
+ if (!MUL_CLKGATE || active[1]) begin
+ rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
+ end
+ if (!MUL_CLKGATE || active[2]) begin
+ rd_q <= rd;
+ end
+ end
+
+ always @(posedge clk) begin
+ if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
+ if (instr_rs1_signed)
+ rs1 <= $signed(pcpi_rs1);
+ else
+ rs1 <= $unsigned(pcpi_rs1);
+
+ if (instr_rs2_signed)
+ rs2 <= $signed(pcpi_rs2);
+ else
+ rs2 <= $unsigned(pcpi_rs2);
+ active[0] <= 1;
+ end else begin
+ active[0] <= 0;
+ end
+
+ active[3:1] <= active;
+ shift_out <= instr_any_mulh;
+
+ if (!resetn)
+ active <= 0;
+ end
+
+ assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
+ assign pcpi_wait = 0;
+ assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
+`ifdef RISCV_FORMAL_ALTOPS
+ assign pcpi_rd =
+ instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
+ instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
+ instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
+ instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
+`else
+ assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
+`endif
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_div
+ ***************************************************************/
+
+module picorv32_pcpi_div (
+ input clk, resetn,
+
+ input pcpi_valid,
+ input [31:0] pcpi_insn,
+ input [31:0] pcpi_rs1,
+ input [31:0] pcpi_rs2,
+ output reg pcpi_wr,
+ output reg [31:0] pcpi_rd,
+ output reg pcpi_wait,
+ output reg pcpi_ready
+);
+ reg instr_div, instr_divu, instr_rem, instr_remu;
+ wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
+
+ reg pcpi_wait_q;
+ wire start = pcpi_wait && !pcpi_wait_q;
+
+ always @(posedge clk) begin
+ instr_div <= 0;
+ instr_divu <= 0;
+ instr_rem <= 0;
+ instr_remu <= 0;
+
+ if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+ case (pcpi_insn[14:12])
+ 3'b100: instr_div <= 1;
+ 3'b101: instr_divu <= 1;
+ 3'b110: instr_rem <= 1;
+ 3'b111: instr_remu <= 1;
+ endcase
+ end
+
+ pcpi_wait <= instr_any_div_rem && resetn;
+ pcpi_wait_q <= pcpi_wait && resetn;
+ end
+
+ reg [31:0] dividend;
+ reg [62:0] divisor;
+ reg [31:0] quotient;
+ reg [31:0] quotient_msk;
+ reg running;
+ reg outsign;
+
+ always @(posedge clk) begin
+ pcpi_ready <= 0;
+ pcpi_wr <= 0;
+ pcpi_rd <= 'bx;
+
+ if (!resetn) begin
+ running <= 0;
+ end else
+ if (start) begin
+ running <= 1;
+ dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
+ divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
+ outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
+ quotient <= 0;
+ quotient_msk <= 1 << 31;
+ end else
+ if (!quotient_msk && running) begin
+ running <= 0;
+ pcpi_ready <= 1;
+ pcpi_wr <= 1;
+`ifdef RISCV_FORMAL_ALTOPS
+ case (1)
+ instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
+ instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
+ instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
+ instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
+ endcase
+`else
+ if (instr_div || instr_divu)
+ pcpi_rd <= outsign ? -quotient : quotient;
+ else
+ pcpi_rd <= outsign ? -dividend : dividend;
+`endif
+ end else begin
+ if (divisor <= dividend) begin
+ dividend <= dividend - divisor;
+ quotient <= quotient | quotient_msk;
+ end
+ divisor <= divisor >> 1;
+`ifdef RISCV_FORMAL_ALTOPS
+ quotient_msk <= quotient_msk >> 5;
+`else
+ quotient_msk <= quotient_msk >> 1;
+`endif
+ end
+ end
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi
+ ***************************************************************/
+
+module picorv32_axi #(
+ parameter [ 0:0] ENABLE_COUNTERS = 1,
+ parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+ parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+ parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+ parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+ parameter [ 0:0] BARREL_SHIFTER = 0,
+ parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+ parameter [ 0:0] TWO_CYCLE_ALU = 0,
+ parameter [ 0:0] COMPRESSED_ISA = 0,
+ parameter [ 0:0] CATCH_MISALIGN = 1,
+ parameter [ 0:0] CATCH_ILLINSN = 1,
+ parameter [ 0:0] ENABLE_PCPI = 0,
+ parameter [ 0:0] ENABLE_MUL = 0,
+ parameter [ 0:0] ENABLE_FAST_MUL = 0,
+ parameter [ 0:0] ENABLE_DIV = 0,
+ parameter [ 0:0] ENABLE_IRQ = 0,
+ parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+ parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+ parameter [ 0:0] ENABLE_TRACE = 0,
+ parameter [ 0:0] REGS_INIT_ZERO = 0,
+ parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+ parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+ parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+ parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+ parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+ input clk, resetn,
+ output trap,
+
+ // AXI4-lite master memory interface
+
+ output mem_axi_awvalid,
+ input mem_axi_awready,
+ output [31:0] mem_axi_awaddr,
+ output [ 2:0] mem_axi_awprot,
+
+ output mem_axi_wvalid,
+ input mem_axi_wready,
+ output [31:0] mem_axi_wdata,
+ output [ 3:0] mem_axi_wstrb,
+
+ input mem_axi_bvalid,
+ output mem_axi_bready,
+
+ output mem_axi_arvalid,
+ input mem_axi_arready,
+ output [31:0] mem_axi_araddr,
+ output [ 2:0] mem_axi_arprot,
+
+ input mem_axi_rvalid,
+ output mem_axi_rready,
+ input [31:0] mem_axi_rdata,
+
+ // Pico Co-Processor Interface (PCPI)
+ output pcpi_valid,
+ output [31:0] pcpi_insn,
+ output [31:0] pcpi_rs1,
+ output [31:0] pcpi_rs2,
+ input pcpi_wr,
+ input [31:0] pcpi_rd,
+ input pcpi_wait,
+ input pcpi_ready,
+
+ // IRQ interface
+ input [31:0] irq,
+ output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+ output rvfi_valid,
+ output [63:0] rvfi_order,
+ output [31:0] rvfi_insn,
+ output rvfi_trap,
+ output rvfi_halt,
+ output rvfi_intr,
+ output [ 4:0] rvfi_rs1_addr,
+ output [ 4:0] rvfi_rs2_addr,
+ output [31:0] rvfi_rs1_rdata,
+ output [31:0] rvfi_rs2_rdata,
+ output [ 4:0] rvfi_rd_addr,
+ output [31:0] rvfi_rd_wdata,
+ output [31:0] rvfi_pc_rdata,
+ output [31:0] rvfi_pc_wdata,
+ output [31:0] rvfi_mem_addr,
+ output [ 3:0] rvfi_mem_rmask,
+ output [ 3:0] rvfi_mem_wmask,
+ output [31:0] rvfi_mem_rdata,
+ output [31:0] rvfi_mem_wdata,
+`endif
+
+ // Trace Interface
+ output trace_valid,
+ output [35:0] trace_data
+);
+ wire mem_valid;
+ wire [31:0] mem_addr;
+ wire [31:0] mem_wdata;
+ wire [ 3:0] mem_wstrb;
+ wire mem_instr;
+ wire mem_ready;
+ wire [31:0] mem_rdata;
+
+ picorv32_axi_adapter axi_adapter (
+ .clk (clk ),
+ .resetn (resetn ),
+ .mem_axi_awvalid(mem_axi_awvalid),
+ .mem_axi_awready(mem_axi_awready),
+ .mem_axi_awaddr (mem_axi_awaddr ),
+ .mem_axi_awprot (mem_axi_awprot ),
+ .mem_axi_wvalid (mem_axi_wvalid ),
+ .mem_axi_wready (mem_axi_wready ),
+ .mem_axi_wdata (mem_axi_wdata ),
+ .mem_axi_wstrb (mem_axi_wstrb ),
+ .mem_axi_bvalid (mem_axi_bvalid ),
+ .mem_axi_bready (mem_axi_bready ),
+ .mem_axi_arvalid(mem_axi_arvalid),
+ .mem_axi_arready(mem_axi_arready),
+ .mem_axi_araddr (mem_axi_araddr ),
+ .mem_axi_arprot (mem_axi_arprot ),
+ .mem_axi_rvalid (mem_axi_rvalid ),
+ .mem_axi_rready (mem_axi_rready ),
+ .mem_axi_rdata (mem_axi_rdata ),
+ .mem_valid (mem_valid ),
+ .mem_instr (mem_instr ),
+ .mem_ready (mem_ready ),
+ .mem_addr (mem_addr ),
+ .mem_wdata (mem_wdata ),
+ .mem_wstrb (mem_wstrb ),
+ .mem_rdata (mem_rdata )
+ );
+
+ picorv32 #(
+ .ENABLE_COUNTERS (ENABLE_COUNTERS ),
+ .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
+ .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
+ .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+ .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
+ .BARREL_SHIFTER (BARREL_SHIFTER ),
+ .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
+ .TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
+ .COMPRESSED_ISA (COMPRESSED_ISA ),
+ .CATCH_MISALIGN (CATCH_MISALIGN ),
+ .CATCH_ILLINSN (CATCH_ILLINSN ),
+ .ENABLE_PCPI (ENABLE_PCPI ),
+ .ENABLE_MUL (ENABLE_MUL ),
+ .ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
+ .ENABLE_DIV (ENABLE_DIV ),
+ .ENABLE_IRQ (ENABLE_IRQ ),
+ .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
+ .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
+ .ENABLE_TRACE (ENABLE_TRACE ),
+ .REGS_INIT_ZERO (REGS_INIT_ZERO ),
+ .MASKED_IRQ (MASKED_IRQ ),
+ .LATCHED_IRQ (LATCHED_IRQ ),
+ .PROGADDR_RESET (PROGADDR_RESET ),
+ .PROGADDR_IRQ (PROGADDR_IRQ ),
+ .STACKADDR (STACKADDR )
+ ) picorv32_core (
+ .clk (clk ),
+ .resetn (resetn),
+ .trap (trap ),
+
+ .mem_valid(mem_valid),
+ .mem_addr (mem_addr ),
+ .mem_wdata(mem_wdata),
+ .mem_wstrb(mem_wstrb),
+ .mem_instr(mem_instr),
+ .mem_ready(mem_ready),
+ .mem_rdata(mem_rdata),
+
+ .pcpi_valid(pcpi_valid),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_wr ),
+ .pcpi_rd (pcpi_rd ),
+ .pcpi_wait (pcpi_wait ),
+ .pcpi_ready(pcpi_ready),
+
+ .irq(irq),
+ .eoi(eoi),
+
+`ifdef RISCV_FORMAL
+ .rvfi_valid (rvfi_valid ),
+ .rvfi_order (rvfi_order ),
+ .rvfi_insn (rvfi_insn ),
+ .rvfi_trap (rvfi_trap ),
+ .rvfi_halt (rvfi_halt ),
+ .rvfi_intr (rvfi_intr ),
+ .rvfi_rs1_addr (rvfi_rs1_addr ),
+ .rvfi_rs2_addr (rvfi_rs2_addr ),
+ .rvfi_rs1_rdata(rvfi_rs1_rdata),
+ .rvfi_rs2_rdata(rvfi_rs2_rdata),
+ .rvfi_rd_addr (rvfi_rd_addr ),
+ .rvfi_rd_wdata (rvfi_rd_wdata ),
+ .rvfi_pc_rdata (rvfi_pc_rdata ),
+ .rvfi_pc_wdata (rvfi_pc_wdata ),
+ .rvfi_mem_addr (rvfi_mem_addr ),
+ .rvfi_mem_rmask(rvfi_mem_rmask),
+ .rvfi_mem_wmask(rvfi_mem_wmask),
+ .rvfi_mem_rdata(rvfi_mem_rdata),
+ .rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+ .trace_valid(trace_valid),
+ .trace_data (trace_data)
+ );
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi_adapter
+ ***************************************************************/
+
+module picorv32_axi_adapter (
+ input clk, resetn,
+
+ // AXI4-lite master memory interface
+
+ output mem_axi_awvalid,
+ input mem_axi_awready,
+ output [31:0] mem_axi_awaddr,
+ output [ 2:0] mem_axi_awprot,
+
+ output mem_axi_wvalid,
+ input mem_axi_wready,
+ output [31:0] mem_axi_wdata,
+ output [ 3:0] mem_axi_wstrb,
+
+ input mem_axi_bvalid,
+ output mem_axi_bready,
+
+ output mem_axi_arvalid,
+ input mem_axi_arready,
+ output [31:0] mem_axi_araddr,
+ output [ 2:0] mem_axi_arprot,
+
+ input mem_axi_rvalid,
+ output mem_axi_rready,
+ input [31:0] mem_axi_rdata,
+
+ // Native PicoRV32 memory interface
+
+ input mem_valid,
+ input mem_instr,
+ output mem_ready,
+ input [31:0] mem_addr,
+ input [31:0] mem_wdata,
+ input [ 3:0] mem_wstrb,
+ output [31:0] mem_rdata
+);
+ reg ack_awvalid;
+ reg ack_arvalid;
+ reg ack_wvalid;
+ reg xfer_done;
+
+ assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
+ assign mem_axi_awaddr = mem_addr;
+ assign mem_axi_awprot = 0;
+
+ assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
+ assign mem_axi_araddr = mem_addr;
+ assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
+
+ assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
+ assign mem_axi_wdata = mem_wdata;
+ assign mem_axi_wstrb = mem_wstrb;
+
+ assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
+ assign mem_axi_bready = mem_valid && |mem_wstrb;
+ assign mem_axi_rready = mem_valid && !mem_wstrb;
+ assign mem_rdata = mem_axi_rdata;
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ ack_awvalid <= 0;
+ end else begin
+ xfer_done <= mem_valid && mem_ready;
+ if (mem_axi_awready && mem_axi_awvalid)
+ ack_awvalid <= 1;
+ if (mem_axi_arready && mem_axi_arvalid)
+ ack_arvalid <= 1;
+ if (mem_axi_wready && mem_axi_wvalid)
+ ack_wvalid <= 1;
+ if (xfer_done || !mem_valid) begin
+ ack_awvalid <= 0;
+ ack_arvalid <= 0;
+ ack_wvalid <= 0;
+ end
+ end
+ end
+endmodule
+
+
+/***************************************************************
+ * picorv32_wb
+ ***************************************************************/
+
+module picorv32_wb #(
+ parameter [ 0:0] ENABLE_COUNTERS = 1,
+ parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+ parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+ parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+ parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+ parameter [ 0:0] BARREL_SHIFTER = 0,
+ parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+ parameter [ 0:0] TWO_CYCLE_ALU = 0,
+ parameter [ 0:0] COMPRESSED_ISA = 0,
+ parameter [ 0:0] CATCH_MISALIGN = 1,
+ parameter [ 0:0] CATCH_ILLINSN = 1,
+ parameter [ 0:0] ENABLE_PCPI = 0,
+ parameter [ 0:0] ENABLE_MUL = 0,
+ parameter [ 0:0] ENABLE_FAST_MUL = 0,
+ parameter [ 0:0] ENABLE_DIV = 0,
+ parameter [ 0:0] ENABLE_IRQ = 0,
+ parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+ parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+ parameter [ 0:0] ENABLE_TRACE = 0,
+ parameter [ 0:0] REGS_INIT_ZERO = 0,
+ parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+ parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+ parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+ parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+ parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+ output trap,
+
+ // Wishbone interfaces
+ input wb_rst_i,
+ input wb_clk_i,
+
+ output reg [31:0] wbm_adr_o,
+ output reg [31:0] wbm_dat_o,
+ input [31:0] wbm_dat_i,
+ output reg wbm_we_o,
+ output reg [3:0] wbm_sel_o,
+ output reg wbm_stb_o,
+ input wbm_ack_i,
+ output reg wbm_cyc_o,
+
+ // Pico Co-Processor Interface (PCPI)
+ output pcpi_valid,
+ output [31:0] pcpi_insn,
+ output [31:0] pcpi_rs1,
+ output [31:0] pcpi_rs2,
+ input pcpi_wr,
+ input [31:0] pcpi_rd,
+ input pcpi_wait,
+ input pcpi_ready,
+
+ // IRQ interface
+ input [31:0] irq,
+ output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+ output rvfi_valid,
+ output [63:0] rvfi_order,
+ output [31:0] rvfi_insn,
+ output rvfi_trap,
+ output rvfi_halt,
+ output rvfi_intr,
+ output [ 4:0] rvfi_rs1_addr,
+ output [ 4:0] rvfi_rs2_addr,
+ output [31:0] rvfi_rs1_rdata,
+ output [31:0] rvfi_rs2_rdata,
+ output [ 4:0] rvfi_rd_addr,
+ output [31:0] rvfi_rd_wdata,
+ output [31:0] rvfi_pc_rdata,
+ output [31:0] rvfi_pc_wdata,
+ output [31:0] rvfi_mem_addr,
+ output [ 3:0] rvfi_mem_rmask,
+ output [ 3:0] rvfi_mem_wmask,
+ output [31:0] rvfi_mem_rdata,
+ output [31:0] rvfi_mem_wdata,
+`endif
+
+ // Trace Interface
+ output trace_valid,
+ output [35:0] trace_data,
+
+ output mem_instr
+);
+ wire mem_valid;
+ wire [31:0] mem_addr;
+ wire [31:0] mem_wdata;
+ wire [ 3:0] mem_wstrb;
+ reg mem_ready;
+ reg [31:0] mem_rdata;
+
+ wire clk;
+ wire resetn;
+
+ assign clk = wb_clk_i;
+ assign resetn = ~wb_rst_i;
+
+ picorv32 #(
+ .ENABLE_COUNTERS (ENABLE_COUNTERS ),
+ .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
+ .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
+ .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+ .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
+ .BARREL_SHIFTER (BARREL_SHIFTER ),
+ .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
+ .TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
+ .COMPRESSED_ISA (COMPRESSED_ISA ),
+ .CATCH_MISALIGN (CATCH_MISALIGN ),
+ .CATCH_ILLINSN (CATCH_ILLINSN ),
+ .ENABLE_PCPI (ENABLE_PCPI ),
+ .ENABLE_MUL (ENABLE_MUL ),
+ .ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
+ .ENABLE_DIV (ENABLE_DIV ),
+ .ENABLE_IRQ (ENABLE_IRQ ),
+ .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
+ .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
+ .ENABLE_TRACE (ENABLE_TRACE ),
+ .REGS_INIT_ZERO (REGS_INIT_ZERO ),
+ .MASKED_IRQ (MASKED_IRQ ),
+ .LATCHED_IRQ (LATCHED_IRQ ),
+ .PROGADDR_RESET (PROGADDR_RESET ),
+ .PROGADDR_IRQ (PROGADDR_IRQ ),
+ .STACKADDR (STACKADDR )
+ ) picorv32_core (
+ .clk (clk ),
+ .resetn (resetn),
+ .trap (trap ),
+
+ .mem_valid(mem_valid),
+ .mem_addr (mem_addr ),
+ .mem_wdata(mem_wdata),
+ .mem_wstrb(mem_wstrb),
+ .mem_instr(mem_instr),
+ .mem_ready(mem_ready),
+ .mem_rdata(mem_rdata),
+
+ .pcpi_valid(pcpi_valid),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_wr ),
+ .pcpi_rd (pcpi_rd ),
+ .pcpi_wait (pcpi_wait ),
+ .pcpi_ready(pcpi_ready),
+
+ .irq(irq),
+ .eoi(eoi),
+
+`ifdef RISCV_FORMAL
+ .rvfi_valid (rvfi_valid ),
+ .rvfi_order (rvfi_order ),
+ .rvfi_insn (rvfi_insn ),
+ .rvfi_trap (rvfi_trap ),
+ .rvfi_halt (rvfi_halt ),
+ .rvfi_intr (rvfi_intr ),
+ .rvfi_rs1_addr (rvfi_rs1_addr ),
+ .rvfi_rs2_addr (rvfi_rs2_addr ),
+ .rvfi_rs1_rdata(rvfi_rs1_rdata),
+ .rvfi_rs2_rdata(rvfi_rs2_rdata),
+ .rvfi_rd_addr (rvfi_rd_addr ),
+ .rvfi_rd_wdata (rvfi_rd_wdata ),
+ .rvfi_pc_rdata (rvfi_pc_rdata ),
+ .rvfi_pc_wdata (rvfi_pc_wdata ),
+ .rvfi_mem_addr (rvfi_mem_addr ),
+ .rvfi_mem_rmask(rvfi_mem_rmask),
+ .rvfi_mem_wmask(rvfi_mem_wmask),
+ .rvfi_mem_rdata(rvfi_mem_rdata),
+ .rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+ .trace_valid(trace_valid),
+ .trace_data (trace_data)
+ );
+ // Wishbone Controller
+ localparam IDLE = 2'b00;
+ localparam WBSTART = 2'b01;
+ localparam WBEND = 2'b10;
+
+ reg [1:0] state;
+
+ wire we;
+ assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
+
+ always @(posedge wb_clk_i) begin
+ if (wb_rst_i) begin
+ wbm_adr_o <= 0;
+ wbm_dat_o <= 0;
+ wbm_we_o <= 0;
+ wbm_sel_o <= 0;
+ wbm_stb_o <= 0;
+ wbm_cyc_o <= 0;
+ state <= IDLE;
+ end else begin
+ case (state)
+ IDLE: begin
+ if (mem_valid) begin
+ wbm_adr_o <= mem_addr;
+ wbm_dat_o <= mem_wdata;
+ wbm_we_o <= we;
+ wbm_sel_o <= mem_wstrb;
+
+ wbm_stb_o <= 1'b1;
+ wbm_cyc_o <= 1'b1;
+ state <= WBSTART;
+ end else begin
+ mem_ready <= 1'b0;
+
+ wbm_stb_o <= 1'b0;
+ wbm_cyc_o <= 1'b0;
+ wbm_we_o <= 1'b0;
+ end
+ end
+ WBSTART:begin
+ if (wbm_ack_i) begin
+ mem_rdata <= wbm_dat_i;
+ mem_ready <= 1'b1;
+
+ state <= WBEND;
+
+ wbm_stb_o <= 1'b0;
+ wbm_cyc_o <= 1'b0;
+ wbm_we_o <= 1'b0;
+ end
+ end
+ WBEND: begin
+ mem_ready <= 1'b0;
+
+ state <= IDLE;
+ end
+ default:
+ state <= IDLE;
+ endcase
+ end
+ end
+endmodule
+`default_nettype wire
diff --git a/ip/third_party/picorv32_wb/simpleuart.v b/ip/third_party/picorv32_wb/simpleuart.v
new file mode 100644
index 0000000..4fe9f0c
--- /dev/null
+++ b/ip/third_party/picorv32_wb/simpleuart.v
@@ -0,0 +1,223 @@
+`default_nettype none
+/*
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+module simpleuart_wb # (
+ parameter BASE_ADR = 32'h 2000_0000,
+ parameter CLK_DIV = 8'h00,
+ parameter DATA = 8'h04,
+ parameter CONFIG = 8'h08
+) (
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input [31:0] wb_adr_i, // (verify): input address was originaly 22 bits , why ? (max number of words ?)
+ input [31:0] wb_dat_i,
+ input [3:0] wb_sel_i,
+ input wb_we_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+
+ output wb_ack_o,
+ output [31:0] wb_dat_o,
+
+ output uart_enabled,
+ output ser_tx,
+ input ser_rx
+
+);
+ wire [31:0] simpleuart_reg_div_do;
+ wire [31:0] simpleuart_reg_dat_do;
+ wire [31:0] simpleuart_reg_cfg_do;
+ wire reg_dat_wait;
+
+ wire resetn = ~wb_rst_i;
+ wire valid = wb_stb_i && wb_cyc_i;
+ wire simpleuart_reg_div_sel = valid && (wb_adr_i == (BASE_ADR | CLK_DIV));
+ wire simpleuart_reg_dat_sel = valid && (wb_adr_i == (BASE_ADR | DATA));
+ wire simpleuart_reg_cfg_sel = valid && (wb_adr_i == (BASE_ADR | CONFIG));
+
+ wire [3:0] reg_div_we = simpleuart_reg_div_sel ? (wb_sel_i & {4{wb_we_i}}): 4'b 0000;
+ wire reg_dat_we = simpleuart_reg_dat_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0; // simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0
+ wire reg_cfg_we = simpleuart_reg_cfg_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0;
+
+ wire [31:0] mem_wdata = wb_dat_i;
+ wire reg_dat_re = simpleuart_reg_dat_sel && !wb_sel_i && ~wb_we_i; // read_enable
+
+ assign wb_dat_o = simpleuart_reg_div_sel ? simpleuart_reg_div_do:
+ simpleuart_reg_cfg_sel ? simpleuart_reg_cfg_do:
+ simpleuart_reg_dat_do;
+ assign wb_ack_o = (simpleuart_reg_div_sel || simpleuart_reg_dat_sel
+ || simpleuart_reg_cfg_sel) && (!reg_dat_wait);
+
+ simpleuart simpleuart (
+ .clk (wb_clk_i),
+ .resetn (resetn),
+
+ .ser_tx (ser_tx),
+ .ser_rx (ser_rx),
+ .enabled (uart_enabled),
+
+ .reg_div_we (reg_div_we),
+ .reg_div_di (mem_wdata),
+ .reg_div_do (simpleuart_reg_div_do),
+
+ .reg_cfg_we (reg_cfg_we),
+ .reg_cfg_di (mem_wdata),
+ .reg_cfg_do (simpleuart_reg_cfg_do),
+
+ .reg_dat_we (reg_dat_we),
+ .reg_dat_re (reg_dat_re),
+ .reg_dat_di (mem_wdata),
+ .reg_dat_do (simpleuart_reg_dat_do),
+ .reg_dat_wait(reg_dat_wait)
+ );
+
+endmodule
+
+module simpleuart (
+ input clk,
+ input resetn,
+
+ output enabled,
+ output ser_tx,
+ input ser_rx,
+
+ input [3:0] reg_div_we,
+ input [31:0] reg_div_di,
+ output [31:0] reg_div_do,
+
+ input reg_cfg_we,
+ input [31:0] reg_cfg_di,
+ output [31:0] reg_cfg_do,
+
+ input reg_dat_we,
+ input reg_dat_re,
+ input [31:0] reg_dat_di,
+ output [31:0] reg_dat_do,
+ output reg_dat_wait
+);
+ reg [31:0] cfg_divider;
+ reg enabled;
+
+ reg [3:0] recv_state;
+ reg [31:0] recv_divcnt;
+ reg [7:0] recv_pattern;
+ reg [7:0] recv_buf_data;
+ reg recv_buf_valid;
+
+ reg [9:0] send_pattern;
+ reg [3:0] send_bitcnt;
+ reg [31:0] send_divcnt;
+ reg send_dummy;
+
+ wire reg_ena_do;
+
+ assign reg_div_do = cfg_divider;
+ assign reg_ena_do = {31'd0, enabled};
+
+ assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
+ assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0;
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ cfg_divider <= 1;
+ enabled <= 1'b0;
+ end else begin
+ if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0];
+ if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8];
+ if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
+ if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
+ if (reg_cfg_we) enabled <= reg_div_di[0];
+ end
+ end
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ recv_state <= 0;
+ recv_divcnt <= 0;
+ recv_pattern <= 0;
+ recv_buf_data <= 0;
+ recv_buf_valid <= 0;
+ end else begin
+ recv_divcnt <= recv_divcnt + 1;
+ if (reg_dat_re)
+ recv_buf_valid <= 0;
+ case (recv_state)
+ 0: begin
+ if (!ser_rx && enabled)
+ recv_state <= 1;
+ recv_divcnt <= 0;
+ end
+ 1: begin
+ if (2*recv_divcnt > cfg_divider) begin
+ recv_state <= 2;
+ recv_divcnt <= 0;
+ end
+ end
+ 10: begin
+ if (recv_divcnt > cfg_divider) begin
+ recv_buf_data <= recv_pattern;
+ recv_buf_valid <= 1;
+ recv_state <= 0;
+ end
+ end
+ default: begin
+ if (recv_divcnt > cfg_divider) begin
+ recv_pattern <= {ser_rx, recv_pattern[7:1]};
+ recv_state <= recv_state + 1;
+ recv_divcnt <= 0;
+ end
+ end
+ endcase
+ end
+ end
+
+ assign ser_tx = send_pattern[0];
+
+ always @(posedge clk) begin
+ if (reg_div_we && enabled)
+ send_dummy <= 1;
+ send_divcnt <= send_divcnt + 1;
+ if (!resetn) begin
+ send_pattern <= ~0;
+ send_bitcnt <= 0;
+ send_divcnt <= 0;
+ send_dummy <= 1;
+ end else begin
+ if (send_dummy && !send_bitcnt) begin
+ send_pattern <= ~0;
+ send_bitcnt <= 15;
+ send_divcnt <= 0;
+ send_dummy <= 0;
+ end else
+ if (reg_dat_we && !send_bitcnt) begin
+ send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
+ send_bitcnt <= 10;
+ send_divcnt <= 0;
+ end else
+ if (send_divcnt > cfg_divider && send_bitcnt) begin
+ send_pattern <= {1'b1, send_pattern[9:1]};
+ send_bitcnt <= send_bitcnt - 1;
+ send_divcnt <= 0;
+ end
+ end
+ end
+endmodule
+`default_nettype wire
diff --git a/ip/third_party/picorv32_wb/spimemio.v b/ip/third_party/picorv32_wb/spimemio.v
new file mode 100644
index 0000000..dc37126
--- /dev/null
+++ b/ip/third_party/picorv32_wb/spimemio.v
@@ -0,0 +1,743 @@
+`default_nettype none
+/*
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+module spimemio_wb (
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input [31:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ input [3:0] wb_sel_i,
+ input wb_we_i,
+ input wb_cyc_i,
+
+ input wb_flash_stb_i,
+ input wb_cfg_stb_i,
+
+ output wb_flash_ack_o,
+ output wb_cfg_ack_o,
+
+ output [31:0] wb_flash_dat_o,
+ output [31:0] wb_cfg_dat_o,
+
+ input pass_thru,
+ input pass_thru_csb,
+ input pass_thru_sck,
+ input pass_thru_sdi,
+ output pass_thru_sdo,
+
+ output flash_csb,
+ output flash_clk,
+
+ output flash_csb_oeb,
+ output flash_clk_oeb,
+
+ output flash_io0_oeb,
+ output flash_io1_oeb,
+ output flash_io2_oeb,
+ output flash_io3_oeb,
+
+ output flash_csb_ieb,
+ output flash_clk_ieb,
+
+ output flash_io0_ieb,
+ output flash_io1_ieb,
+ output flash_io2_ieb,
+ output flash_io3_ieb,
+
+ output flash_io0_do,
+ output flash_io1_do,
+ output flash_io2_do,
+ output flash_io3_do,
+
+ input flash_io0_di,
+ input flash_io1_di,
+ input flash_io2_di,
+ input flash_io3_di
+
+);
+ wire spimem_ready;
+ wire [23:0] mem_addr;
+ wire [31:0] spimem_rdata;
+ wire [31:0] spimemio_cfgreg_do;
+ wire [3:0] cfgreg_we;
+ wire spimemio_cfgreg_sel;
+ wire valid;
+ wire resetn;
+
+ assign resetn = ~wb_rst_i;
+ assign valid = wb_cyc_i && wb_flash_stb_i;
+ assign wb_flash_ack_o = spimem_ready;
+ assign wb_cfg_ack_o = spimemio_cfgreg_sel;
+
+ assign mem_addr = wb_adr_i[23:0];
+ assign spimemio_cfgreg_sel = wb_cyc_i && wb_cfg_stb_i;
+
+ assign cfgreg_we = spimemio_cfgreg_sel ? wb_sel_i & {4{wb_we_i}} : 4'b 0000;
+ assign wb_flash_dat_o = spimem_rdata;
+ assign wb_cfg_dat_o = spimemio_cfgreg_do;
+
+ spimemio spimemio (
+ .clk (wb_clk_i),
+ .resetn (resetn),
+ .valid (valid),
+ .ready (spimem_ready),
+ .addr (mem_addr),
+ .rdata (spimem_rdata),
+
+ .flash_csb (flash_csb),
+ .flash_clk (flash_clk),
+
+ .flash_csb_oeb (flash_csb_oeb),
+ .flash_clk_oeb (flash_clk_oeb),
+
+ .flash_io0_oeb (flash_io0_oeb),
+ .flash_io1_oeb (flash_io1_oeb),
+ .flash_io2_oeb (flash_io2_oeb),
+ .flash_io3_oeb (flash_io3_oeb),
+
+ .flash_csb_ieb (flash_csb_ieb),
+ .flash_clk_ieb (flash_clk_ieb),
+
+ .flash_io0_ieb (flash_io0_ieb),
+ .flash_io1_ieb (flash_io1_ieb),
+ .flash_io2_ieb (flash_io2_ieb),
+ .flash_io3_ieb (flash_io3_ieb),
+
+ .flash_io0_do (flash_io0_do),
+ .flash_io1_do (flash_io1_do),
+ .flash_io2_do (flash_io2_do),
+ .flash_io3_do (flash_io3_do),
+
+ .flash_io0_di (flash_io0_di),
+ .flash_io1_di (flash_io1_di),
+ .flash_io2_di (flash_io2_di),
+ .flash_io3_di (flash_io3_di),
+
+ .cfgreg_we(cfgreg_we),
+ .cfgreg_di(wb_dat_i),
+ .cfgreg_do(spimemio_cfgreg_do),
+
+ .pass_thru(pass_thru),
+ .pass_thru_csb(pass_thru_csb),
+ .pass_thru_sck(pass_thru_sck),
+ .pass_thru_sdi(pass_thru_sdi),
+ .pass_thru_sdo(pass_thru_sdo)
+ );
+
+endmodule
+
+module spimemio (
+ input clk, resetn,
+
+ input valid,
+ output ready,
+ input [23:0] addr,
+ output reg [31:0] rdata,
+
+ output flash_csb,
+ output flash_clk,
+
+ output flash_csb_oeb,
+ output flash_clk_oeb,
+
+ output flash_io0_oeb,
+ output flash_io1_oeb,
+ output flash_io2_oeb,
+ output flash_io3_oeb,
+
+ output flash_csb_ieb,
+ output flash_clk_ieb,
+
+ output flash_io0_ieb,
+ output flash_io1_ieb,
+ output flash_io2_ieb,
+ output flash_io3_ieb,
+
+ output flash_io0_do,
+ output flash_io1_do,
+ output flash_io2_do,
+ output flash_io3_do,
+
+ input flash_io0_di,
+ input flash_io1_di,
+ input flash_io2_di,
+ input flash_io3_di,
+
+ input [3:0] cfgreg_we,
+ input [31:0] cfgreg_di,
+ output [31:0] cfgreg_do,
+
+ input pass_thru,
+ input pass_thru_csb,
+ input pass_thru_sck,
+ input pass_thru_sdi,
+ output pass_thru_sdo
+);
+ reg xfer_resetn;
+ reg din_valid;
+ wire din_ready;
+ reg [7:0] din_data;
+ reg [3:0] din_tag;
+ reg din_cont;
+ reg din_qspi;
+ reg din_ddr;
+ reg din_rd;
+
+ wire dout_valid;
+ wire [7:0] dout_data;
+ wire [3:0] dout_tag;
+
+ reg [23:0] buffer;
+
+ reg [23:0] rd_addr;
+ reg rd_valid;
+ reg rd_wait;
+ reg rd_inc;
+
+ assign ready = valid && (addr == rd_addr) && rd_valid;
+ wire jump = valid && !ready && (addr != rd_addr+4) && rd_valid;
+
+ reg softreset;
+
+ reg config_en; // cfgreg[31]
+ reg config_ddr; // cfgreg[22]
+ reg config_qspi; // cfgreg[21]
+ reg config_cont; // cfgreg[20]
+ reg [3:0] config_dummy; // cfgreg[19:16]
+ reg [3:0] config_oe; // cfgreg[11:8]
+ reg config_csb; // cfgreg[5]
+ reg config_clk; // cfgref[4]
+ reg [3:0] config_do; // cfgreg[3:0]
+
+ assign cfgreg_do[31] = config_en;
+ assign cfgreg_do[30:23] = 0;
+ assign cfgreg_do[22] = config_ddr;
+ assign cfgreg_do[21] = config_qspi;
+ assign cfgreg_do[20] = config_cont;
+ assign cfgreg_do[19:16] = config_dummy;
+ assign cfgreg_do[15:12] = 0;
+ assign cfgreg_do[11:8] = {~flash_io3_oeb, ~flash_io2_oeb, ~flash_io1_oeb, ~flash_io0_oeb};
+ assign cfgreg_do[7:6] = 0;
+ assign cfgreg_do[5] = flash_csb;
+ assign cfgreg_do[4] = flash_clk;
+ assign cfgreg_do[3:0] = {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
+
+ always @(posedge clk) begin
+ softreset <= !config_en || cfgreg_we;
+ if (!resetn) begin
+ softreset <= 1;
+ config_en <= 1;
+ config_csb <= 0;
+ config_clk <= 0;
+ config_oe <= 0;
+ config_do <= 0;
+ config_ddr <= 0;
+ config_qspi <= 0;
+ config_cont <= 0;
+ config_dummy <= 8;
+ end else begin
+ if (cfgreg_we[0]) begin
+ config_csb <= cfgreg_di[5];
+ config_clk <= cfgreg_di[4];
+ config_do <= cfgreg_di[3:0];
+ end
+ if (cfgreg_we[1]) begin
+ config_oe <= cfgreg_di[11:8];
+ end
+ if (cfgreg_we[2]) begin
+ config_ddr <= cfgreg_di[22];
+ config_qspi <= cfgreg_di[21];
+ config_cont <= cfgreg_di[20];
+ config_dummy <= cfgreg_di[19:16];
+ end
+ if (cfgreg_we[3]) begin
+ config_en <= cfgreg_di[31];
+ end
+ end
+ end
+
+ wire xfer_csb;
+ wire xfer_clk;
+
+ wire xfer_io0_oe;
+ wire xfer_io1_oe;
+ wire xfer_io2_oe;
+ wire xfer_io3_oe;
+
+ wire xfer_io0_do;
+ wire xfer_io1_do;
+ wire xfer_io2_do;
+ wire xfer_io3_do;
+
+ reg xfer_io0_90;
+ reg xfer_io1_90;
+ reg xfer_io2_90;
+ reg xfer_io3_90;
+
+ always @(negedge clk) begin
+ xfer_io0_90 <= xfer_io0_do;
+ xfer_io1_90 <= xfer_io1_do;
+ xfer_io2_90 <= xfer_io2_do;
+ xfer_io3_90 <= xfer_io3_do;
+ end
+
+ wire pass_thru;
+ wire pass_thru_csb;
+ wire pass_thru_sck;
+ wire pass_thru_sdi;
+ wire pass_thru_sdo;
+
+ assign flash_csb = (pass_thru) ? pass_thru_csb : (config_en ? xfer_csb : config_csb);
+ assign flash_clk = (pass_thru) ? pass_thru_sck : (config_en ? xfer_clk : config_clk);
+
+ assign flash_csb_oeb = (pass_thru) ? 1'b0 : (~resetn ? 1'b1 : 1'b0);
+ assign flash_clk_oeb = (pass_thru) ? 1'b0 : (~resetn ? 1'b1 : 1'b0);
+
+ assign flash_io0_oeb = pass_thru ? 1'b0 : ~resetn ? 1'b1 : (config_en ? ~xfer_io0_oe : ~config_oe[0]);
+ assign flash_io1_oeb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? ~xfer_io1_oe : ~config_oe[1]);
+ assign flash_io2_oeb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? ~xfer_io2_oe : ~config_oe[2]);
+ assign flash_io3_oeb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? ~xfer_io3_oe : ~config_oe[3]);
+ assign flash_csb_ieb = 1'b1; /* Always disabled */
+ assign flash_clk_ieb = 1'b1; /* Always disabled */
+
+ assign flash_io0_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io0_oe : config_oe[0]);
+ assign flash_io1_ieb = pass_thru ? 1'b0 : ~resetn ? 1'b1 : (config_en ? xfer_io1_oe : config_oe[1]);
+ assign flash_io2_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io2_oe : config_oe[2]);
+ assign flash_io3_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io3_oe : config_oe[3]);
+
+ assign flash_io0_do = pass_thru ? pass_thru_sdi : (config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0]);
+ assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1];
+ assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];
+ assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];
+ assign pass_thru_sdo = pass_thru ? flash_io1_di : 1'b0;
+
+ wire xfer_dspi = din_ddr && !din_qspi;
+ wire xfer_ddr = din_ddr && din_qspi;
+
+ spimemio_xfer xfer (
+ .clk (clk ),
+ .resetn (resetn ),
+ .xfer_resetn (xfer_resetn ),
+ .din_valid (din_valid ),
+ .din_ready (din_ready ),
+ .din_data (din_data ),
+ .din_tag (din_tag ),
+ .din_cont (din_cont ),
+ .din_dspi (xfer_dspi ),
+ .din_qspi (din_qspi ),
+ .din_ddr (xfer_ddr ),
+ .din_rd (din_rd ),
+ .dout_valid (dout_valid ),
+ .dout_data (dout_data ),
+ .dout_tag (dout_tag ),
+ .flash_csb (xfer_csb ),
+ .flash_clk (xfer_clk ),
+ .flash_io0_oe (xfer_io0_oe ),
+ .flash_io1_oe (xfer_io1_oe ),
+ .flash_io2_oe (xfer_io2_oe ),
+ .flash_io3_oe (xfer_io3_oe ),
+ .flash_io0_do (xfer_io0_do ),
+ .flash_io1_do (xfer_io1_do ),
+ .flash_io2_do (xfer_io2_do ),
+ .flash_io3_do (xfer_io3_do ),
+ .flash_io0_di (flash_io0_di),
+ .flash_io1_di (flash_io1_di),
+ .flash_io2_di (flash_io2_di),
+ .flash_io3_di (flash_io3_di)
+ );
+
+ reg [3:0] state;
+
+ always @(posedge clk) begin
+ xfer_resetn <= 1;
+ din_valid <= 0;
+
+ if (!resetn || softreset) begin
+ state <= 0;
+ xfer_resetn <= 0;
+ rd_valid <= 0;
+ din_tag <= 0;
+ din_cont <= 0;
+ din_qspi <= 0;
+ din_ddr <= 0;
+ din_rd <= 0;
+ end else begin
+ if (dout_valid && dout_tag == 1) buffer[ 7: 0] <= dout_data;
+ if (dout_valid && dout_tag == 2) buffer[15: 8] <= dout_data;
+ if (dout_valid && dout_tag == 3) buffer[23:16] <= dout_data;
+ if (dout_valid && dout_tag == 4) begin
+ rdata <= {dout_data, buffer};
+ rd_addr <= rd_inc ? rd_addr + 4 : addr;
+ rd_valid <= 1;
+ rd_wait <= rd_inc;
+ rd_inc <= 1;
+ end
+
+ if (valid)
+ rd_wait <= 0;
+
+ case (state)
+ 0: begin
+ din_valid <= 1;
+ din_data <= 8'h ff;
+ din_tag <= 0;
+ if (din_ready) begin
+ din_valid <= 0;
+ state <= 1;
+ end
+ end
+ 1: begin
+ if (dout_valid) begin
+ xfer_resetn <= 0;
+ state <= 2;
+ end
+ end
+ 2: begin
+ din_valid <= 1;
+ din_data <= 8'h ab;
+ din_tag <= 0;
+ if (din_ready) begin
+ din_valid <= 0;
+ state <= 3;
+ end
+ end
+ 3: begin
+ if (dout_valid) begin
+ xfer_resetn <= 0;
+ state <= 4;
+ end
+ end
+ 4: begin
+ rd_inc <= 0;
+ din_valid <= 1;
+ din_tag <= 0;
+ case ({config_ddr, config_qspi})
+ 2'b11: din_data <= 8'h ED;
+ 2'b01: din_data <= 8'h EB;
+ 2'b10: din_data <= 8'h BB;
+ 2'b00: din_data <= 8'h 03;
+ endcase
+ if (din_ready) begin
+ din_valid <= 0;
+ state <= 5;
+ end
+ end
+ 5: begin
+ if (valid && !ready) begin
+ din_valid <= 1;
+ din_tag <= 0;
+ din_data <= addr[23:16];
+ din_qspi <= config_qspi;
+ din_ddr <= config_ddr;
+ if (din_ready) begin
+ din_valid <= 0;
+ state <= 6;
+ end
+ end
+ end
+ 6: begin
+ din_valid <= 1;
+ din_tag <= 0;
+ din_data <= addr[15:8];
+ if (din_ready) begin
+ din_valid <= 0;
+ state <= 7;
+ end
+ end
+ 7: begin
+ din_valid <= 1;
+ din_tag <= 0;
+ din_data <= addr[7:0];
+ if (din_ready) begin
+ din_valid <= 0;
+ din_data <= 0;
+ state <= config_qspi || config_ddr ? 8 : 9;
+ end
+ end
+ 8: begin
+ din_valid <= 1;
+ din_tag <= 0;
+ din_data <= config_cont ? 8'h A5 : 8'h FF;
+ if (din_ready) begin
+ din_rd <= 1;
+ din_data <= config_dummy;
+ din_valid <= 0;
+ state <= 9;
+ end
+ end
+ 9: begin
+ din_valid <= 1;
+ din_tag <= 1;
+ if (din_ready) begin
+ din_valid <= 0;
+ state <= 10;
+ end
+ end
+ 10: begin
+ din_valid <= 1;
+ din_data <= 8'h 00;
+ din_tag <= 2;
+ if (din_ready) begin
+ din_valid <= 0;
+ state <= 11;
+ end
+ end
+ 11: begin
+ din_valid <= 1;
+ din_tag <= 3;
+ if (din_ready) begin
+ din_valid <= 0;
+ state <= 12;
+ end
+ end
+ 12: begin
+ if (!rd_wait || valid) begin
+ din_valid <= 1;
+ din_tag <= 4;
+ if (din_ready) begin
+ din_valid <= 0;
+ state <= 9;
+ end
+ end
+ end
+ endcase
+
+ if (jump) begin
+ rd_inc <= 0;
+ rd_valid <= 0;
+ xfer_resetn <= 0;
+ if (config_cont) begin
+ state <= 5;
+ end else begin
+ state <= 4;
+ din_qspi <= 0;
+ din_ddr <= 0;
+ end
+ din_rd <= 0;
+ end
+ end
+ end
+endmodule
+
+module spimemio_xfer (
+ input clk, resetn, xfer_resetn,
+
+ input din_valid,
+ output din_ready,
+ input [7:0] din_data,
+ input [3:0] din_tag,
+ input din_cont,
+ input din_dspi,
+ input din_qspi,
+ input din_ddr,
+ input din_rd,
+
+ output dout_valid,
+ output [7:0] dout_data,
+ output [3:0] dout_tag,
+
+ output reg flash_csb,
+ output reg flash_clk,
+
+ output reg flash_io0_oe,
+ output reg flash_io1_oe,
+ output reg flash_io2_oe,
+ output reg flash_io3_oe,
+
+ output reg flash_io0_do,
+ output reg flash_io1_do,
+ output reg flash_io2_do,
+ output reg flash_io3_do,
+
+ input flash_io0_di,
+ input flash_io1_di,
+ input flash_io2_di,
+ input flash_io3_di
+);
+ reg [7:0] obuffer;
+ reg [7:0] ibuffer;
+
+ reg [3:0] count;
+ reg [3:0] dummy_count;
+
+ reg xfer_cont;
+ reg xfer_dspi;
+ reg xfer_qspi;
+ reg xfer_ddr;
+ reg xfer_ddr_q;
+ reg xfer_rd;
+ reg [3:0] xfer_tag;
+ reg [3:0] xfer_tag_q;
+
+ reg [7:0] next_obuffer;
+ reg [7:0] next_ibuffer;
+ reg [3:0] next_count;
+
+ reg fetch;
+ reg next_fetch;
+ reg last_fetch;
+
+ always @(posedge clk) begin
+ xfer_ddr_q <= xfer_ddr;
+ xfer_tag_q <= xfer_tag;
+ end
+
+ assign din_ready = din_valid && xfer_resetn && next_fetch;
+
+ assign dout_valid = (xfer_ddr_q ? fetch && !last_fetch : next_fetch && !fetch) && xfer_resetn;
+ assign dout_data = ibuffer;
+ assign dout_tag = xfer_tag_q;
+
+ always @* begin
+ flash_io0_oe = 0;
+ flash_io1_oe = 0;
+ flash_io2_oe = 0;
+ flash_io3_oe = 0;
+
+ flash_io0_do = 0;
+ flash_io1_do = 0;
+ flash_io2_do = 0;
+ flash_io3_do = 0;
+
+ next_obuffer = obuffer;
+ next_ibuffer = ibuffer;
+ next_count = count;
+ next_fetch = 0;
+
+ if (dummy_count == 0) begin
+ casez ({xfer_ddr, xfer_qspi, xfer_dspi})
+ 3'b 000: begin
+ flash_io0_oe = 1;
+ flash_io0_do = obuffer[7];
+
+ if (flash_clk) begin
+ next_obuffer = {obuffer[6:0], 1'b 0};
+ next_count = count - |count;
+ end else begin
+ next_ibuffer = {ibuffer[6:0], flash_io1_di};
+ end
+
+ next_fetch = (next_count == 0);
+ end
+ 3'b 01?: begin
+ flash_io0_oe = !xfer_rd;
+ flash_io1_oe = !xfer_rd;
+ flash_io2_oe = !xfer_rd;
+ flash_io3_oe = !xfer_rd;
+
+ flash_io0_do = obuffer[4];
+ flash_io1_do = obuffer[5];
+ flash_io2_do = obuffer[6];
+ flash_io3_do = obuffer[7];
+
+ if (flash_clk) begin
+ next_obuffer = {obuffer[3:0], 4'b 0000};
+ next_count = count - {|count, 2'b00};
+ end else begin
+ next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
+ end
+
+ next_fetch = (next_count == 0);
+ end
+ 3'b 11?: begin
+ flash_io0_oe = !xfer_rd;
+ flash_io1_oe = !xfer_rd;
+ flash_io2_oe = !xfer_rd;
+ flash_io3_oe = !xfer_rd;
+
+ flash_io0_do = obuffer[4];
+ flash_io1_do = obuffer[5];
+ flash_io2_do = obuffer[6];
+ flash_io3_do = obuffer[7];
+
+ next_obuffer = {obuffer[3:0], 4'b 0000};
+ next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
+ next_count = count - {|count, 2'b00};
+
+ next_fetch = (next_count == 0);
+ end
+ 3'b ??1: begin
+ flash_io0_oe = !xfer_rd;
+ flash_io1_oe = !xfer_rd;
+
+ flash_io0_do = obuffer[6];
+ flash_io1_do = obuffer[7];
+
+ if (flash_clk) begin
+ next_obuffer = {obuffer[5:0], 2'b 00};
+ next_count = count - {|count, 1'b0};
+ end else begin
+ next_ibuffer = {ibuffer[5:0], flash_io1_di, flash_io0_di};
+ end
+
+ next_fetch = (next_count == 0);
+ end
+ endcase
+ end
+ end
+
+ always @(posedge clk) begin
+ if (!resetn || !xfer_resetn) begin
+ fetch <= 1;
+ last_fetch <= 1;
+ flash_csb <= 1;
+ flash_clk <= 0;
+ count <= 0;
+ dummy_count <= 0;
+ xfer_tag <= 0;
+ xfer_cont <= 0;
+ xfer_dspi <= 0;
+ xfer_qspi <= 0;
+ xfer_ddr <= 0;
+ xfer_rd <= 0;
+ end else begin
+ fetch <= next_fetch;
+ last_fetch <= xfer_ddr ? fetch : 1;
+ if (dummy_count) begin
+ flash_clk <= !flash_clk && !flash_csb;
+ dummy_count <= dummy_count - flash_clk;
+ end else
+ if (count) begin
+ flash_clk <= !flash_clk && !flash_csb;
+ obuffer <= next_obuffer;
+ ibuffer <= next_ibuffer;
+ count <= next_count;
+ end
+ if (din_valid && din_ready) begin
+ flash_csb <= 0;
+ flash_clk <= 0;
+
+ count <= 8;
+ dummy_count <= din_rd ? din_data : 0;
+ obuffer <= din_data;
+
+ xfer_tag <= din_tag;
+ xfer_cont <= din_cont;
+ xfer_dspi <= din_dspi;
+ xfer_qspi <= din_qspi;
+ xfer_ddr <= din_ddr;
+ xfer_rd <= din_rd;
+ end
+ end
+ end
+endmodule
+
+`default_nettype wire
diff --git a/ip/third_party/picorv32_wb/storage_bridge_wb.v b/ip/third_party/picorv32_wb/storage_bridge_wb.v
new file mode 100644
index 0000000..bf70052
--- /dev/null
+++ b/ip/third_party/picorv32_wb/storage_bridge_wb.v
@@ -0,0 +1,97 @@
+`default_nettype none
+module storage_bridge_wb (
+ // MGMT_AREA R/W WB Interface
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input [31:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ input [3:0] wb_sel_i,
+ input wb_we_i,
+ input wb_cyc_i,
+ input [1:0] wb_stb_i,
+ output reg [1:0] wb_ack_o,
+ output reg [31:0] wb_rw_dat_o,
+
+ // MGMT_AREA RO WB Interface
+ output [31:0] wb_ro_dat_o,
+
+ // MGMT Area native memory interface
+ output [`RAM_BLOCKS-1:0] mgmt_ena,
+ output [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask,
+ output [`RAM_BLOCKS-1:0] mgmt_wen,
+ output [7:0] mgmt_addr,
+ output [31:0] mgmt_wdata,
+ input [(`RAM_BLOCKS*32)-1:0] mgmt_rdata,
+
+ // MGMT_AREA RO Interface
+ output mgmt_ena_ro,
+ output [7:0] mgmt_addr_ro,
+ input [31:0] mgmt_rdata_ro
+);
+ parameter [(`RAM_BLOCKS*24)-1:0] RW_BLOCKS_ADR = {
+ {24'h 10_0000},
+ {24'h 00_0000}
+ };
+
+ parameter [23:0] RO_BLOCKS_ADR = {
+ {24'h 20_0000}
+ };
+
+ parameter ADR_MASK = 24'h FF_0000;
+
+ wire [1:0] valid;
+ wire [1:0] wen;
+ wire [7:0] wen_mask;
+
+ assign valid = {2{wb_cyc_i}} & wb_stb_i;
+ assign wen = wb_we_i & valid;
+ assign wen_mask = wb_sel_i & {{4{wen[1]}}, {4{wen[0]}}};
+
+ // Ack generation
+ reg [1:0] wb_ack_read;
+
+ always @(posedge wb_clk_i) begin
+ if (wb_rst_i == 1'b 1) begin
+ wb_ack_read <= 2'b0;
+ wb_ack_o <= 2'b0;
+ end else begin
+ wb_ack_o <= wb_we_i? (valid & ~wb_ack_o): wb_ack_read;
+ wb_ack_read <= (valid & ~wb_ack_o) & ~wb_ack_read;
+ end
+ end
+
+ // Address decoding
+ wire [`RAM_BLOCKS-1: 0] rw_sel;
+ wire ro_sel;
+
+ genvar iS;
+ generate
+ for (iS = 0; iS < `RAM_BLOCKS; iS = iS + 1) begin
+ assign rw_sel[iS] =
+ ((wb_adr_i[23:0] & ADR_MASK) == RW_BLOCKS_ADR[(iS+1)*24-1:iS*24]);
+ end
+ endgenerate
+
+ // Management R/W interface
+ assign mgmt_ena = valid[0] ? ~rw_sel : {`RAM_BLOCKS{1'b1}};
+ assign mgmt_wen = ~{`RAM_BLOCKS{wen[0]}};
+ assign mgmt_wen_mask = {`RAM_BLOCKS{wen_mask[3:0]}};
+ assign mgmt_addr = wb_adr_i[9:2];
+ assign mgmt_wdata = wb_dat_i[31:0];
+
+ integer i;
+ always @(*) begin
+ wb_rw_dat_o = {32{1'b0}};
+ for (i=0; i<(`RAM_BLOCKS*32); i=i+1)
+ wb_rw_dat_o[i%32] = wb_rw_dat_o[i%32] | (rw_sel[i/32] & mgmt_rdata[i]);
+ end
+
+ // RO Interface
+ assign ro_sel = ((wb_adr_i[23:0] & ADR_MASK) == RO_BLOCKS_ADR);
+ assign mgmt_ena_ro = valid[1] ? ~ro_sel : 1'b1;
+ assign mgmt_addr_ro = wb_adr_i[9:2];
+ assign wb_ro_dat_o = mgmt_rdata_ro;
+
+endmodule
+`default_nettype wire
diff --git a/ip/third_party/picorv32_wb/wb_intercon.v b/ip/third_party/picorv32_wb/wb_intercon.v
new file mode 100644
index 0000000..6c3ab52
--- /dev/null
+++ b/ip/third_party/picorv32_wb/wb_intercon.v
@@ -0,0 +1,59 @@
+`default_nettype none
+module wb_intercon #(
+ parameter DW = 32, // Data Width
+ parameter AW = 32, // Address Width
+ parameter NS = 6 // Number of Slaves
+) (
+ // Master Interface
+ input [AW-1:0] wbm_adr_i,
+ input wbm_stb_i,
+
+ output reg [DW-1:0] wbm_dat_o,
+ output wbm_ack_o,
+
+ // Slave Interface
+ input [NS*DW-1:0] wbs_dat_i,
+ input [NS-1:0] wbs_ack_i,
+ output [NS-1:0] wbs_stb_o
+);
+ parameter [NS*AW-1:0] ADR_MASK = { // Page & Sub-page bits
+ {8'hFF, {24{1'b0}} },
+ {8'hFF, {24{1'b0}} },
+ {8'hFF, {24{1'b0}} },
+ {8'hFF, {24{1'b0}} },
+ {8'hFF, {24{1'b0}} },
+ {8'hFF, {24{1'b0}} }
+ };
+ parameter [NS*AW-1:0] SLAVE_ADR = {
+ { 32'h2800_0000 }, // Flash Configuration Register
+ { 32'h2200_0000 }, // System Control
+ { 32'h2100_0000 }, // GPIOs
+ { 32'h2000_0000 }, // UART
+ { 32'h1000_0000 }, // Flash
+ { 32'h0000_0000 } // RAM
+ };
+
+ wire [NS-1: 0] slave_sel;
+
+ // Address decoder
+ genvar iS;
+ generate
+ for (iS = 0; iS < NS; iS = iS + 1) begin
+ assign slave_sel[iS] =
+ ((wbm_adr_i & ADR_MASK[(iS+1)*AW-1:iS*AW]) == SLAVE_ADR[(iS+1)*AW-1:iS*AW]);
+ end
+ endgenerate
+
+ // Data-out Assignment
+ assign wbm_ack_o = |(wbs_ack_i & slave_sel);
+ assign wbs_stb_o = {NS{wbm_stb_i}} & slave_sel;
+
+ integer i;
+ always @(*) begin
+ wbm_dat_o = {DW{1'b0}};
+ for (i=0; i<(NS*DW); i=i+1)
+ wbm_dat_o[i%DW] = wbm_dat_o[i%DW] | (slave_sel[i/DW] & wbs_dat_i[i]);
+ end
+
+endmodule
+`default_nettype wire
diff --git a/ip/third_party/verilog-wishbone/.gitignore b/ip/third_party/verilog-wishbone/.gitignore
new file mode 100644
index 0000000..964df4d
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/.gitignore
@@ -0,0 +1,6 @@
+*~
+*.lxt
+*.pyc
+*.vvp
+*.kate-swp
+
diff --git a/ip/third_party/verilog-wishbone/.travis.yml b/ip/third_party/verilog-wishbone/.travis.yml
new file mode 100644
index 0000000..15f9a3c
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/.travis.yml
@@ -0,0 +1,15 @@
+language: python
+python:
+ - "3.6"
+before_install:
+ - export d=`pwd`
+ - export PYTHON_EXE=`which python`
+ - sudo apt-get update -qq
+ - sudo apt-get install -y iverilog
+ - git clone https://github.com/jandecaluwe/myhdl.git
+ - cd $d/myhdl && sudo $PYTHON_EXE setup.py install
+ - cd $d/myhdl/cosimulation/icarus && make && sudo install -m 0755 -D ./myhdl.vpi /usr/lib/x86_64-linux-gnu/ivl/myhdl.vpi
+ - cd $d
+script:
+ - cd tb && py.test
+
diff --git a/ip/third_party/verilog-wishbone/AUTHORS b/ip/third_party/verilog-wishbone/AUTHORS
new file mode 100644
index 0000000..7dab2b3
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/AUTHORS
@@ -0,0 +1 @@
+Alex Forencich <alex@alexforencich.com>
diff --git a/ip/third_party/verilog-wishbone/COPYING b/ip/third_party/verilog-wishbone/COPYING
new file mode 100644
index 0000000..a8a83f7
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/COPYING
@@ -0,0 +1,21 @@
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+
diff --git a/ip/third_party/verilog-wishbone/README b/ip/third_party/verilog-wishbone/README
new file mode 120000
index 0000000..42061c0
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/README
@@ -0,0 +1 @@
+README.md
\ No newline at end of file
diff --git a/ip/third_party/verilog-wishbone/README.md b/ip/third_party/verilog-wishbone/README.md
new file mode 100644
index 0000000..95d42a0
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/README.md
@@ -0,0 +1,94 @@
+# Verilog Wishbone Components Readme
+
+For more information and updates: http://alexforencich.com/wiki/en/verilog/wishbone/start
+
+GitHub repository: https://github.com/alexforencich/verilog-wishbone
+
+## Introduction
+
+Collection of Wishbone bus components. Most components are fully
+parametrizable in interface widths. Includes full MyHDL testbench with
+intelligent bus cosimulation endpoints.
+
+## Documentation
+
+### arbiter module
+
+General-purpose parametrizable arbiter. Supports priority and round-robin
+arbitration. Supports blocking until request release or acknowledge.
+
+### axis_wb_master module
+
+AXI Stream Wishbone master. Intended to be used to bridge a streaming
+or packet-based protocol (serial, ethernet, etc.) to a Wishbone bus.
+
+### priority_encoder module
+
+Parametrizable priority encoder.
+
+### wb_adapter module
+
+Width adapter module to bridge wishbone buses of differing widths. The module
+is parametrizable, but their are certain restrictions. First, the bus word
+widths must be identical (same data bus width per select line). Second, the
+bus widths must be related by an integer multiple (e.g. 2 words and 6 words,
+but not 4 words and 6 words).
+
+### wb_arbiter_N module
+
+Parametrizable arbiter module to enable sharing between multiple masters.
+
+Can be generated with arbitrary port counts with wb_arbiter.py.
+
+### wb_async_reg module
+
+Asynchronous register module for clock domain crossing with parametrizable
+data and address interface widths. Uses internal synchronization to pass
+wishbone bus cycles across clock domain boundaries.
+
+### wb_dp_ram module
+
+Dual-port, dual-clock RAM with parametrizable data and address interface
+widths.
+
+### wb_mux_N module
+
+Wishbone multiplexer with parametrizable data and address interface widths.
+
+Can be generated with arbitrary port counts with wb_mux.py.
+
+### wb_ram module
+
+RAM with parametrizable data and address interface widths.
+
+### wb_reg module
+
+Synchronous register with parametrizable data and address interface widths.
+Registers all wishbone signals. Used to improve timing for long routes.
+
+### Source Files
+
+ arbiter.v : General-purpose parametrizable arbiter
+ axis_wb_master.v : AXI Stream Wishbone master
+ priority_encoder.v : Parametrizable priority encoder
+ wb_adapter.v : Parametrizable bus width adapter
+ wb_arbiter.py : Arbiter generator
+ wb_arbiter_2.py : 2 port WB arbiter
+ wb_async_reg.v : Asynchronous register
+ wb_dp_ram.v : Dual port RAM
+ wb_mux.py : WB mux generator
+ wb_mux_2.v : 2 port WB mux
+ wb_ram.v : Single port RAM
+ wb_reg.v : Register
+
+## Testing
+
+Running the included testbenches requires MyHDL and Icarus Verilog. Make sure
+that myhdl.vpi is installed properly for cosimulation to work correctly. The
+testbenches can be run with a Python test runner like nose or py.test, or the
+individual test scripts can be run with python directly.
+
+### Testbench Files
+
+ tb/axis_ep.py : MyHDL AXI Stream endpoints
+ tb/wb.py : MyHDL Wishbone master model and RAM model
diff --git a/ip/third_party/verilog-wishbone/rtl/arbiter.v b/ip/third_party/verilog-wishbone/rtl/arbiter.v
new file mode 100644
index 0000000..d2b94f5
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/arbiter.v
@@ -0,0 +1,153 @@
+/*
+
+Copyright (c) 2014-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Arbiter module
+ */
+module arbiter #
+(
+ parameter PORTS = 4,
+ // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+ parameter TYPE = "PRIORITY",
+ // block type: "NONE", "REQUEST", "ACKNOWLEDGE"
+ parameter BLOCK = "NONE",
+ // LSB priority: "LOW", "HIGH"
+ parameter LSB_PRIORITY = "LOW"
+)
+(
+ input wire clk,
+ input wire rst,
+
+ input wire [PORTS-1:0] request,
+ input wire [PORTS-1:0] acknowledge,
+
+ output wire [PORTS-1:0] grant,
+ output wire grant_valid,
+ output wire [$clog2(PORTS)-1:0] grant_encoded
+);
+
+reg [PORTS-1:0] grant_reg = 0, grant_next;
+reg grant_valid_reg = 0, grant_valid_next;
+reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
+
+assign grant_valid = grant_valid_reg;
+assign grant = grant_reg;
+assign grant_encoded = grant_encoded_reg;
+
+wire request_valid;
+wire [$clog2(PORTS)-1:0] request_index;
+wire [PORTS-1:0] request_mask;
+
+priority_encoder #(
+ .WIDTH(PORTS),
+ .LSB_PRIORITY(LSB_PRIORITY)
+)
+priority_encoder_inst (
+ .input_unencoded(request),
+ .output_valid(request_valid),
+ .output_encoded(request_index),
+ .output_unencoded(request_mask)
+);
+
+reg [PORTS-1:0] mask_reg = 0, mask_next;
+
+wire masked_request_valid;
+wire [$clog2(PORTS)-1:0] masked_request_index;
+wire [PORTS-1:0] masked_request_mask;
+
+priority_encoder #(
+ .WIDTH(PORTS),
+ .LSB_PRIORITY(LSB_PRIORITY)
+)
+priority_encoder_masked (
+ .input_unencoded(request & mask_reg),
+ .output_valid(masked_request_valid),
+ .output_encoded(masked_request_index),
+ .output_unencoded(masked_request_mask)
+);
+
+always @* begin
+ grant_next = 0;
+ grant_valid_next = 0;
+ grant_encoded_next = 0;
+ mask_next = mask_reg;
+
+ if (BLOCK == "REQUEST" && grant_reg & request) begin
+ // granted request still asserted; hold it
+ grant_valid_next = grant_valid_reg;
+ grant_next = grant_reg;
+ grant_encoded_next = grant_encoded_reg;
+ end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(grant_reg & acknowledge)) begin
+ // granted request not yet acknowledged; hold it
+ grant_valid_next = grant_valid_reg;
+ grant_next = grant_reg;
+ grant_encoded_next = grant_encoded_reg;
+ end else if (request_valid) begin
+ if (TYPE == "PRIORITY") begin
+ grant_valid_next = 1;
+ grant_next = request_mask;
+ grant_encoded_next = request_index;
+ end else if (TYPE == "ROUND_ROBIN") begin
+ if (masked_request_valid) begin
+ grant_valid_next = 1;
+ grant_next = masked_request_mask;
+ grant_encoded_next = masked_request_index;
+ if (LSB_PRIORITY == "LOW") begin
+ mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
+ end else begin
+ mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
+ end
+ end else begin
+ grant_valid_next = 1;
+ grant_next = request_mask;
+ grant_encoded_next = request_index;
+ if (LSB_PRIORITY == "LOW") begin
+ mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
+ end else begin
+ mask_next = {PORTS{1'b1}} << (request_index + 1);
+ end
+ end
+ end
+ end
+end
+
+always @(posedge clk) begin
+ if (rst) begin
+ grant_reg <= 0;
+ grant_valid_reg <= 0;
+ grant_encoded_reg <= 0;
+ mask_reg <= 0;
+ end else begin
+ grant_reg <= grant_next;
+ grant_valid_reg <= grant_valid_next;
+ grant_encoded_reg <= grant_encoded_next;
+ mask_reg <= mask_next;
+ end
+end
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/axis_wb_master.v b/ip/third_party/verilog-wishbone/rtl/axis_wb_master.v
new file mode 100644
index 0000000..6d25f99
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/axis_wb_master.v
@@ -0,0 +1,562 @@
+/*
+
+Copyright (c) 2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI stream wishbone master
+ */
+module axis_wb_master #
+(
+ parameter IMPLICIT_FRAMING = 0, // implicit framing (ignore tlast, look for start)
+ parameter COUNT_SIZE = 16, // size of word count register
+ parameter AXIS_DATA_WIDTH = 8, // width of AXI data bus
+ parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8), // width of AXI bus tkeep signal
+ parameter WB_DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter WB_ADDR_WIDTH = 32, // width of address bus in bits
+ parameter WB_SELECT_WIDTH = (WB_DATA_WIDTH/8), // width of word select bus (1, 2, 4, or 8)
+ parameter READ_REQ = 8'hA1, // read requst type
+ parameter WRITE_REQ = 8'hA2, // write requst type
+ parameter READ_RESP = 8'hA3, // read response type
+ parameter WRITE_RESP = 8'hA4 // write response type
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * AXI input
+ */
+ input wire [AXIS_DATA_WIDTH-1:0] input_axis_tdata,
+ input wire [AXIS_KEEP_WIDTH-1:0] input_axis_tkeep,
+ input wire input_axis_tvalid,
+ output wire input_axis_tready,
+ input wire input_axis_tlast,
+ input wire input_axis_tuser,
+
+ /*
+ * AXI output
+ */
+ output wire [AXIS_DATA_WIDTH-1:0] output_axis_tdata,
+ output wire [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep,
+ output wire output_axis_tvalid,
+ input wire output_axis_tready,
+ output wire output_axis_tlast,
+ output wire output_axis_tuser,
+
+ /*
+ * Wishbone interface
+ */
+ output wire [WB_ADDR_WIDTH-1:0] wb_adr_o, // ADR_O() address
+ input wire [WB_DATA_WIDTH-1:0] wb_dat_i, // DAT_I() data in
+ output wire [WB_DATA_WIDTH-1:0] wb_dat_o, // DAT_O() data out
+ output wire wb_we_o, // WE_O write enable output
+ output wire [WB_SELECT_WIDTH-1:0] wb_sel_o, // SEL_O() select output
+ output wire wb_stb_o, // STB_O strobe output
+ input wire wb_ack_i, // ACK_I acknowledge input
+ input wire wb_err_i, // ERR_I error input
+ output wire wb_cyc_o, // CYC_O cycle output
+
+ /*
+ * Status
+ */
+ output wire busy
+);
+
+// bus word width
+localparam AXIS_DATA_WORD_SIZE = AXIS_DATA_WIDTH / AXIS_KEEP_WIDTH;
+
+// for interfaces that are more than one word wide, disable address lines
+parameter WB_VALID_ADDR_WIDTH = WB_ADDR_WIDTH - $clog2(WB_SELECT_WIDTH);
+// width of data port in words (1, 2, 4, or 8)
+parameter WB_WORD_WIDTH = WB_SELECT_WIDTH;
+// size of words (8, 16, 32, or 64 bits)
+parameter WB_WORD_SIZE = WB_DATA_WIDTH/WB_WORD_WIDTH;
+
+parameter WORD_PART_ADDR_WIDTH = $clog2(WB_WORD_SIZE/AXIS_DATA_WORD_SIZE);
+
+parameter ADDR_WIDTH_ADJ = WB_ADDR_WIDTH+WORD_PART_ADDR_WIDTH;
+
+parameter COUNT_WORD_WIDTH = (COUNT_SIZE+AXIS_DATA_WORD_SIZE-1)/AXIS_DATA_WORD_SIZE;
+parameter ADDR_WORD_WIDTH = (ADDR_WIDTH_ADJ+AXIS_DATA_WORD_SIZE-1)/AXIS_DATA_WORD_SIZE;
+
+// bus width assertions
+initial begin
+ if (AXIS_KEEP_WIDTH * AXIS_DATA_WORD_SIZE != AXIS_DATA_WIDTH) begin
+ $error("Error: AXI data width not evenly divisble");
+ $finish;
+ end
+
+ if (WB_WORD_WIDTH * WB_WORD_SIZE != WB_DATA_WIDTH) begin
+ $error("Error: WB data width not evenly divisble");
+ $finish;
+ end
+
+ if (2**$clog2(WB_WORD_WIDTH) != WB_WORD_WIDTH) begin
+ $error("Error: WB word width must be even power of two");
+ $finish;
+ end
+
+ if (AXIS_DATA_WORD_SIZE*2**$clog2(WB_WORD_SIZE/AXIS_DATA_WORD_SIZE) != WB_WORD_SIZE) begin
+ $error("Error: WB word size must be a power of two multiple of the AXI word size");
+ $finish;
+ end
+
+ if (AXIS_KEEP_WIDTH > 1) begin
+ $error("Error: currently, only single word AXI bus supported");
+ $finish;
+ end
+end
+
+localparam [2:0]
+ STATE_IDLE = 3'd0,
+ STATE_HEADER = 3'd1,
+ STATE_READ_1 = 3'd2,
+ STATE_READ_2 = 3'd3,
+ STATE_WRITE_1 = 3'd4,
+ STATE_WRITE_2 = 3'd5,
+ STATE_WAIT_LAST = 3'd6;
+
+reg [2:0] state_reg = STATE_IDLE, state_next;
+
+reg [COUNT_SIZE-1:0] ptr_reg = {COUNT_SIZE{1'b0}}, ptr_next;
+reg [7:0] count_reg = 8'd0, count_next;
+reg last_cycle_reg = 1'b0;
+
+reg [ADDR_WIDTH_ADJ-1:0] addr_reg = {ADDR_WIDTH_ADJ{1'b0}}, addr_next;
+reg [WB_DATA_WIDTH-1:0] data_reg = {WB_DATA_WIDTH{1'b0}}, data_next;
+
+reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
+
+reg wb_we_o_reg = 1'b0, wb_we_o_next;
+reg [WB_SELECT_WIDTH-1:0] wb_sel_o_reg = {WB_SELECT_WIDTH{1'b0}}, wb_sel_o_next;
+reg wb_stb_o_reg = 1'b0, wb_stb_o_next;
+reg wb_cyc_o_reg = 1'b0, wb_cyc_o_next;
+
+reg busy_reg = 1'b0;
+
+// internal datapath
+reg [AXIS_DATA_WIDTH-1:0] output_axis_tdata_int;
+reg [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep_int;
+reg output_axis_tvalid_int;
+reg output_axis_tready_int_reg = 1'b0;
+reg output_axis_tlast_int;
+reg output_axis_tuser_int;
+wire output_axis_tready_int_early;
+
+assign input_axis_tready = input_axis_tready_reg;
+
+assign wb_adr_o = {addr_reg[ADDR_WIDTH_ADJ-1:ADDR_WIDTH_ADJ-WB_VALID_ADDR_WIDTH], {WB_ADDR_WIDTH-WB_VALID_ADDR_WIDTH{1'b0}}};
+assign wb_dat_o = data_reg;
+assign wb_we_o = wb_we_o_reg;
+assign wb_sel_o = wb_sel_o_reg;
+assign wb_stb_o = wb_stb_o_reg;
+assign wb_cyc_o = wb_cyc_o_reg;
+
+assign busy = busy_reg;
+
+always @* begin
+ state_next = STATE_IDLE;
+
+ ptr_next = ptr_reg;
+ count_next = count_reg;
+
+ input_axis_tready_next = 1'b0;
+
+ output_axis_tdata_int = {AXIS_DATA_WIDTH{1'b0}};
+ output_axis_tkeep_int = {{AXIS_KEEP_WIDTH-1{1'b0}}, 1'b1};
+ output_axis_tvalid_int = 1'b0;
+ output_axis_tlast_int = 1'b0;
+ output_axis_tuser_int = 1'b0;
+
+ addr_next = addr_reg;
+ data_next = data_reg;
+
+ wb_we_o_next = wb_we_o_reg;
+ wb_sel_o_next = wb_sel_o_reg;
+ wb_stb_o_next = 1'b0;
+ wb_cyc_o_next = 1'b0;
+
+ case (state_reg)
+ STATE_IDLE: begin
+ // idle, wait for start indicator
+ input_axis_tready_next = output_axis_tready_int_early;
+ wb_we_o_next = 1'b0;
+
+ if (input_axis_tready & input_axis_tvalid) begin
+ if (!IMPLICIT_FRAMING & input_axis_tlast) begin
+ // last asserted, ignore cycle
+ state_next = STATE_IDLE;
+ end else if (input_axis_tdata == READ_REQ) begin
+ // start of read
+ output_axis_tdata_int = READ_RESP;
+ output_axis_tvalid_int = 1'b1;
+ output_axis_tlast_int = 1'b0;
+ output_axis_tuser_int = 1'b0;
+ wb_we_o_next = 1'b0;
+ count_next = COUNT_WORD_WIDTH+ADDR_WORD_WIDTH-1;
+ state_next = STATE_HEADER;
+ end else if (input_axis_tdata == WRITE_REQ) begin
+ // start of write
+ output_axis_tdata_int = WRITE_RESP;
+ output_axis_tvalid_int = 1'b1;
+ output_axis_tlast_int = 1'b0;
+ output_axis_tuser_int = 1'b0;
+ wb_we_o_next = 1'b1;
+ count_next = COUNT_WORD_WIDTH+ADDR_WORD_WIDTH-1;
+ state_next = STATE_HEADER;
+ end else begin
+ // invalid start of packet
+ if (IMPLICIT_FRAMING) begin
+ // drop byte
+ state_next = STATE_IDLE;
+ end else begin
+ // drop packet
+ state_next = STATE_WAIT_LAST;
+ end
+ end
+ end else begin
+ state_next = STATE_IDLE;
+ end
+ end
+ STATE_HEADER: begin
+ // store address and length
+ input_axis_tready_next = output_axis_tready_int_early;
+
+ if (input_axis_tready & input_axis_tvalid) begin
+ // pass through
+ output_axis_tdata_int = input_axis_tdata;
+ output_axis_tvalid_int = 1'b1;
+ output_axis_tlast_int = 1'b0;
+ output_axis_tuser_int = 1'b0;
+ // store pointers
+ if (count_reg < COUNT_WORD_WIDTH) begin
+ ptr_next[AXIS_DATA_WORD_SIZE*count_reg +: AXIS_DATA_WORD_SIZE] = input_axis_tdata;
+ end else begin
+ addr_next[AXIS_DATA_WORD_SIZE*(count_reg-COUNT_WORD_WIDTH) +: AXIS_DATA_WORD_SIZE] = input_axis_tdata;
+ end
+ count_next = count_reg - 1;
+ if (count_reg == 0) begin
+ // end of header
+ // set initial word offset
+ if (WB_ADDR_WIDTH == WB_VALID_ADDR_WIDTH && WORD_PART_ADDR_WIDTH == 0) begin
+ count_next = 0;
+ end else begin
+ count_next = addr_reg[ADDR_WIDTH_ADJ-WB_VALID_ADDR_WIDTH-1:0];
+ end
+ wb_sel_o_next = {WB_SELECT_WIDTH{1'b0}};
+ data_next = {WB_DATA_WIDTH{1'b0}};
+ if (wb_we_o_reg) begin
+ // start writing
+ if (input_axis_tlast) begin
+ // end of frame in header
+ output_axis_tlast_int = 1'b1;
+ output_axis_tuser_int = 1'b1;
+ state_next = STATE_IDLE;
+ end else begin
+ output_axis_tlast_int = 1'b1;
+ state_next = STATE_WRITE_1;
+ end
+ end else begin
+ // start reading
+ if (IMPLICIT_FRAMING) begin
+ input_axis_tready_next = 1'b0;
+ end else begin
+ input_axis_tready_next = !(last_cycle_reg || (input_axis_tvalid & input_axis_tlast));
+ end
+ wb_cyc_o_next = 1'b1;
+ wb_stb_o_next = 1'b1;
+ wb_sel_o_next = {WB_SELECT_WIDTH{1'b1}};
+ state_next = STATE_READ_1;
+ end
+ end else begin
+ if (IMPLICIT_FRAMING) begin
+ state_next = STATE_HEADER;
+ end else begin
+ if (input_axis_tlast) begin
+ // end of frame in header
+ output_axis_tlast_int = 1'b1;
+ output_axis_tuser_int = 1'b1;
+ state_next = STATE_IDLE;
+ end else begin
+ state_next = STATE_HEADER;
+ end
+ end
+ end
+ end else begin
+ state_next = STATE_HEADER;
+ end
+ end
+ STATE_READ_1: begin
+ // wait for ack
+ wb_cyc_o_next = 1'b1;
+ wb_stb_o_next = 1'b1;
+
+ // drop padding
+ if (!IMPLICIT_FRAMING) begin
+ input_axis_tready_next = !(last_cycle_reg || (input_axis_tvalid & input_axis_tlast));
+ end
+
+ if (wb_ack_i || wb_err_i) begin
+ // read cycle complete, store result
+ data_next = wb_dat_i;
+ addr_next = addr_reg + (1 << (WB_ADDR_WIDTH-WB_VALID_ADDR_WIDTH+WORD_PART_ADDR_WIDTH));
+ wb_cyc_o_next = 1'b0;
+ wb_stb_o_next = 1'b0;
+ wb_sel_o_next = {WB_SELECT_WIDTH{1'b0}};
+ state_next = STATE_READ_2;
+ end else begin
+ state_next = STATE_READ_1;
+ end
+ end
+ STATE_READ_2: begin
+ // send data
+
+ // drop padding
+ if (!IMPLICIT_FRAMING) begin
+ input_axis_tready_next = !(last_cycle_reg || (input_axis_tvalid & input_axis_tlast));
+ end
+
+ if (output_axis_tready_int_reg) begin
+ // transfer word and update pointers
+ output_axis_tdata_int = data_reg[AXIS_DATA_WORD_SIZE*count_reg +: AXIS_DATA_WORD_SIZE];
+ output_axis_tvalid_int = 1'b1;
+ output_axis_tlast_int = 1'b0;
+ output_axis_tuser_int = 1'b0;
+ count_next = count_reg + 1;
+ ptr_next = ptr_reg - 1;
+ if (ptr_reg == 1) begin
+ // last word of read
+ output_axis_tlast_int = 1'b1;
+ if (!IMPLICIT_FRAMING && !(last_cycle_reg || (input_axis_tvalid & input_axis_tlast))) begin
+ state_next = STATE_WAIT_LAST;
+ end else begin
+ input_axis_tready_next = output_axis_tready_int_early;
+ state_next = STATE_IDLE;
+ end
+ end else if (count_reg == (WB_SELECT_WIDTH*WB_WORD_SIZE/AXIS_DATA_WORD_SIZE)-1) begin
+ // end of stored data word; read the next one
+ count_next = 0;
+ wb_cyc_o_next = 1'b1;
+ wb_stb_o_next = 1'b1;
+ wb_sel_o_next = {WB_SELECT_WIDTH{1'b1}};
+ state_next = STATE_READ_1;
+ end else begin
+ state_next = STATE_READ_2;
+ end
+ end else begin
+ state_next = STATE_READ_2;
+ end
+ end
+ STATE_WRITE_1: begin
+ // write data
+ input_axis_tready_next = 1'b1;
+
+ if (input_axis_tready & input_axis_tvalid) begin
+ // store word
+ data_next[AXIS_DATA_WORD_SIZE*count_reg +: AXIS_DATA_WORD_SIZE] = input_axis_tdata;
+ count_next = count_reg + 1;
+ ptr_next = ptr_reg - 1;
+ wb_sel_o_next[count_reg >> ((WB_WORD_SIZE/AXIS_DATA_WORD_SIZE)-1)] = 1'b1;
+ if (count_reg == (WB_SELECT_WIDTH*WB_WORD_SIZE/AXIS_DATA_WORD_SIZE)-1 || ptr_reg == 1) begin
+ // have full word or at end of block, start write operation
+ count_next = 0;
+ input_axis_tready_next = 1'b0;
+ wb_cyc_o_next = 1'b1;
+ wb_stb_o_next = 1'b1;
+ state_next = STATE_WRITE_2;
+ end else begin
+ state_next = STATE_WRITE_1;
+ end
+ end else begin
+ state_next = STATE_WRITE_1;
+ end
+ end
+ STATE_WRITE_2: begin
+ // wait for ack
+ wb_cyc_o_next = 1'b1;
+ wb_stb_o_next = 1'b1;
+
+ if (wb_ack_i || wb_err_i) begin
+ // end of write operation
+ data_next = {WB_DATA_WIDTH{1'b0}};
+ addr_next = addr_reg + (1 << (WB_ADDR_WIDTH-WB_VALID_ADDR_WIDTH+WORD_PART_ADDR_WIDTH));
+ wb_cyc_o_next = 1'b0;
+ wb_stb_o_next = 1'b0;
+ wb_sel_o_next = {WB_SELECT_WIDTH{1'b0}};
+ if (ptr_reg == 0) begin
+ // done writing
+ if (!IMPLICIT_FRAMING && !last_cycle_reg) begin
+ input_axis_tready_next = 1'b1;
+ state_next = STATE_WAIT_LAST;
+ end else begin
+ input_axis_tready_next = output_axis_tready_int_early;
+ state_next = STATE_IDLE;
+ end
+ end else begin
+ // more to write
+ state_next = STATE_WRITE_1;
+ end
+ end else begin
+ state_next = STATE_WRITE_2;
+ end
+ end
+ STATE_WAIT_LAST: begin
+ // wait for end of frame
+ input_axis_tready_next = 1'b1;
+
+ if (input_axis_tready & input_axis_tvalid) begin
+ // wait for tlast
+ if (input_axis_tlast) begin
+ input_axis_tready_next = output_axis_tready_int_early;
+ state_next = STATE_IDLE;
+ end else begin
+ state_next = STATE_WAIT_LAST;
+ end
+ end else begin
+ state_next = STATE_WAIT_LAST;
+ end
+ end
+ endcase
+end
+
+always @(posedge clk) begin
+ if (rst) begin
+ state_reg <= STATE_IDLE;
+ input_axis_tready_reg <= 1'b0;
+ wb_stb_o_reg <= 1'b0;
+ wb_cyc_o_reg <= 1'b0;
+ busy_reg <= 1'b0;
+ end else begin
+ state_reg <= state_next;
+ input_axis_tready_reg <= input_axis_tready_next;
+ wb_stb_o_reg <= wb_stb_o_next;
+ wb_cyc_o_reg <= wb_cyc_o_next;
+ busy_reg <= state_next != STATE_IDLE;
+ end
+
+ ptr_reg <= ptr_next;
+ count_reg <= count_next;
+
+ if (input_axis_tready & input_axis_tvalid) begin
+ last_cycle_reg <= input_axis_tlast;
+ end
+
+ addr_reg <= addr_next;
+ data_reg <= data_next;
+
+ wb_we_o_reg <= wb_we_o_next;
+ wb_sel_o_reg <= wb_sel_o_next;
+end
+
+// output datapath logic
+reg [AXIS_DATA_WIDTH-1:0] output_axis_tdata_reg = {AXIS_DATA_WIDTH{1'b0}};
+reg [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep_reg = {{AXIS_KEEP_WIDTH-1{1'b0}}, 1'b1};
+reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
+reg output_axis_tlast_reg = 1'b0;
+reg output_axis_tuser_reg = 1'b0;
+
+reg [AXIS_DATA_WIDTH-1:0] temp_axis_tdata_reg = {AXIS_DATA_WIDTH{1'b0}};
+reg [AXIS_KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {{AXIS_KEEP_WIDTH-1{1'b0}}, 1'b1};
+reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
+reg temp_axis_tlast_reg = 1'b0;
+reg temp_axis_tuser_reg = 1'b0;
+
+// datapath control
+reg store_axis_int_to_output;
+reg store_axis_int_to_temp;
+reg store_axis_temp_to_output;
+
+assign output_axis_tdata = output_axis_tdata_reg;
+assign output_axis_tkeep = output_axis_tkeep_reg;
+assign output_axis_tvalid = output_axis_tvalid_reg;
+assign output_axis_tlast = output_axis_tlast_reg;
+assign output_axis_tuser = output_axis_tuser_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
+
+always @* begin
+ // transfer sink ready state to source
+ output_axis_tvalid_next = output_axis_tvalid_reg;
+ temp_axis_tvalid_next = temp_axis_tvalid_reg;
+
+ store_axis_int_to_output = 1'b0;
+ store_axis_int_to_temp = 1'b0;
+ store_axis_temp_to_output = 1'b0;
+
+ if (output_axis_tready_int_reg) begin
+ // input is ready
+ if (output_axis_tready | ~output_axis_tvalid_reg) begin
+ // output is ready or currently not valid, transfer data to output
+ output_axis_tvalid_next = output_axis_tvalid_int;
+ store_axis_int_to_output = 1'b1;
+ end else begin
+ // output is not ready, store input in temp
+ temp_axis_tvalid_next = output_axis_tvalid_int;
+ store_axis_int_to_temp = 1'b1;
+ end
+ end else if (output_axis_tready) begin
+ // input is not ready, but output is ready
+ output_axis_tvalid_next = temp_axis_tvalid_reg;
+ temp_axis_tvalid_next = 1'b0;
+ store_axis_temp_to_output = 1'b1;
+ end
+end
+
+always @(posedge clk) begin
+ if (rst) begin
+ output_axis_tvalid_reg <= 1'b0;
+ output_axis_tready_int_reg <= 1'b0;
+ temp_axis_tvalid_reg <= 1'b0;
+ end else begin
+ output_axis_tvalid_reg <= output_axis_tvalid_next;
+ output_axis_tready_int_reg <= output_axis_tready_int_early;
+ temp_axis_tvalid_reg <= temp_axis_tvalid_next;
+ end
+
+ // datapath
+ if (store_axis_int_to_output) begin
+ output_axis_tdata_reg <= output_axis_tdata_int;
+ output_axis_tkeep_reg <= output_axis_tkeep_int;
+ output_axis_tlast_reg <= output_axis_tlast_int;
+ output_axis_tuser_reg <= output_axis_tuser_int;
+ end else if (store_axis_temp_to_output) begin
+ output_axis_tdata_reg <= temp_axis_tdata_reg;
+ output_axis_tkeep_reg <= temp_axis_tkeep_reg;
+ output_axis_tlast_reg <= temp_axis_tlast_reg;
+ output_axis_tuser_reg <= temp_axis_tuser_reg;
+ end
+
+ if (store_axis_int_to_temp) begin
+ temp_axis_tdata_reg <= output_axis_tdata_int;
+ temp_axis_tkeep_reg <= output_axis_tkeep_int;
+ temp_axis_tlast_reg <= output_axis_tlast_int;
+ temp_axis_tuser_reg <= output_axis_tuser_int;
+ end
+end
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/priority_encoder.v b/ip/third_party/verilog-wishbone/rtl/priority_encoder.v
new file mode 100644
index 0000000..7303063
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/priority_encoder.v
@@ -0,0 +1,98 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Priority encoder module
+ */
+module priority_encoder #
+(
+ parameter WIDTH = 4,
+ // LSB priority: "LOW", "HIGH"
+ parameter LSB_PRIORITY = "LOW"
+)
+(
+ input wire [WIDTH-1:0] input_unencoded,
+ output wire output_valid,
+ output wire [$clog2(WIDTH)-1:0] output_encoded,
+ output wire [WIDTH-1:0] output_unencoded
+);
+
+// power-of-two width
+parameter W1 = 2**$clog2(WIDTH);
+parameter W2 = W1/2;
+
+generate
+ if (WIDTH == 1) begin
+ // one input
+ assign output_valid = input_unencoded;
+ assign output_encoded = 0;
+ end else if (WIDTH == 2) begin
+ // two inputs - just an OR gate
+ assign output_valid = |input_unencoded;
+ if (LSB_PRIORITY == "LOW") begin
+ assign output_encoded = input_unencoded[1];
+ end else begin
+ assign output_encoded = ~input_unencoded[0];
+ end
+ end else begin
+ // more than two inputs - split into two parts and recurse
+ // also pad input to correct power-of-two width
+ wire [$clog2(W2)-1:0] out1, out2;
+ wire valid1, valid2;
+ priority_encoder #(
+ .WIDTH(W2),
+ .LSB_PRIORITY(LSB_PRIORITY)
+ )
+ priority_encoder_inst1 (
+ .input_unencoded(input_unencoded[W2-1:0]),
+ .output_valid(valid1),
+ .output_encoded(out1)
+ );
+ priority_encoder #(
+ .WIDTH(W2),
+ .LSB_PRIORITY(LSB_PRIORITY)
+ )
+ priority_encoder_inst2 (
+ .input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
+ .output_valid(valid2),
+ .output_encoded(out2)
+ );
+ // multiplexer to select part
+ assign output_valid = valid1 | valid2;
+ if (LSB_PRIORITY == "LOW") begin
+ assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
+ end else begin
+ assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2};
+ end
+ end
+endgenerate
+
+// unencoded output
+assign output_unencoded = 1 << output_encoded;
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_adapter.v b/ip/third_party/verilog-wishbone/rtl/wb_adapter.v
new file mode 100644
index 0000000..ee65ace
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_adapter.v
@@ -0,0 +1,361 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Wishbone width adapter
+ */
+module wb_adapter #
+(
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter WBM_DATA_WIDTH = 32, // width of master data bus in bits (8, 16, 32, or 64)
+ parameter WBM_SELECT_WIDTH = (WBM_DATA_WIDTH/8), // width of master word select bus (1, 2, 4, or 8)
+ parameter WBS_DATA_WIDTH = 32, // width of slave data bus in bits (8, 16, 32, or 64)
+ parameter WBS_SELECT_WIDTH = (WBS_DATA_WIDTH/8) // width of slave word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
+ input wire [WBM_DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [WBM_DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [WBM_SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address output
+ input wire [WBS_DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
+ output wire [WBS_DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
+ output wire wbs_we_o, // WE_O write enable output
+ output wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
+ output wire wbs_stb_o, // STB_O strobe output
+ input wire wbs_ack_i, // ACK_I acknowledge input
+ input wire wbs_err_i, // ERR_I error input
+ input wire wbs_rty_i, // RTY_I retry input
+ output wire wbs_cyc_o // CYC_O cycle output
+);
+
+// address bit offets
+parameter WBM_ADDR_BIT_OFFSET = $clog2(WBM_SELECT_WIDTH);
+parameter WBS_ADDR_BIT_OFFSET = $clog2(WBS_SELECT_WIDTH);
+// for interfaces that are more than one word wide, disable address lines
+parameter WBM_VALID_ADDR_WIDTH = ADDR_WIDTH - WBM_ADDR_BIT_OFFSET;
+parameter WBS_VALID_ADDR_WIDTH = ADDR_WIDTH - WBS_ADDR_BIT_OFFSET;
+// width of data port in words (1, 2, 4, or 8)
+parameter WBM_WORD_WIDTH = WBM_SELECT_WIDTH;
+parameter WBS_WORD_WIDTH = WBS_SELECT_WIDTH;
+// size of words (8, 16, 32, or 64 bits)
+parameter WBM_WORD_SIZE = WBM_DATA_WIDTH/WBM_WORD_WIDTH;
+parameter WBS_WORD_SIZE = WBS_DATA_WIDTH/WBS_WORD_WIDTH;
+// required number of cycles to match widths
+localparam CYCLE_COUNT = (WBM_SELECT_WIDTH > WBS_SELECT_WIDTH) ? (WBM_SELECT_WIDTH / WBS_SELECT_WIDTH) : (WBS_SELECT_WIDTH / WBM_SELECT_WIDTH);
+
+// bus width assertions
+initial begin
+ if (WBM_WORD_WIDTH * WBM_WORD_SIZE != WBM_DATA_WIDTH) begin
+ $error("Error: master data width not evenly divisble");
+ $finish;
+ end
+
+ if (WBS_WORD_WIDTH * WBS_WORD_SIZE != WBS_DATA_WIDTH) begin
+ $error("Error: slave data width not evenly divisble");
+ $finish;
+ end
+
+ if (WBM_WORD_SIZE != WBS_WORD_SIZE) begin
+ $error("Error: word size mismatch");
+ $finish;
+ end
+end
+
+// state register
+localparam [1:0]
+ STATE_IDLE = 2'd0,
+ STATE_WAIT_ACK = 2'd1,
+ STATE_PAUSE = 2'd2;
+
+reg [1:0] state_reg = STATE_IDLE, state_next;
+
+reg [CYCLE_COUNT-1:0] cycle_mask_reg = {CYCLE_COUNT{1'b1}}, cycle_mask_next;
+reg [CYCLE_COUNT-1:0] cycle_sel_raw;
+wire [CYCLE_COUNT-1:0] cycle_sel;
+wire [$clog2(CYCLE_COUNT)-1:0] cycle_sel_enc;
+wire cycle_sel_valid;
+
+reg [$clog2(CYCLE_COUNT)-1:0] current_cycle_reg = 0, current_cycle_next;
+
+reg [WBM_DATA_WIDTH-1:0] wbm_dat_o_reg = {WBM_DATA_WIDTH{1'b0}}, wbm_dat_o_next;
+reg wbm_ack_o_reg = 1'b0, wbm_ack_o_next;
+reg wbm_err_o_reg = 1'b0, wbm_err_o_next;
+reg wbm_rty_o_reg = 1'b0, wbm_rty_o_next;
+
+reg [ADDR_WIDTH-1:0] wbs_adr_o_reg = {ADDR_WIDTH{1'b0}}, wbs_adr_o_next;
+reg [WBS_DATA_WIDTH-1:0] wbs_dat_o_reg = {WBS_DATA_WIDTH{1'b0}}, wbs_dat_o_next;
+reg wbs_we_o_reg = 1'b0, wbs_we_o_next;
+reg [WBS_SELECT_WIDTH-1:0] wbs_sel_o_reg = {WBS_SELECT_WIDTH{1'b0}}, wbs_sel_o_next;
+reg wbs_stb_o_reg = 1'b0, wbs_stb_o_next;
+reg wbs_cyc_o_reg = 1'b0, wbs_cyc_o_next;
+
+assign wbm_dat_o = wbm_dat_o_reg;
+assign wbm_ack_o = wbm_ack_o_reg;
+assign wbm_err_o = wbm_err_o_reg;
+assign wbm_rty_o = wbm_rty_o_reg;
+
+assign wbs_adr_o = wbs_adr_o_reg;
+assign wbs_dat_o = wbs_dat_o_reg;
+assign wbs_we_o = wbs_we_o_reg;
+assign wbs_sel_o = wbs_sel_o_reg;
+assign wbs_stb_o = wbs_stb_o_reg;
+assign wbs_cyc_o = wbs_cyc_o_reg;
+
+priority_encoder #(
+ .WIDTH(CYCLE_COUNT),
+ .LSB_PRIORITY("HIGH")
+)
+cycle_encoder_inst (
+ .input_unencoded(cycle_sel_raw & cycle_mask_reg),
+ .output_valid(cycle_sel_valid),
+ .output_encoded(cycle_sel_enc),
+ .output_unencoded(cycle_sel)
+);
+
+integer j;
+
+always @* begin
+ for (j = 0; j < CYCLE_COUNT; j = j + 1) begin
+ cycle_sel_raw[j] <= wbm_sel_i[j*WBS_SELECT_WIDTH +: WBS_SELECT_WIDTH] != 0;
+ end
+end
+
+integer i;
+
+always @* begin
+ state_next = STATE_IDLE;
+
+ cycle_mask_next = cycle_mask_reg;
+
+ current_cycle_next = current_cycle_reg;
+
+ wbm_dat_o_next = wbm_dat_o_reg;
+ wbm_ack_o_next = 1'b0;
+ wbm_err_o_next = 1'b0;
+ wbm_rty_o_next = 1'b0;
+
+ wbs_adr_o_next = wbs_adr_o_reg;
+ wbs_dat_o_next = wbs_dat_o_reg;
+ wbs_we_o_next = wbs_we_o_reg;
+ wbs_sel_o_next = wbs_sel_o_reg;
+ wbs_stb_o_next = wbs_stb_o_reg;
+ wbs_cyc_o_next = wbs_cyc_o_reg;
+
+ if (WBM_WORD_WIDTH > WBS_WORD_WIDTH) begin
+ // master is wider (multiple cycles may be necessary)
+ case (state_reg)
+ STATE_IDLE: begin
+ // idle state
+ wbm_dat_o_next = 1'b0;
+ wbs_cyc_o_next = wbm_cyc_i;
+
+ cycle_mask_next = {CYCLE_COUNT{1'b1}};
+
+ state_next = STATE_IDLE;
+
+ if (wbm_cyc_i & wbm_stb_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o)) begin
+ // master cycle start
+ wbm_err_o_next = 1'b1;
+
+ if (cycle_sel_valid) begin
+ // set current cycle and mask for next cycle
+ current_cycle_next = cycle_sel_enc;
+ cycle_mask_next = {CYCLE_COUNT{1'b1}} << (cycle_sel_enc+1);
+ // mask address for slave alignment
+ wbs_adr_o_next = wbm_adr_i & ({ADDR_WIDTH{1'b1}} << WBM_ADDR_BIT_OFFSET);
+ wbs_adr_o_next[WBM_ADDR_BIT_OFFSET - 1:WBS_ADDR_BIT_OFFSET] = cycle_sel_enc;
+ // select corresponding data word
+ wbs_dat_o_next = wbm_dat_i[cycle_sel_enc*WBS_DATA_WIDTH +: WBS_DATA_WIDTH];
+ wbs_we_o_next = wbm_we_i;
+ // select proper select lines
+ wbs_sel_o_next = wbm_sel_i[cycle_sel_enc*WBS_SELECT_WIDTH +: WBS_SELECT_WIDTH];
+ wbs_stb_o_next = 1'b1;
+ wbs_cyc_o_next = 1'b1;
+ wbm_err_o_next = 1'b0;
+ state_next = STATE_WAIT_ACK;
+ end
+ end
+ end
+ STATE_WAIT_ACK: begin
+ if (wbs_err_i | wbs_rty_i) begin
+ // error or retry - stop and propagate condition to master
+ cycle_mask_next = {CYCLE_COUNT{1'b1}};
+ wbm_ack_o_next = wbs_ack_i;
+ wbm_err_o_next = wbs_err_i;
+ wbm_rty_o_next = wbs_rty_i;
+ wbs_we_o_next = 1'b0;
+ wbs_stb_o_next = 1'b0;
+ state_next = STATE_IDLE;
+ end else if (wbs_ack_i) begin
+ // end of cycle - pass through slave to master
+ // store output word with proper offset
+ wbm_dat_o_next[current_cycle_reg*WBS_DATA_WIDTH +: WBS_DATA_WIDTH] = wbs_dat_i;
+ wbm_ack_o_next = wbs_ack_i;
+ wbs_we_o_next = 1'b0;
+ wbs_stb_o_next = 1'b0;
+
+ cycle_mask_next = {CYCLE_COUNT{1'b1}};
+ state_next = STATE_IDLE;
+
+ if (cycle_sel_valid) begin
+ // set current cycle and mask for next cycle
+ current_cycle_next = cycle_sel_enc;
+ cycle_mask_next = {CYCLE_COUNT{1'b1}} << (cycle_sel_enc+1);
+ // mask address for slave alignment
+ wbs_adr_o_next = wbm_adr_i & ({ADDR_WIDTH{1'b1}} << WBM_ADDR_BIT_OFFSET);
+ wbs_adr_o_next[WBM_ADDR_BIT_OFFSET - 1:WBS_ADDR_BIT_OFFSET] = cycle_sel_enc;
+ // select corresponding data word
+ wbs_dat_o_next = wbm_dat_i[cycle_sel_enc*WBS_DATA_WIDTH +: WBS_DATA_WIDTH];
+ wbs_we_o_next = wbm_we_i;
+ // select proper select lines
+ wbs_sel_o_next = wbm_sel_i[cycle_sel_enc*WBS_SELECT_WIDTH +: WBS_SELECT_WIDTH];
+ wbs_stb_o_next = 1'b0;
+ wbs_cyc_o_next = 1'b1;
+ wbm_ack_o_next = 1'b0;
+ state_next = STATE_PAUSE;
+ end
+ end else begin
+ state_next = STATE_WAIT_ACK;
+ end
+ end
+ STATE_PAUSE: begin
+ // start new cycle
+ wbs_stb_o_next = 1'b1;
+ state_next = STATE_WAIT_ACK;
+ end
+ endcase
+ end else if (WBS_WORD_WIDTH > WBM_WORD_WIDTH) begin
+ // slave is wider (always single cycle)
+ if (wbs_cyc_o_reg & wbs_stb_o_reg) begin
+ // cycle - hold values
+ if (wbs_ack_i | wbs_err_i | wbs_rty_i) begin
+ // end of cycle - pass through slave to master
+ // select output word based on address LSBs
+ wbm_dat_o_next = wbs_dat_i >> (wbm_adr_i[WBS_ADDR_BIT_OFFSET - 1:WBM_ADDR_BIT_OFFSET] * WBM_DATA_WIDTH);
+ wbm_ack_o_next = wbs_ack_i;
+ wbm_err_o_next = wbs_err_i;
+ wbm_rty_o_next = wbs_rty_i;
+ wbs_we_o_next = 1'b0;
+ wbs_stb_o_next = 1'b0;
+ end
+ end else begin
+ // idle - pass through master to slave
+ wbm_ack_o_next = 1'b0;
+ wbm_err_o_next = 1'b0;
+ wbm_rty_o_next = 1'b0;
+ // mask address for slave alignment
+ wbs_adr_o_next = wbm_adr_i & ({ADDR_WIDTH{1'b1}} << WBS_ADDR_BIT_OFFSET);
+ // duplicate input data across output port
+ wbs_dat_o_next = {(WBS_WORD_WIDTH / WBM_WORD_WIDTH){wbm_dat_i}};
+ wbs_we_o_next = wbm_we_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
+ // shift select lines based on address LSBs
+ wbs_sel_o_next = wbm_sel_i << (wbm_adr_i[WBS_ADDR_BIT_OFFSET - 1:WBM_ADDR_BIT_OFFSET] * WBM_SELECT_WIDTH);
+ wbs_stb_o_next = wbm_stb_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
+ wbs_cyc_o_next = wbm_cyc_i;
+ end
+ end else begin
+ // same width - act as a simple register
+ if (wbs_cyc_o_reg & wbs_stb_o_reg) begin
+ // cycle - hold values
+ if (wbs_ack_i | wbs_err_i | wbs_rty_i) begin
+ // end of cycle - pass through slave to master
+ wbm_dat_o_next = wbs_dat_i;
+ wbm_ack_o_next = wbs_ack_i;
+ wbm_err_o_next = wbs_err_i;
+ wbm_rty_o_next = wbs_rty_i;
+ wbs_we_o_next = 1'b0;
+ wbs_stb_o_next = 1'b0;
+ end
+ end else begin
+ // idle - pass through master to slave
+ wbm_ack_o_next = 1'b0;
+ wbm_err_o_next = 1'b0;
+ wbm_rty_o_next = 1'b0;
+ wbs_adr_o_next = wbm_adr_i;
+ wbs_dat_o_next = wbm_dat_i;
+ wbs_we_o_next = wbm_we_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
+ wbs_sel_o_next = wbm_sel_i;
+ wbs_stb_o_next = wbm_stb_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
+ wbs_cyc_o_next = wbm_cyc_i;
+ end
+ end
+end
+
+always @(posedge clk) begin
+ if (rst) begin
+ state_reg <= STATE_IDLE;
+
+ cycle_mask_reg <= {CYCLE_COUNT{1'b1}};
+
+ wbm_ack_o_reg <= 1'b0;
+ wbm_err_o_reg <= 1'b0;
+ wbm_rty_o_reg <= 1'b0;
+
+ wbs_stb_o_reg <= 1'b0;
+ wbs_cyc_o_reg <= 1'b0;
+ end else begin
+ state_reg <= state_next;
+
+ cycle_mask_reg <= cycle_mask_next;
+
+ wbm_ack_o_reg <= wbm_ack_o_next;
+ wbm_err_o_reg <= wbm_err_o_next;
+ wbm_rty_o_reg <= wbm_rty_o_next;
+
+ wbs_stb_o_reg <= wbs_stb_o_next;
+ wbs_cyc_o_reg <= wbs_cyc_o_next;
+ end
+
+ current_cycle_reg <= current_cycle_next;
+
+ wbm_dat_o_reg <= wbm_dat_o_next;
+
+ wbs_adr_o_reg <= wbs_adr_o_next;
+ wbs_dat_o_reg <= wbs_dat_o_next;
+ wbs_we_o_reg <= wbs_we_o_next;
+ wbs_sel_o_reg <= wbs_sel_o_next;
+end
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_arbiter.py b/ip/third_party/verilog-wishbone/rtl/wb_arbiter.py
new file mode 100755
index 0000000..2fdf912
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_arbiter.py
@@ -0,0 +1,183 @@
+#!/usr/bin/env python
+"""
+Generates a Wishbone arbiter with the specified number of ports
+"""
+
+from __future__ import print_function
+
+import argparse
+import math
+from jinja2 import Template
+
+def main():
+ parser = argparse.ArgumentParser(description=__doc__.strip())
+ parser.add_argument('-p', '--ports', type=int, default=2, help="number of ports")
+ parser.add_argument('-n', '--name', type=str, help="module name")
+ parser.add_argument('-o', '--output', type=str, help="output file name")
+
+ args = parser.parse_args()
+
+ try:
+ generate(**args.__dict__)
+ except IOError as ex:
+ print(ex)
+ exit(1)
+
+def generate(ports=2, name=None, output=None):
+ if name is None:
+ name = "wb_arbiter_{0}".format(ports)
+
+ if output is None:
+ output = name + ".v"
+
+ print("Opening file '{0}'...".format(output))
+
+ output_file = open(output, 'w')
+
+ print("Generating {0} port Wishbone arbiter {1}...".format(ports, name))
+
+ select_width = int(math.ceil(math.log(ports, 2)))
+
+ t = Template(u"""/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone {{n}} port arbiter
+ */
+module {{name}} #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8), // width of word select bus (1, 2, 4, or 8)
+ parameter ARB_TYPE = "PRIORITY", // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+ parameter LSB_PRIORITY = "HIGH" // LSB priority: "LOW", "HIGH"
+)
+(
+ input wire clk,
+ input wire rst,
+{%- for p in ports %}
+
+ /*
+ * Wishbone master {{p}} input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm{{p}}_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm{{p}}_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm{{p}}_dat_o, // DAT_O() data out
+ input wire wbm{{p}}_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm{{p}}_sel_i, // SEL_I() select input
+ input wire wbm{{p}}_stb_i, // STB_I strobe input
+ output wire wbm{{p}}_ack_o, // ACK_O acknowledge output
+ output wire wbm{{p}}_err_o, // ERR_O error output
+ output wire wbm{{p}}_rty_o, // RTY_O retry output
+ input wire wbm{{p}}_cyc_i, // CYC_I cycle input
+{%- endfor %}
+
+ /*
+ * Wishbone slave output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
+ output wire wbs_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
+ output wire wbs_stb_o, // STB_O strobe output
+ input wire wbs_ack_i, // ACK_I acknowledge input
+ input wire wbs_err_i, // ERR_I error input
+ input wire wbs_rty_i, // RTY_I retry input
+ output wire wbs_cyc_o // CYC_O cycle output
+);
+
+wire [{{n-1}}:0] request;
+wire [{{n-1}}:0] grant;
+{% for p in ports %}
+assign request[{{p}}] = wbm{{p}}_cyc_i;
+{%- endfor %}
+{% for p in ports %}
+wire wbm{{p}}_sel = grant[{{p}}] & grant_valid;
+{%- endfor %}
+{%- for p in ports %}
+
+// master {{p}}
+assign wbm{{p}}_dat_o = wbs_dat_i;
+assign wbm{{p}}_ack_o = wbs_ack_i & wbm{{p}}_sel;
+assign wbm{{p}}_err_o = wbs_err_i & wbm{{p}}_sel;
+assign wbm{{p}}_rty_o = wbs_rty_i & wbm{{p}}_sel;
+{%- endfor %}
+
+// slave
+assign wbs_adr_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_adr_i :
+ {% endfor %}{ADDR_WIDTH{1'b0}};
+
+assign wbs_dat_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_dat_i :
+ {% endfor %}{DATA_WIDTH{1'b0}};
+
+assign wbs_we_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_we_i :
+ {% endfor %}1'b0;
+
+assign wbs_sel_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_sel_i :
+ {% endfor %}{SELECT_WIDTH{1'b0}};
+
+assign wbs_stb_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_stb_i :
+ {% endfor %}1'b0;
+
+assign wbs_cyc_o = {% for p in ports %}wbm{{p}}_sel ? 1'b1 :
+ {% endfor %}1'b0;
+
+// arbiter instance
+arbiter #(
+ .PORTS({{n}}),
+ .TYPE(ARB_TYPE),
+ .BLOCK("REQUEST"),
+ .LSB_PRIORITY(LSB_PRIORITY)
+)
+arb_inst (
+ .clk(clk),
+ .rst(rst),
+ .request(request),
+ .acknowledge(),
+ .grant(grant),
+ .grant_valid(grant_valid),
+ .grant_encoded()
+);
+
+endmodule
+
+""")
+
+ output_file.write(t.render(
+ n=ports,
+ w=select_width,
+ name=name,
+ ports=range(ports)
+ ))
+
+ print("Done")
+
+if __name__ == "__main__":
+ main()
+
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_arbiter_2.v b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_2.v
new file mode 100644
index 0000000..ead4717
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_2.v
@@ -0,0 +1,150 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 2 port arbiter
+ */
+module wb_arbiter_2 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8), // width of word select bus (1, 2, 4, or 8)
+ parameter ARB_TYPE = "PRIORITY", // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+ parameter LSB_PRIORITY = "HIGH" // LSB priority: "LOW", "HIGH"
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master 0 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm0_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm0_dat_o, // DAT_O() data out
+ input wire wbm0_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm0_sel_i, // SEL_I() select input
+ input wire wbm0_stb_i, // STB_I strobe input
+ output wire wbm0_ack_o, // ACK_O acknowledge output
+ output wire wbm0_err_o, // ERR_O error output
+ output wire wbm0_rty_o, // RTY_O retry output
+ input wire wbm0_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 1 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm1_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm1_dat_o, // DAT_O() data out
+ input wire wbm1_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm1_sel_i, // SEL_I() select input
+ input wire wbm1_stb_i, // STB_I strobe input
+ output wire wbm1_ack_o, // ACK_O acknowledge output
+ output wire wbm1_err_o, // ERR_O error output
+ output wire wbm1_rty_o, // RTY_O retry output
+ input wire wbm1_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
+ output wire wbs_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
+ output wire wbs_stb_o, // STB_O strobe output
+ input wire wbs_ack_i, // ACK_I acknowledge input
+ input wire wbs_err_i, // ERR_I error input
+ input wire wbs_rty_i, // RTY_I retry input
+ output wire wbs_cyc_o // CYC_O cycle output
+);
+
+wire [1:0] request;
+wire [1:0] grant;
+
+assign request[0] = wbm0_cyc_i;
+assign request[1] = wbm1_cyc_i;
+
+wire wbm0_sel = grant[0] & grant_valid;
+wire wbm1_sel = grant[1] & grant_valid;
+
+// master 0
+assign wbm0_dat_o = wbs_dat_i;
+assign wbm0_ack_o = wbs_ack_i & wbm0_sel;
+assign wbm0_err_o = wbs_err_i & wbm0_sel;
+assign wbm0_rty_o = wbs_rty_i & wbm0_sel;
+
+// master 1
+assign wbm1_dat_o = wbs_dat_i;
+assign wbm1_ack_o = wbs_ack_i & wbm1_sel;
+assign wbm1_err_o = wbs_err_i & wbm1_sel;
+assign wbm1_rty_o = wbs_rty_i & wbm1_sel;
+
+// slave
+assign wbs_adr_o = wbm0_sel ? wbm0_adr_i :
+ wbm1_sel ? wbm1_adr_i :
+ {ADDR_WIDTH{1'b0}};
+
+assign wbs_dat_o = wbm0_sel ? wbm0_dat_i :
+ wbm1_sel ? wbm1_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbs_we_o = wbm0_sel ? wbm0_we_i :
+ wbm1_sel ? wbm1_we_i :
+ 1'b0;
+
+assign wbs_sel_o = wbm0_sel ? wbm0_sel_i :
+ wbm1_sel ? wbm1_sel_i :
+ {SELECT_WIDTH{1'b0}};
+
+assign wbs_stb_o = wbm0_sel ? wbm0_stb_i :
+ wbm1_sel ? wbm1_stb_i :
+ 1'b0;
+
+assign wbs_cyc_o = wbm0_sel ? 1'b1 :
+ wbm1_sel ? 1'b1 :
+ 1'b0;
+
+// arbiter instance
+arbiter #(
+ .PORTS(2),
+ .TYPE(ARB_TYPE),
+ .BLOCK("REQUEST"),
+ .LSB_PRIORITY(LSB_PRIORITY)
+)
+arb_inst (
+ .clk(clk),
+ .rst(rst),
+ .request(request),
+ .acknowledge(),
+ .grant(grant),
+ .grant_valid(grant_valid),
+ .grant_encoded()
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_arbiter_3.v b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_3.v
new file mode 100644
index 0000000..22250e5
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_3.v
@@ -0,0 +1,178 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 3 port arbiter
+ */
+module wb_arbiter_3 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8), // width of word select bus (1, 2, 4, or 8)
+ parameter ARB_TYPE = "PRIORITY", // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+ parameter LSB_PRIORITY = "HIGH" // LSB priority: "LOW", "HIGH"
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master 0 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm0_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm0_dat_o, // DAT_O() data out
+ input wire wbm0_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm0_sel_i, // SEL_I() select input
+ input wire wbm0_stb_i, // STB_I strobe input
+ output wire wbm0_ack_o, // ACK_O acknowledge output
+ output wire wbm0_err_o, // ERR_O error output
+ output wire wbm0_rty_o, // RTY_O retry output
+ input wire wbm0_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 1 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm1_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm1_dat_o, // DAT_O() data out
+ input wire wbm1_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm1_sel_i, // SEL_I() select input
+ input wire wbm1_stb_i, // STB_I strobe input
+ output wire wbm1_ack_o, // ACK_O acknowledge output
+ output wire wbm1_err_o, // ERR_O error output
+ output wire wbm1_rty_o, // RTY_O retry output
+ input wire wbm1_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 2 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm2_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm2_dat_o, // DAT_O() data out
+ input wire wbm2_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm2_sel_i, // SEL_I() select input
+ input wire wbm2_stb_i, // STB_I strobe input
+ output wire wbm2_ack_o, // ACK_O acknowledge output
+ output wire wbm2_err_o, // ERR_O error output
+ output wire wbm2_rty_o, // RTY_O retry output
+ input wire wbm2_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
+ output wire wbs_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
+ output wire wbs_stb_o, // STB_O strobe output
+ input wire wbs_ack_i, // ACK_I acknowledge input
+ input wire wbs_err_i, // ERR_I error input
+ input wire wbs_rty_i, // RTY_I retry input
+ output wire wbs_cyc_o // CYC_O cycle output
+);
+
+wire [2:0] request;
+wire [2:0] grant;
+
+assign request[0] = wbm0_cyc_i;
+assign request[1] = wbm1_cyc_i;
+assign request[2] = wbm2_cyc_i;
+
+wire wbm0_sel = grant[0] & grant_valid;
+wire wbm1_sel = grant[1] & grant_valid;
+wire wbm2_sel = grant[2] & grant_valid;
+
+// master 0
+assign wbm0_dat_o = wbs_dat_i;
+assign wbm0_ack_o = wbs_ack_i & wbm0_sel;
+assign wbm0_err_o = wbs_err_i & wbm0_sel;
+assign wbm0_rty_o = wbs_rty_i & wbm0_sel;
+
+// master 1
+assign wbm1_dat_o = wbs_dat_i;
+assign wbm1_ack_o = wbs_ack_i & wbm1_sel;
+assign wbm1_err_o = wbs_err_i & wbm1_sel;
+assign wbm1_rty_o = wbs_rty_i & wbm1_sel;
+
+// master 2
+assign wbm2_dat_o = wbs_dat_i;
+assign wbm2_ack_o = wbs_ack_i & wbm2_sel;
+assign wbm2_err_o = wbs_err_i & wbm2_sel;
+assign wbm2_rty_o = wbs_rty_i & wbm2_sel;
+
+// slave
+assign wbs_adr_o = wbm0_sel ? wbm0_adr_i :
+ wbm1_sel ? wbm1_adr_i :
+ wbm2_sel ? wbm2_adr_i :
+ {ADDR_WIDTH{1'b0}};
+
+assign wbs_dat_o = wbm0_sel ? wbm0_dat_i :
+ wbm1_sel ? wbm1_dat_i :
+ wbm2_sel ? wbm2_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbs_we_o = wbm0_sel ? wbm0_we_i :
+ wbm1_sel ? wbm1_we_i :
+ wbm2_sel ? wbm2_we_i :
+ 1'b0;
+
+assign wbs_sel_o = wbm0_sel ? wbm0_sel_i :
+ wbm1_sel ? wbm1_sel_i :
+ wbm2_sel ? wbm2_sel_i :
+ {SELECT_WIDTH{1'b0}};
+
+assign wbs_stb_o = wbm0_sel ? wbm0_stb_i :
+ wbm1_sel ? wbm1_stb_i :
+ wbm2_sel ? wbm2_stb_i :
+ 1'b0;
+
+assign wbs_cyc_o = wbm0_sel ? 1'b1 :
+ wbm1_sel ? 1'b1 :
+ wbm2_sel ? 1'b1 :
+ 1'b0;
+
+// arbiter instance
+arbiter #(
+ .PORTS(3),
+ .TYPE(ARB_TYPE),
+ .BLOCK("REQUEST"),
+ .LSB_PRIORITY(LSB_PRIORITY)
+)
+arb_inst (
+ .clk(clk),
+ .rst(rst),
+ .request(request),
+ .acknowledge(),
+ .grant(grant),
+ .grant_valid(grant_valid),
+ .grant_encoded()
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_arbiter_4.v b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_4.v
new file mode 100644
index 0000000..883784a
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_4.v
@@ -0,0 +1,206 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 4 port arbiter
+ */
+module wb_arbiter_4 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8), // width of word select bus (1, 2, 4, or 8)
+ parameter ARB_TYPE = "PRIORITY", // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+ parameter LSB_PRIORITY = "HIGH" // LSB priority: "LOW", "HIGH"
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master 0 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm0_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm0_dat_o, // DAT_O() data out
+ input wire wbm0_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm0_sel_i, // SEL_I() select input
+ input wire wbm0_stb_i, // STB_I strobe input
+ output wire wbm0_ack_o, // ACK_O acknowledge output
+ output wire wbm0_err_o, // ERR_O error output
+ output wire wbm0_rty_o, // RTY_O retry output
+ input wire wbm0_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 1 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm1_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm1_dat_o, // DAT_O() data out
+ input wire wbm1_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm1_sel_i, // SEL_I() select input
+ input wire wbm1_stb_i, // STB_I strobe input
+ output wire wbm1_ack_o, // ACK_O acknowledge output
+ output wire wbm1_err_o, // ERR_O error output
+ output wire wbm1_rty_o, // RTY_O retry output
+ input wire wbm1_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 2 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm2_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm2_dat_o, // DAT_O() data out
+ input wire wbm2_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm2_sel_i, // SEL_I() select input
+ input wire wbm2_stb_i, // STB_I strobe input
+ output wire wbm2_ack_o, // ACK_O acknowledge output
+ output wire wbm2_err_o, // ERR_O error output
+ output wire wbm2_rty_o, // RTY_O retry output
+ input wire wbm2_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 3 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm3_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm3_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm3_dat_o, // DAT_O() data out
+ input wire wbm3_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm3_sel_i, // SEL_I() select input
+ input wire wbm3_stb_i, // STB_I strobe input
+ output wire wbm3_ack_o, // ACK_O acknowledge output
+ output wire wbm3_err_o, // ERR_O error output
+ output wire wbm3_rty_o, // RTY_O retry output
+ input wire wbm3_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
+ output wire wbs_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
+ output wire wbs_stb_o, // STB_O strobe output
+ input wire wbs_ack_i, // ACK_I acknowledge input
+ input wire wbs_err_i, // ERR_I error input
+ input wire wbs_rty_i, // RTY_I retry input
+ output wire wbs_cyc_o // CYC_O cycle output
+);
+
+wire [3:0] request;
+wire [3:0] grant;
+
+assign request[0] = wbm0_cyc_i;
+assign request[1] = wbm1_cyc_i;
+assign request[2] = wbm2_cyc_i;
+assign request[3] = wbm3_cyc_i;
+
+wire wbm0_sel = grant[0] & grant_valid;
+wire wbm1_sel = grant[1] & grant_valid;
+wire wbm2_sel = grant[2] & grant_valid;
+wire wbm3_sel = grant[3] & grant_valid;
+
+// master 0
+assign wbm0_dat_o = wbs_dat_i;
+assign wbm0_ack_o = wbs_ack_i & wbm0_sel;
+assign wbm0_err_o = wbs_err_i & wbm0_sel;
+assign wbm0_rty_o = wbs_rty_i & wbm0_sel;
+
+// master 1
+assign wbm1_dat_o = wbs_dat_i;
+assign wbm1_ack_o = wbs_ack_i & wbm1_sel;
+assign wbm1_err_o = wbs_err_i & wbm1_sel;
+assign wbm1_rty_o = wbs_rty_i & wbm1_sel;
+
+// master 2
+assign wbm2_dat_o = wbs_dat_i;
+assign wbm2_ack_o = wbs_ack_i & wbm2_sel;
+assign wbm2_err_o = wbs_err_i & wbm2_sel;
+assign wbm2_rty_o = wbs_rty_i & wbm2_sel;
+
+// master 3
+assign wbm3_dat_o = wbs_dat_i;
+assign wbm3_ack_o = wbs_ack_i & wbm3_sel;
+assign wbm3_err_o = wbs_err_i & wbm3_sel;
+assign wbm3_rty_o = wbs_rty_i & wbm3_sel;
+
+// slave
+assign wbs_adr_o = wbm0_sel ? wbm0_adr_i :
+ wbm1_sel ? wbm1_adr_i :
+ wbm2_sel ? wbm2_adr_i :
+ wbm3_sel ? wbm3_adr_i :
+ {ADDR_WIDTH{1'b0}};
+
+assign wbs_dat_o = wbm0_sel ? wbm0_dat_i :
+ wbm1_sel ? wbm1_dat_i :
+ wbm2_sel ? wbm2_dat_i :
+ wbm3_sel ? wbm3_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbs_we_o = wbm0_sel ? wbm0_we_i :
+ wbm1_sel ? wbm1_we_i :
+ wbm2_sel ? wbm2_we_i :
+ wbm3_sel ? wbm3_we_i :
+ 1'b0;
+
+assign wbs_sel_o = wbm0_sel ? wbm0_sel_i :
+ wbm1_sel ? wbm1_sel_i :
+ wbm2_sel ? wbm2_sel_i :
+ wbm3_sel ? wbm3_sel_i :
+ {SELECT_WIDTH{1'b0}};
+
+assign wbs_stb_o = wbm0_sel ? wbm0_stb_i :
+ wbm1_sel ? wbm1_stb_i :
+ wbm2_sel ? wbm2_stb_i :
+ wbm3_sel ? wbm3_stb_i :
+ 1'b0;
+
+assign wbs_cyc_o = wbm0_sel ? 1'b1 :
+ wbm1_sel ? 1'b1 :
+ wbm2_sel ? 1'b1 :
+ wbm3_sel ? 1'b1 :
+ 1'b0;
+
+// arbiter instance
+arbiter #(
+ .PORTS(4),
+ .TYPE(ARB_TYPE),
+ .BLOCK("REQUEST"),
+ .LSB_PRIORITY(LSB_PRIORITY)
+)
+arb_inst (
+ .clk(clk),
+ .rst(rst),
+ .request(request),
+ .acknowledge(),
+ .grant(grant),
+ .grant_valid(grant_valid),
+ .grant_encoded()
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_arbiter_5.v b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_5.v
new file mode 100644
index 0000000..dba2468
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_5.v
@@ -0,0 +1,234 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 5 port arbiter
+ */
+module wb_arbiter_5 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8), // width of word select bus (1, 2, 4, or 8)
+ parameter ARB_TYPE = "PRIORITY", // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+ parameter LSB_PRIORITY = "HIGH" // LSB priority: "LOW", "HIGH"
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master 0 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm0_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm0_dat_o, // DAT_O() data out
+ input wire wbm0_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm0_sel_i, // SEL_I() select input
+ input wire wbm0_stb_i, // STB_I strobe input
+ output wire wbm0_ack_o, // ACK_O acknowledge output
+ output wire wbm0_err_o, // ERR_O error output
+ output wire wbm0_rty_o, // RTY_O retry output
+ input wire wbm0_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 1 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm1_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm1_dat_o, // DAT_O() data out
+ input wire wbm1_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm1_sel_i, // SEL_I() select input
+ input wire wbm1_stb_i, // STB_I strobe input
+ output wire wbm1_ack_o, // ACK_O acknowledge output
+ output wire wbm1_err_o, // ERR_O error output
+ output wire wbm1_rty_o, // RTY_O retry output
+ input wire wbm1_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 2 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm2_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm2_dat_o, // DAT_O() data out
+ input wire wbm2_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm2_sel_i, // SEL_I() select input
+ input wire wbm2_stb_i, // STB_I strobe input
+ output wire wbm2_ack_o, // ACK_O acknowledge output
+ output wire wbm2_err_o, // ERR_O error output
+ output wire wbm2_rty_o, // RTY_O retry output
+ input wire wbm2_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 3 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm3_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm3_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm3_dat_o, // DAT_O() data out
+ input wire wbm3_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm3_sel_i, // SEL_I() select input
+ input wire wbm3_stb_i, // STB_I strobe input
+ output wire wbm3_ack_o, // ACK_O acknowledge output
+ output wire wbm3_err_o, // ERR_O error output
+ output wire wbm3_rty_o, // RTY_O retry output
+ input wire wbm3_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 4 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm4_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm4_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm4_dat_o, // DAT_O() data out
+ input wire wbm4_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm4_sel_i, // SEL_I() select input
+ input wire wbm4_stb_i, // STB_I strobe input
+ output wire wbm4_ack_o, // ACK_O acknowledge output
+ output wire wbm4_err_o, // ERR_O error output
+ output wire wbm4_rty_o, // RTY_O retry output
+ input wire wbm4_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
+ output wire wbs_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
+ output wire wbs_stb_o, // STB_O strobe output
+ input wire wbs_ack_i, // ACK_I acknowledge input
+ input wire wbs_err_i, // ERR_I error input
+ input wire wbs_rty_i, // RTY_I retry input
+ output wire wbs_cyc_o // CYC_O cycle output
+);
+
+wire [4:0] request;
+wire [4:0] grant;
+
+assign request[0] = wbm0_cyc_i;
+assign request[1] = wbm1_cyc_i;
+assign request[2] = wbm2_cyc_i;
+assign request[3] = wbm3_cyc_i;
+assign request[4] = wbm4_cyc_i;
+
+wire wbm0_sel = grant[0] & grant_valid;
+wire wbm1_sel = grant[1] & grant_valid;
+wire wbm2_sel = grant[2] & grant_valid;
+wire wbm3_sel = grant[3] & grant_valid;
+wire wbm4_sel = grant[4] & grant_valid;
+
+// master 0
+assign wbm0_dat_o = wbs_dat_i;
+assign wbm0_ack_o = wbs_ack_i & wbm0_sel;
+assign wbm0_err_o = wbs_err_i & wbm0_sel;
+assign wbm0_rty_o = wbs_rty_i & wbm0_sel;
+
+// master 1
+assign wbm1_dat_o = wbs_dat_i;
+assign wbm1_ack_o = wbs_ack_i & wbm1_sel;
+assign wbm1_err_o = wbs_err_i & wbm1_sel;
+assign wbm1_rty_o = wbs_rty_i & wbm1_sel;
+
+// master 2
+assign wbm2_dat_o = wbs_dat_i;
+assign wbm2_ack_o = wbs_ack_i & wbm2_sel;
+assign wbm2_err_o = wbs_err_i & wbm2_sel;
+assign wbm2_rty_o = wbs_rty_i & wbm2_sel;
+
+// master 3
+assign wbm3_dat_o = wbs_dat_i;
+assign wbm3_ack_o = wbs_ack_i & wbm3_sel;
+assign wbm3_err_o = wbs_err_i & wbm3_sel;
+assign wbm3_rty_o = wbs_rty_i & wbm3_sel;
+
+// master 4
+assign wbm4_dat_o = wbs_dat_i;
+assign wbm4_ack_o = wbs_ack_i & wbm4_sel;
+assign wbm4_err_o = wbs_err_i & wbm4_sel;
+assign wbm4_rty_o = wbs_rty_i & wbm4_sel;
+
+// slave
+assign wbs_adr_o = wbm0_sel ? wbm0_adr_i :
+ wbm1_sel ? wbm1_adr_i :
+ wbm2_sel ? wbm2_adr_i :
+ wbm3_sel ? wbm3_adr_i :
+ wbm4_sel ? wbm4_adr_i :
+ {ADDR_WIDTH{1'b0}};
+
+assign wbs_dat_o = wbm0_sel ? wbm0_dat_i :
+ wbm1_sel ? wbm1_dat_i :
+ wbm2_sel ? wbm2_dat_i :
+ wbm3_sel ? wbm3_dat_i :
+ wbm4_sel ? wbm4_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbs_we_o = wbm0_sel ? wbm0_we_i :
+ wbm1_sel ? wbm1_we_i :
+ wbm2_sel ? wbm2_we_i :
+ wbm3_sel ? wbm3_we_i :
+ wbm4_sel ? wbm4_we_i :
+ 1'b0;
+
+assign wbs_sel_o = wbm0_sel ? wbm0_sel_i :
+ wbm1_sel ? wbm1_sel_i :
+ wbm2_sel ? wbm2_sel_i :
+ wbm3_sel ? wbm3_sel_i :
+ wbm4_sel ? wbm4_sel_i :
+ {SELECT_WIDTH{1'b0}};
+
+assign wbs_stb_o = wbm0_sel ? wbm0_stb_i :
+ wbm1_sel ? wbm1_stb_i :
+ wbm2_sel ? wbm2_stb_i :
+ wbm3_sel ? wbm3_stb_i :
+ wbm4_sel ? wbm4_stb_i :
+ 1'b0;
+
+assign wbs_cyc_o = wbm0_sel ? 1'b1 :
+ wbm1_sel ? 1'b1 :
+ wbm2_sel ? 1'b1 :
+ wbm3_sel ? 1'b1 :
+ wbm4_sel ? 1'b1 :
+ 1'b0;
+
+// arbiter instance
+arbiter #(
+ .PORTS(5),
+ .TYPE(ARB_TYPE),
+ .BLOCK("REQUEST"),
+ .LSB_PRIORITY(LSB_PRIORITY)
+)
+arb_inst (
+ .clk(clk),
+ .rst(rst),
+ .request(request),
+ .acknowledge(),
+ .grant(grant),
+ .grant_valid(grant_valid),
+ .grant_encoded()
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_arbiter_8.v b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_8.v
new file mode 100644
index 0000000..0114a11
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_arbiter_8.v
@@ -0,0 +1,318 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 8 port arbiter
+ */
+module wb_arbiter_8 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8), // width of word select bus (1, 2, 4, or 8)
+ parameter ARB_TYPE = "PRIORITY", // arbitration type: "PRIORITY" or "ROUND_ROBIN"
+ parameter LSB_PRIORITY = "HIGH" // LSB priority: "LOW", "HIGH"
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master 0 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm0_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm0_dat_o, // DAT_O() data out
+ input wire wbm0_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm0_sel_i, // SEL_I() select input
+ input wire wbm0_stb_i, // STB_I strobe input
+ output wire wbm0_ack_o, // ACK_O acknowledge output
+ output wire wbm0_err_o, // ERR_O error output
+ output wire wbm0_rty_o, // RTY_O retry output
+ input wire wbm0_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 1 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm1_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm1_dat_o, // DAT_O() data out
+ input wire wbm1_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm1_sel_i, // SEL_I() select input
+ input wire wbm1_stb_i, // STB_I strobe input
+ output wire wbm1_ack_o, // ACK_O acknowledge output
+ output wire wbm1_err_o, // ERR_O error output
+ output wire wbm1_rty_o, // RTY_O retry output
+ input wire wbm1_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 2 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm2_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm2_dat_o, // DAT_O() data out
+ input wire wbm2_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm2_sel_i, // SEL_I() select input
+ input wire wbm2_stb_i, // STB_I strobe input
+ output wire wbm2_ack_o, // ACK_O acknowledge output
+ output wire wbm2_err_o, // ERR_O error output
+ output wire wbm2_rty_o, // RTY_O retry output
+ input wire wbm2_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 3 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm3_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm3_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm3_dat_o, // DAT_O() data out
+ input wire wbm3_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm3_sel_i, // SEL_I() select input
+ input wire wbm3_stb_i, // STB_I strobe input
+ output wire wbm3_ack_o, // ACK_O acknowledge output
+ output wire wbm3_err_o, // ERR_O error output
+ output wire wbm3_rty_o, // RTY_O retry output
+ input wire wbm3_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 4 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm4_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm4_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm4_dat_o, // DAT_O() data out
+ input wire wbm4_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm4_sel_i, // SEL_I() select input
+ input wire wbm4_stb_i, // STB_I strobe input
+ output wire wbm4_ack_o, // ACK_O acknowledge output
+ output wire wbm4_err_o, // ERR_O error output
+ output wire wbm4_rty_o, // RTY_O retry output
+ input wire wbm4_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 5 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm5_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm5_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm5_dat_o, // DAT_O() data out
+ input wire wbm5_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm5_sel_i, // SEL_I() select input
+ input wire wbm5_stb_i, // STB_I strobe input
+ output wire wbm5_ack_o, // ACK_O acknowledge output
+ output wire wbm5_err_o, // ERR_O error output
+ output wire wbm5_rty_o, // RTY_O retry output
+ input wire wbm5_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 6 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm6_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm6_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm6_dat_o, // DAT_O() data out
+ input wire wbm6_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm6_sel_i, // SEL_I() select input
+ input wire wbm6_stb_i, // STB_I strobe input
+ output wire wbm6_ack_o, // ACK_O acknowledge output
+ output wire wbm6_err_o, // ERR_O error output
+ output wire wbm6_rty_o, // RTY_O retry output
+ input wire wbm6_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone master 7 input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm7_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm7_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm7_dat_o, // DAT_O() data out
+ input wire wbm7_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm7_sel_i, // SEL_I() select input
+ input wire wbm7_stb_i, // STB_I strobe input
+ output wire wbm7_ack_o, // ACK_O acknowledge output
+ output wire wbm7_err_o, // ERR_O error output
+ output wire wbm7_rty_o, // RTY_O retry output
+ input wire wbm7_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
+ output wire wbs_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
+ output wire wbs_stb_o, // STB_O strobe output
+ input wire wbs_ack_i, // ACK_I acknowledge input
+ input wire wbs_err_i, // ERR_I error input
+ input wire wbs_rty_i, // RTY_I retry input
+ output wire wbs_cyc_o // CYC_O cycle output
+);
+
+wire [7:0] request;
+wire [7:0] grant;
+
+assign request[0] = wbm0_cyc_i;
+assign request[1] = wbm1_cyc_i;
+assign request[2] = wbm2_cyc_i;
+assign request[3] = wbm3_cyc_i;
+assign request[4] = wbm4_cyc_i;
+assign request[5] = wbm5_cyc_i;
+assign request[6] = wbm6_cyc_i;
+assign request[7] = wbm7_cyc_i;
+
+wire wbm0_sel = grant[0] & grant_valid;
+wire wbm1_sel = grant[1] & grant_valid;
+wire wbm2_sel = grant[2] & grant_valid;
+wire wbm3_sel = grant[3] & grant_valid;
+wire wbm4_sel = grant[4] & grant_valid;
+wire wbm5_sel = grant[5] & grant_valid;
+wire wbm6_sel = grant[6] & grant_valid;
+wire wbm7_sel = grant[7] & grant_valid;
+
+// master 0
+assign wbm0_dat_o = wbs_dat_i;
+assign wbm0_ack_o = wbs_ack_i & wbm0_sel;
+assign wbm0_err_o = wbs_err_i & wbm0_sel;
+assign wbm0_rty_o = wbs_rty_i & wbm0_sel;
+
+// master 1
+assign wbm1_dat_o = wbs_dat_i;
+assign wbm1_ack_o = wbs_ack_i & wbm1_sel;
+assign wbm1_err_o = wbs_err_i & wbm1_sel;
+assign wbm1_rty_o = wbs_rty_i & wbm1_sel;
+
+// master 2
+assign wbm2_dat_o = wbs_dat_i;
+assign wbm2_ack_o = wbs_ack_i & wbm2_sel;
+assign wbm2_err_o = wbs_err_i & wbm2_sel;
+assign wbm2_rty_o = wbs_rty_i & wbm2_sel;
+
+// master 3
+assign wbm3_dat_o = wbs_dat_i;
+assign wbm3_ack_o = wbs_ack_i & wbm3_sel;
+assign wbm3_err_o = wbs_err_i & wbm3_sel;
+assign wbm3_rty_o = wbs_rty_i & wbm3_sel;
+
+// master 4
+assign wbm4_dat_o = wbs_dat_i;
+assign wbm4_ack_o = wbs_ack_i & wbm4_sel;
+assign wbm4_err_o = wbs_err_i & wbm4_sel;
+assign wbm4_rty_o = wbs_rty_i & wbm4_sel;
+
+// master 5
+assign wbm5_dat_o = wbs_dat_i;
+assign wbm5_ack_o = wbs_ack_i & wbm5_sel;
+assign wbm5_err_o = wbs_err_i & wbm5_sel;
+assign wbm5_rty_o = wbs_rty_i & wbm5_sel;
+
+// master 6
+assign wbm6_dat_o = wbs_dat_i;
+assign wbm6_ack_o = wbs_ack_i & wbm6_sel;
+assign wbm6_err_o = wbs_err_i & wbm6_sel;
+assign wbm6_rty_o = wbs_rty_i & wbm6_sel;
+
+// master 7
+assign wbm7_dat_o = wbs_dat_i;
+assign wbm7_ack_o = wbs_ack_i & wbm7_sel;
+assign wbm7_err_o = wbs_err_i & wbm7_sel;
+assign wbm7_rty_o = wbs_rty_i & wbm7_sel;
+
+// slave
+assign wbs_adr_o = wbm0_sel ? wbm0_adr_i :
+ wbm1_sel ? wbm1_adr_i :
+ wbm2_sel ? wbm2_adr_i :
+ wbm3_sel ? wbm3_adr_i :
+ wbm4_sel ? wbm4_adr_i :
+ wbm5_sel ? wbm5_adr_i :
+ wbm6_sel ? wbm6_adr_i :
+ wbm7_sel ? wbm7_adr_i :
+ {ADDR_WIDTH{1'b0}};
+
+assign wbs_dat_o = wbm0_sel ? wbm0_dat_i :
+ wbm1_sel ? wbm1_dat_i :
+ wbm2_sel ? wbm2_dat_i :
+ wbm3_sel ? wbm3_dat_i :
+ wbm4_sel ? wbm4_dat_i :
+ wbm5_sel ? wbm5_dat_i :
+ wbm6_sel ? wbm6_dat_i :
+ wbm7_sel ? wbm7_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbs_we_o = wbm0_sel ? wbm0_we_i :
+ wbm1_sel ? wbm1_we_i :
+ wbm2_sel ? wbm2_we_i :
+ wbm3_sel ? wbm3_we_i :
+ wbm4_sel ? wbm4_we_i :
+ wbm5_sel ? wbm5_we_i :
+ wbm6_sel ? wbm6_we_i :
+ wbm7_sel ? wbm7_we_i :
+ 1'b0;
+
+assign wbs_sel_o = wbm0_sel ? wbm0_sel_i :
+ wbm1_sel ? wbm1_sel_i :
+ wbm2_sel ? wbm2_sel_i :
+ wbm3_sel ? wbm3_sel_i :
+ wbm4_sel ? wbm4_sel_i :
+ wbm5_sel ? wbm5_sel_i :
+ wbm6_sel ? wbm6_sel_i :
+ wbm7_sel ? wbm7_sel_i :
+ {SELECT_WIDTH{1'b0}};
+
+assign wbs_stb_o = wbm0_sel ? wbm0_stb_i :
+ wbm1_sel ? wbm1_stb_i :
+ wbm2_sel ? wbm2_stb_i :
+ wbm3_sel ? wbm3_stb_i :
+ wbm4_sel ? wbm4_stb_i :
+ wbm5_sel ? wbm5_stb_i :
+ wbm6_sel ? wbm6_stb_i :
+ wbm7_sel ? wbm7_stb_i :
+ 1'b0;
+
+assign wbs_cyc_o = wbm0_sel ? 1'b1 :
+ wbm1_sel ? 1'b1 :
+ wbm2_sel ? 1'b1 :
+ wbm3_sel ? 1'b1 :
+ wbm4_sel ? 1'b1 :
+ wbm5_sel ? 1'b1 :
+ wbm6_sel ? 1'b1 :
+ wbm7_sel ? 1'b1 :
+ 1'b0;
+
+// arbiter instance
+arbiter #(
+ .PORTS(8),
+ .TYPE(ARB_TYPE),
+ .BLOCK("REQUEST"),
+ .LSB_PRIORITY(LSB_PRIORITY)
+)
+arb_inst (
+ .clk(clk),
+ .rst(rst),
+ .request(request),
+ .acknowledge(),
+ .grant(grant),
+ .grant_valid(grant_valid),
+ .grant_encoded()
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_async_reg.v b/ip/third_party/verilog-wishbone/rtl/wb_async_reg.v
new file mode 100644
index 0000000..1c37832
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_async_reg.v
@@ -0,0 +1,225 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Wishbone register
+ */
+module wb_async_reg #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ // master side
+ input wire wbm_clk,
+ input wire wbm_rst,
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ // slave side
+ input wire wbs_clk,
+ input wire wbs_rst,
+ output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address
+ input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
+ output wire wbs_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
+ output wire wbs_stb_o, // STB_O strobe output
+ input wire wbs_ack_i, // ACK_I acknowledge input
+ input wire wbs_err_i, // ERR_I error input
+ input wire wbs_rty_i, // RTY_I retry input
+ output wire wbs_cyc_o // CYC_O cycle output
+);
+
+reg [ADDR_WIDTH-1:0] wbm_adr_i_reg = 0;
+reg [DATA_WIDTH-1:0] wbm_dat_i_reg = 0;
+reg [DATA_WIDTH-1:0] wbm_dat_o_reg = 0;
+reg wbm_we_i_reg = 0;
+reg [SELECT_WIDTH-1:0] wbm_sel_i_reg = 0;
+reg wbm_stb_i_reg = 0;
+reg wbm_ack_o_reg = 0;
+reg wbm_err_o_reg = 0;
+reg wbm_rty_o_reg = 0;
+reg wbm_cyc_i_reg = 0;
+
+reg wbm_done_sync1 = 0;
+reg wbm_done_sync2 = 0;
+reg wbm_done_sync3 = 0;
+
+reg [ADDR_WIDTH-1:0] wbs_adr_o_reg = 0;
+reg [DATA_WIDTH-1:0] wbs_dat_i_reg = 0;
+reg [DATA_WIDTH-1:0] wbs_dat_o_reg = 0;
+reg wbs_we_o_reg = 0;
+reg [SELECT_WIDTH-1:0] wbs_sel_o_reg = 0;
+reg wbs_stb_o_reg = 0;
+reg wbs_ack_i_reg = 0;
+reg wbs_err_i_reg = 0;
+reg wbs_rty_i_reg = 0;
+reg wbs_cyc_o_reg = 0;
+
+reg wbs_cyc_o_sync1 = 0;
+reg wbs_cyc_o_sync2 = 0;
+reg wbs_cyc_o_sync3 = 0;
+
+reg wbs_stb_o_sync1 = 0;
+reg wbs_stb_o_sync2 = 0;
+reg wbs_stb_o_sync3 = 0;
+
+reg wbs_done_reg = 0;
+
+assign wbm_dat_o = wbm_dat_o_reg;
+assign wbm_ack_o = wbm_ack_o_reg;
+assign wbm_err_o = wbm_err_o_reg;
+assign wbm_rty_o = wbm_rty_o_reg;
+
+assign wbs_adr_o = wbs_adr_o_reg;
+assign wbs_dat_o = wbs_dat_o_reg;
+assign wbs_we_o = wbs_we_o_reg;
+assign wbs_sel_o = wbs_sel_o_reg;
+assign wbs_stb_o = wbs_stb_o_reg;
+assign wbs_cyc_o = wbs_cyc_o_reg;
+
+// master side logic
+always @(posedge wbm_clk) begin
+ if (wbm_rst) begin
+ wbm_adr_i_reg <= 0;
+ wbm_dat_i_reg <= 0;
+ wbm_dat_o_reg <= 0;
+ wbm_we_i_reg <= 0;
+ wbm_sel_i_reg <= 0;
+ wbm_stb_i_reg <= 0;
+ wbm_ack_o_reg <= 0;
+ wbm_err_o_reg <= 0;
+ wbm_rty_o_reg <= 0;
+ wbm_cyc_i_reg <= 0;
+ end else begin
+ if (wbm_cyc_i_reg & wbm_stb_i_reg) begin
+ // cycle - hold master
+ if (wbm_done_sync2 & ~wbm_done_sync3) begin
+ // end of cycle - store slave
+ wbm_dat_o_reg <= wbs_dat_i_reg;
+ wbm_ack_o_reg <= wbs_ack_i_reg;
+ wbm_err_o_reg <= wbs_err_i_reg;
+ wbm_rty_o_reg <= wbs_rty_i_reg;
+ wbm_we_i_reg <= 0;
+ wbm_stb_i_reg <= 0;
+ end
+ end else begin
+ // idle - store master
+ wbm_adr_i_reg <= wbm_adr_i;
+ wbm_dat_i_reg <= wbm_dat_i;
+ wbm_dat_o_reg <= 0;
+ wbm_we_i_reg <= wbm_we_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
+ wbm_sel_i_reg <= wbm_sel_i;
+ wbm_stb_i_reg <= wbm_stb_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
+ wbm_ack_o_reg <= 0;
+ wbm_err_o_reg <= 0;
+ wbm_rty_o_reg <= 0;
+ wbm_cyc_i_reg <= wbm_cyc_i;
+ end
+ end
+
+ // synchronize signals
+ wbm_done_sync1 <= wbs_done_reg;
+ wbm_done_sync2 <= wbm_done_sync1;
+ wbm_done_sync3 <= wbm_done_sync2;
+end
+
+// slave side logic
+always @(posedge wbs_clk) begin
+ if (wbs_rst) begin
+ wbs_adr_o_reg <= 0;
+ wbs_dat_i_reg <= 0;
+ wbs_dat_o_reg <= 0;
+ wbs_we_o_reg <= 0;
+ wbs_sel_o_reg <= 0;
+ wbs_stb_o_reg <= 0;
+ wbs_ack_i_reg <= 0;
+ wbs_err_i_reg <= 0;
+ wbs_rty_i_reg <= 0;
+ wbs_cyc_o_reg <= 0;
+ wbs_done_reg <= 0;
+ end else begin
+ if (wbs_ack_i | wbs_err_i | wbs_rty_i) begin
+ // end of cycle - store slave
+ wbs_dat_i_reg <= wbs_dat_i;
+ wbs_ack_i_reg <= wbs_ack_i;
+ wbs_err_i_reg <= wbs_err_i;
+ wbs_rty_i_reg <= wbs_rty_i;
+ wbs_we_o_reg <= 0;
+ wbs_stb_o_reg <= 0;
+ wbs_done_reg <= 1;
+ end else if (wbs_stb_o_sync2 & ~wbs_stb_o_sync3) begin
+ // beginning of cycle - store master
+ wbs_adr_o_reg <= wbm_adr_i_reg;
+ wbs_dat_i_reg <= 0;
+ wbs_dat_o_reg <= wbm_dat_i_reg;
+ wbs_we_o_reg <= wbm_we_i_reg;
+ wbs_sel_o_reg <= wbm_sel_i_reg;
+ wbs_stb_o_reg <= wbm_stb_i_reg;
+ wbs_ack_i_reg <= 0;
+ wbs_err_i_reg <= 0;
+ wbs_rty_i_reg <= 0;
+ wbs_cyc_o_reg <= wbm_cyc_i_reg;
+ wbs_done_reg <= 0;
+ end else if (~wbs_cyc_o_sync2 & wbs_cyc_o_sync3) begin
+ // cyc deassert
+ wbs_adr_o_reg <= 0;
+ wbs_dat_i_reg <= 0;
+ wbs_dat_o_reg <= 0;
+ wbs_we_o_reg <= 0;
+ wbs_sel_o_reg <= 0;
+ wbs_stb_o_reg <= 0;
+ wbs_ack_i_reg <= 0;
+ wbs_err_i_reg <= 0;
+ wbs_rty_i_reg <= 0;
+ wbs_cyc_o_reg <= 0;
+ wbs_done_reg <= 0;
+ end
+ end
+
+ // synchronize signals
+ wbs_cyc_o_sync1 <= wbm_cyc_i_reg;
+ wbs_cyc_o_sync2 <= wbs_cyc_o_sync1;
+ wbs_cyc_o_sync3 <= wbs_cyc_o_sync2;
+
+ wbs_stb_o_sync1 <= wbm_stb_i_reg;
+ wbs_stb_o_sync2 <= wbs_stb_o_sync1;
+ wbs_stb_o_sync3 <= wbs_stb_o_sync2;
+end
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_dp_ram.v b/ip/third_party/verilog-wishbone/rtl/wb_dp_ram.v
new file mode 100644
index 0000000..370e973
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_dp_ram.v
@@ -0,0 +1,127 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Wishbone dual port RAM
+ */
+module wb_dp_ram #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 16, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ // port A
+ input wire a_clk,
+ input wire [ADDR_WIDTH-1:0] a_adr_i, // ADR_I() address
+ input wire [DATA_WIDTH-1:0] a_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] a_dat_o, // DAT_O() data out
+ input wire a_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] a_sel_i, // SEL_I() select input
+ input wire a_stb_i, // STB_I strobe input
+ output wire a_ack_o, // ACK_O acknowledge output
+ input wire a_cyc_i, // CYC_I cycle input
+
+ // port B
+ input wire b_clk,
+ input wire [ADDR_WIDTH-1:0] b_adr_i, // ADR_I() address
+ input wire [DATA_WIDTH-1:0] b_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] b_dat_o, // DAT_O() data out
+ input wire b_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] b_sel_i, // SEL_I() select input
+ input wire b_stb_i, // STB_I strobe input
+ output wire b_ack_o, // ACK_O acknowledge output
+ input wire b_cyc_i // CYC_I cycle input
+);
+
+// for interfaces that are more than one word wide, disable address lines
+parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(SELECT_WIDTH);
+// width of data port in words (1, 2, 4, or 8)
+parameter WORD_WIDTH = SELECT_WIDTH;
+// size of words (8, 16, 32, or 64 bits)
+parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
+
+reg [DATA_WIDTH-1:0] a_dat_o_reg = {DATA_WIDTH{1'b0}};
+reg a_ack_o_reg = 1'b0;
+
+reg [DATA_WIDTH-1:0] b_dat_o_reg = {DATA_WIDTH{1'b0}};
+reg b_ack_o_reg = 1'b0;
+
+// (* RAM_STYLE="BLOCK" *)
+reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
+
+wire [VALID_ADDR_WIDTH-1:0] a_adr_i_valid = a_adr_i >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+wire [VALID_ADDR_WIDTH-1:0] b_adr_i_valid = b_adr_i >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+
+assign a_dat_o = a_dat_o_reg;
+assign a_ack_o = a_ack_o_reg;
+
+assign b_dat_o = b_dat_o_reg;
+assign b_ack_o = b_ack_o_reg;
+
+integer i, j;
+
+initial begin
+ // two nested loops for smaller number of iterations per loop
+ // workaround for synthesizer complaints about large loop counts
+ for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
+ for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
+ mem[j] = 0;
+ end
+ end
+end
+
+// port A
+always @(posedge a_clk) begin
+ a_ack_o_reg <= 1'b0;
+ for (i = 0; i < WORD_WIDTH; i = i + 1) begin
+ if (a_cyc_i & a_stb_i & ~a_ack_o) begin
+ if (a_we_i & a_sel_i[i]) begin
+ mem[a_adr_i_valid][WORD_SIZE*i +: WORD_SIZE] <= a_dat_i[WORD_SIZE*i +: WORD_SIZE];
+ end
+ a_dat_o_reg[WORD_SIZE*i +: WORD_SIZE] <= mem[a_adr_i_valid][WORD_SIZE*i +: WORD_SIZE];
+ a_ack_o_reg <= 1'b1;
+ end
+ end
+end
+
+// port B
+always @(posedge b_clk) begin
+ b_ack_o_reg <= 1'b0;
+ for (i = 0; i < WORD_WIDTH; i = i + 1) begin
+ if (b_cyc_i & b_stb_i & ~b_ack_o) begin
+ if (b_we_i & b_sel_i[i]) begin
+ mem[b_adr_i_valid][WORD_SIZE*i +: WORD_SIZE] <= b_dat_i[WORD_SIZE*i +: WORD_SIZE];
+ end
+ b_dat_o_reg[WORD_SIZE*i +: WORD_SIZE] <= mem[b_adr_i_valid][WORD_SIZE*i +: WORD_SIZE];
+ b_ack_o_reg <= 1'b1;
+ end
+ end
+end
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_mux.py b/ip/third_party/verilog-wishbone/rtl/wb_mux.py
new file mode 100755
index 0000000..ec458f9
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_mux.py
@@ -0,0 +1,166 @@
+#!/usr/bin/env python
+"""
+Generates a Wishbone multiplexer with the specified number of ports
+"""
+
+from __future__ import print_function
+
+import argparse
+import math
+from jinja2 import Template
+
+def main():
+ parser = argparse.ArgumentParser(description=__doc__.strip())
+ parser.add_argument('-p', '--ports', type=int, default=2, help="number of ports")
+ parser.add_argument('-n', '--name', type=str, help="module name")
+ parser.add_argument('-o', '--output', type=str, help="output file name")
+
+ args = parser.parse_args()
+
+ try:
+ generate(**args.__dict__)
+ except IOError as ex:
+ print(ex)
+ exit(1)
+
+def generate(ports=2, name=None, output=None):
+ if name is None:
+ name = "wb_mux_{0}".format(ports)
+
+ if output is None:
+ output = name + ".v"
+
+ print("Opening file '{0}'...".format(output))
+
+ output_file = open(output, 'w')
+
+ print("Generating {0} port Wishbone mux {1}...".format(ports, name))
+
+ select_width = int(math.ceil(math.log(ports, 2)))
+
+ t = Template(u"""/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone {{n}} port multiplexer
+ */
+module {{name}} #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+ {%- for p in ports %}
+
+ /*
+ * Wishbone slave {{p}} output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs{{p}}_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs{{p}}_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs{{p}}_dat_o, // DAT_O() data out
+ output wire wbs{{p}}_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs{{p}}_sel_o, // SEL_O() select output
+ output wire wbs{{p}}_stb_o, // STB_O strobe output
+ input wire wbs{{p}}_ack_i, // ACK_I acknowledge input
+ input wire wbs{{p}}_err_i, // ERR_I error input
+ input wire wbs{{p}}_rty_i, // RTY_I retry input
+ output wire wbs{{p}}_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave {{p}} address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs{{p}}_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs{{p}}_addr_msk{% if not loop.last %},{% else %} {% endif %} // Slave address prefix mask
+ {%- endfor %}
+);
+{% for p in ports %}
+wire wbs{{p}}_match = ~|((wbm_adr_i ^ wbs{{p}}_addr) & wbs{{p}}_addr_msk);
+{%- endfor %}
+{% for p in ports %}
+wire wbs{{p}}_sel = wbs{{p}}_match{% if p > 0 %} & ~({% for q in range(p) %}wbs{{q}}_match{% if not loop.last %} | {% endif %}{% endfor %}){% endif %};
+{%- endfor %}
+
+wire master_cycle = wbm_cyc_i & wbm_stb_i;
+
+wire select_error = ~({% for p in ports %}wbs{{p}}_sel{% if not loop.last %} | {% endif %}{% endfor %}) & master_cycle;
+
+// master
+assign wbm_dat_o = {% for p in ports %}wbs{{p}}_sel ? wbs{{p}}_dat_i :
+ {% endfor %}{DATA_WIDTH{1'b0}};
+
+assign wbm_ack_o = {% for p in ports %}wbs{{p}}_ack_i{% if not loop.last %} |
+ {% endif %}{% endfor %};
+
+assign wbm_err_o = {% for p in ports %}wbs{{p}}_err_i |
+ {% endfor %}select_error;
+
+assign wbm_rty_o = {% for p in ports %}wbs{{p}}_rty_i{% if not loop.last %} |
+ {% endif %}{% endfor %};
+{% for p in ports %}
+// slave {{p}}
+assign wbs{{p}}_adr_o = wbm_adr_i;
+assign wbs{{p}}_dat_o = wbm_dat_i;
+assign wbs{{p}}_we_o = wbm_we_i & wbs{{p}}_sel;
+assign wbs{{p}}_sel_o = wbm_sel_i;
+assign wbs{{p}}_stb_o = wbm_stb_i & wbs{{p}}_sel;
+assign wbs{{p}}_cyc_o = wbm_cyc_i & wbs{{p}}_sel;
+{% endfor %}
+
+endmodule
+
+""")
+
+ output_file.write(t.render(
+ n=ports,
+ w=select_width,
+ name=name,
+ ports=range(ports)
+ ))
+
+ print("Done")
+
+if __name__ == "__main__":
+ main()
+
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_mux_2.v b/ip/third_party/verilog-wishbone/rtl/wb_mux_2.v
new file mode 100644
index 0000000..4342ba4
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_mux_2.v
@@ -0,0 +1,139 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 2 port multiplexer
+ */
+module wb_mux_2 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave 0 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
+ output wire wbs0_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
+ output wire wbs0_stb_o, // STB_O strobe output
+ input wire wbs0_ack_i, // ACK_I acknowledge input
+ input wire wbs0_err_i, // ERR_I error input
+ input wire wbs0_rty_i, // RTY_I retry input
+ output wire wbs0_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 0 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 1 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
+ output wire wbs1_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
+ output wire wbs1_stb_o, // STB_O strobe output
+ input wire wbs1_ack_i, // ACK_I acknowledge input
+ input wire wbs1_err_i, // ERR_I error input
+ input wire wbs1_rty_i, // RTY_I retry input
+ output wire wbs1_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 1 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs1_addr_msk // Slave address prefix mask
+);
+
+wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
+wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
+
+wire wbs0_sel = wbs0_match;
+wire wbs1_sel = wbs1_match & ~(wbs0_match);
+
+wire master_cycle = wbm_cyc_i & wbm_stb_i;
+
+wire select_error = ~(wbs0_sel | wbs1_sel) & master_cycle;
+
+// master
+assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
+ wbs1_sel ? wbs1_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbm_ack_o = wbs0_ack_i |
+ wbs1_ack_i;
+
+assign wbm_err_o = wbs0_err_i |
+ wbs1_err_i |
+ select_error;
+
+assign wbm_rty_o = wbs0_rty_i |
+ wbs1_rty_i;
+
+// slave 0
+assign wbs0_adr_o = wbm_adr_i;
+assign wbs0_dat_o = wbm_dat_i;
+assign wbs0_we_o = wbm_we_i & wbs0_sel;
+assign wbs0_sel_o = wbm_sel_i;
+assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
+assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
+
+// slave 1
+assign wbs1_adr_o = wbm_adr_i;
+assign wbs1_dat_o = wbm_dat_i;
+assign wbs1_we_o = wbm_we_i & wbs1_sel;
+assign wbs1_sel_o = wbm_sel_i;
+assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
+assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
+
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_mux_3.v b/ip/third_party/verilog-wishbone/rtl/wb_mux_3.v
new file mode 100644
index 0000000..3afeb31
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_mux_3.v
@@ -0,0 +1,173 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 3 port multiplexer
+ */
+module wb_mux_3 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave 0 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
+ output wire wbs0_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
+ output wire wbs0_stb_o, // STB_O strobe output
+ input wire wbs0_ack_i, // ACK_I acknowledge input
+ input wire wbs0_err_i, // ERR_I error input
+ input wire wbs0_rty_i, // RTY_I retry input
+ output wire wbs0_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 0 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 1 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
+ output wire wbs1_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
+ output wire wbs1_stb_o, // STB_O strobe output
+ input wire wbs1_ack_i, // ACK_I acknowledge input
+ input wire wbs1_err_i, // ERR_I error input
+ input wire wbs1_rty_i, // RTY_I retry input
+ output wire wbs1_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 1 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs1_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 2 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs2_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs2_dat_o, // DAT_O() data out
+ output wire wbs2_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs2_sel_o, // SEL_O() select output
+ output wire wbs2_stb_o, // STB_O strobe output
+ input wire wbs2_ack_i, // ACK_I acknowledge input
+ input wire wbs2_err_i, // ERR_I error input
+ input wire wbs2_rty_i, // RTY_I retry input
+ output wire wbs2_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 2 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs2_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs2_addr_msk // Slave address prefix mask
+);
+
+wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
+wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
+wire wbs2_match = ~|((wbm_adr_i ^ wbs2_addr) & wbs2_addr_msk);
+
+wire wbs0_sel = wbs0_match;
+wire wbs1_sel = wbs1_match & ~(wbs0_match);
+wire wbs2_sel = wbs2_match & ~(wbs0_match | wbs1_match);
+
+wire master_cycle = wbm_cyc_i & wbm_stb_i;
+
+wire select_error = ~(wbs0_sel | wbs1_sel | wbs2_sel) & master_cycle;
+
+// master
+assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
+ wbs1_sel ? wbs1_dat_i :
+ wbs2_sel ? wbs2_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbm_ack_o = wbs0_ack_i |
+ wbs1_ack_i |
+ wbs2_ack_i;
+
+assign wbm_err_o = wbs0_err_i |
+ wbs1_err_i |
+ wbs2_err_i |
+ select_error;
+
+assign wbm_rty_o = wbs0_rty_i |
+ wbs1_rty_i |
+ wbs2_rty_i;
+
+// slave 0
+assign wbs0_adr_o = wbm_adr_i;
+assign wbs0_dat_o = wbm_dat_i;
+assign wbs0_we_o = wbm_we_i & wbs0_sel;
+assign wbs0_sel_o = wbm_sel_i;
+assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
+assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
+
+// slave 1
+assign wbs1_adr_o = wbm_adr_i;
+assign wbs1_dat_o = wbm_dat_i;
+assign wbs1_we_o = wbm_we_i & wbs1_sel;
+assign wbs1_sel_o = wbm_sel_i;
+assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
+assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
+
+// slave 2
+assign wbs2_adr_o = wbm_adr_i;
+assign wbs2_dat_o = wbm_dat_i;
+assign wbs2_we_o = wbm_we_i & wbs2_sel;
+assign wbs2_sel_o = wbm_sel_i;
+assign wbs2_stb_o = wbm_stb_i & wbs2_sel;
+assign wbs2_cyc_o = wbm_cyc_i & wbs2_sel;
+
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_mux_4.v b/ip/third_party/verilog-wishbone/rtl/wb_mux_4.v
new file mode 100644
index 0000000..38b040b
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_mux_4.v
@@ -0,0 +1,207 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 4 port multiplexer
+ */
+module wb_mux_4 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave 0 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
+ output wire wbs0_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
+ output wire wbs0_stb_o, // STB_O strobe output
+ input wire wbs0_ack_i, // ACK_I acknowledge input
+ input wire wbs0_err_i, // ERR_I error input
+ input wire wbs0_rty_i, // RTY_I retry input
+ output wire wbs0_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 0 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 1 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
+ output wire wbs1_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
+ output wire wbs1_stb_o, // STB_O strobe output
+ input wire wbs1_ack_i, // ACK_I acknowledge input
+ input wire wbs1_err_i, // ERR_I error input
+ input wire wbs1_rty_i, // RTY_I retry input
+ output wire wbs1_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 1 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs1_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 2 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs2_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs2_dat_o, // DAT_O() data out
+ output wire wbs2_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs2_sel_o, // SEL_O() select output
+ output wire wbs2_stb_o, // STB_O strobe output
+ input wire wbs2_ack_i, // ACK_I acknowledge input
+ input wire wbs2_err_i, // ERR_I error input
+ input wire wbs2_rty_i, // RTY_I retry input
+ output wire wbs2_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 2 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs2_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs2_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 3 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs3_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs3_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs3_dat_o, // DAT_O() data out
+ output wire wbs3_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs3_sel_o, // SEL_O() select output
+ output wire wbs3_stb_o, // STB_O strobe output
+ input wire wbs3_ack_i, // ACK_I acknowledge input
+ input wire wbs3_err_i, // ERR_I error input
+ input wire wbs3_rty_i, // RTY_I retry input
+ output wire wbs3_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 3 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs3_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs3_addr_msk // Slave address prefix mask
+);
+
+wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
+wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
+wire wbs2_match = ~|((wbm_adr_i ^ wbs2_addr) & wbs2_addr_msk);
+wire wbs3_match = ~|((wbm_adr_i ^ wbs3_addr) & wbs3_addr_msk);
+
+wire wbs0_sel = wbs0_match;
+wire wbs1_sel = wbs1_match & ~(wbs0_match);
+wire wbs2_sel = wbs2_match & ~(wbs0_match | wbs1_match);
+wire wbs3_sel = wbs3_match & ~(wbs0_match | wbs1_match | wbs2_match);
+
+wire master_cycle = wbm_cyc_i & wbm_stb_i;
+
+wire select_error = ~(wbs0_sel | wbs1_sel | wbs2_sel | wbs3_sel) & master_cycle;
+
+// master
+assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
+ wbs1_sel ? wbs1_dat_i :
+ wbs2_sel ? wbs2_dat_i :
+ wbs3_sel ? wbs3_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbm_ack_o = wbs0_ack_i |
+ wbs1_ack_i |
+ wbs2_ack_i |
+ wbs3_ack_i;
+
+assign wbm_err_o = wbs0_err_i |
+ wbs1_err_i |
+ wbs2_err_i |
+ wbs3_err_i |
+ select_error;
+
+assign wbm_rty_o = wbs0_rty_i |
+ wbs1_rty_i |
+ wbs2_rty_i |
+ wbs3_rty_i;
+
+// slave 0
+assign wbs0_adr_o = wbm_adr_i;
+assign wbs0_dat_o = wbm_dat_i;
+assign wbs0_we_o = wbm_we_i & wbs0_sel;
+assign wbs0_sel_o = wbm_sel_i;
+assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
+assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
+
+// slave 1
+assign wbs1_adr_o = wbm_adr_i;
+assign wbs1_dat_o = wbm_dat_i;
+assign wbs1_we_o = wbm_we_i & wbs1_sel;
+assign wbs1_sel_o = wbm_sel_i;
+assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
+assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
+
+// slave 2
+assign wbs2_adr_o = wbm_adr_i;
+assign wbs2_dat_o = wbm_dat_i;
+assign wbs2_we_o = wbm_we_i & wbs2_sel;
+assign wbs2_sel_o = wbm_sel_i;
+assign wbs2_stb_o = wbm_stb_i & wbs2_sel;
+assign wbs2_cyc_o = wbm_cyc_i & wbs2_sel;
+
+// slave 3
+assign wbs3_adr_o = wbm_adr_i;
+assign wbs3_dat_o = wbm_dat_i;
+assign wbs3_we_o = wbm_we_i & wbs3_sel;
+assign wbs3_sel_o = wbm_sel_i;
+assign wbs3_stb_o = wbm_stb_i & wbs3_sel;
+assign wbs3_cyc_o = wbm_cyc_i & wbs3_sel;
+
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_mux_5.v b/ip/third_party/verilog-wishbone/rtl/wb_mux_5.v
new file mode 100644
index 0000000..5c3d8c0
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_mux_5.v
@@ -0,0 +1,241 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 5 port multiplexer
+ */
+module wb_mux_5 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave 0 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
+ output wire wbs0_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
+ output wire wbs0_stb_o, // STB_O strobe output
+ input wire wbs0_ack_i, // ACK_I acknowledge input
+ input wire wbs0_err_i, // ERR_I error input
+ input wire wbs0_rty_i, // RTY_I retry input
+ output wire wbs0_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 0 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 1 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
+ output wire wbs1_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
+ output wire wbs1_stb_o, // STB_O strobe output
+ input wire wbs1_ack_i, // ACK_I acknowledge input
+ input wire wbs1_err_i, // ERR_I error input
+ input wire wbs1_rty_i, // RTY_I retry input
+ output wire wbs1_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 1 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs1_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 2 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs2_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs2_dat_o, // DAT_O() data out
+ output wire wbs2_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs2_sel_o, // SEL_O() select output
+ output wire wbs2_stb_o, // STB_O strobe output
+ input wire wbs2_ack_i, // ACK_I acknowledge input
+ input wire wbs2_err_i, // ERR_I error input
+ input wire wbs2_rty_i, // RTY_I retry input
+ output wire wbs2_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 2 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs2_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs2_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 3 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs3_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs3_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs3_dat_o, // DAT_O() data out
+ output wire wbs3_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs3_sel_o, // SEL_O() select output
+ output wire wbs3_stb_o, // STB_O strobe output
+ input wire wbs3_ack_i, // ACK_I acknowledge input
+ input wire wbs3_err_i, // ERR_I error input
+ input wire wbs3_rty_i, // RTY_I retry input
+ output wire wbs3_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 3 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs3_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs3_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 4 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs4_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs4_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs4_dat_o, // DAT_O() data out
+ output wire wbs4_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs4_sel_o, // SEL_O() select output
+ output wire wbs4_stb_o, // STB_O strobe output
+ input wire wbs4_ack_i, // ACK_I acknowledge input
+ input wire wbs4_err_i, // ERR_I error input
+ input wire wbs4_rty_i, // RTY_I retry input
+ output wire wbs4_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 4 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs4_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs4_addr_msk // Slave address prefix mask
+);
+
+wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
+wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
+wire wbs2_match = ~|((wbm_adr_i ^ wbs2_addr) & wbs2_addr_msk);
+wire wbs3_match = ~|((wbm_adr_i ^ wbs3_addr) & wbs3_addr_msk);
+wire wbs4_match = ~|((wbm_adr_i ^ wbs4_addr) & wbs4_addr_msk);
+
+wire wbs0_sel = wbs0_match;
+wire wbs1_sel = wbs1_match & ~(wbs0_match);
+wire wbs2_sel = wbs2_match & ~(wbs0_match | wbs1_match);
+wire wbs3_sel = wbs3_match & ~(wbs0_match | wbs1_match | wbs2_match);
+wire wbs4_sel = wbs4_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match);
+
+wire master_cycle = wbm_cyc_i & wbm_stb_i;
+
+wire select_error = ~(wbs0_sel | wbs1_sel | wbs2_sel | wbs3_sel | wbs4_sel) & master_cycle;
+
+// master
+assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
+ wbs1_sel ? wbs1_dat_i :
+ wbs2_sel ? wbs2_dat_i :
+ wbs3_sel ? wbs3_dat_i :
+ wbs4_sel ? wbs4_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbm_ack_o = wbs0_ack_i |
+ wbs1_ack_i |
+ wbs2_ack_i |
+ wbs3_ack_i |
+ wbs4_ack_i;
+
+assign wbm_err_o = wbs0_err_i |
+ wbs1_err_i |
+ wbs2_err_i |
+ wbs3_err_i |
+ wbs4_err_i |
+ select_error;
+
+assign wbm_rty_o = wbs0_rty_i |
+ wbs1_rty_i |
+ wbs2_rty_i |
+ wbs3_rty_i |
+ wbs4_rty_i;
+
+// slave 0
+assign wbs0_adr_o = wbm_adr_i;
+assign wbs0_dat_o = wbm_dat_i;
+assign wbs0_we_o = wbm_we_i & wbs0_sel;
+assign wbs0_sel_o = wbm_sel_i;
+assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
+assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
+
+// slave 1
+assign wbs1_adr_o = wbm_adr_i;
+assign wbs1_dat_o = wbm_dat_i;
+assign wbs1_we_o = wbm_we_i & wbs1_sel;
+assign wbs1_sel_o = wbm_sel_i;
+assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
+assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
+
+// slave 2
+assign wbs2_adr_o = wbm_adr_i;
+assign wbs2_dat_o = wbm_dat_i;
+assign wbs2_we_o = wbm_we_i & wbs2_sel;
+assign wbs2_sel_o = wbm_sel_i;
+assign wbs2_stb_o = wbm_stb_i & wbs2_sel;
+assign wbs2_cyc_o = wbm_cyc_i & wbs2_sel;
+
+// slave 3
+assign wbs3_adr_o = wbm_adr_i;
+assign wbs3_dat_o = wbm_dat_i;
+assign wbs3_we_o = wbm_we_i & wbs3_sel;
+assign wbs3_sel_o = wbm_sel_i;
+assign wbs3_stb_o = wbm_stb_i & wbs3_sel;
+assign wbs3_cyc_o = wbm_cyc_i & wbs3_sel;
+
+// slave 4
+assign wbs4_adr_o = wbm_adr_i;
+assign wbs4_dat_o = wbm_dat_i;
+assign wbs4_we_o = wbm_we_i & wbs4_sel;
+assign wbs4_sel_o = wbm_sel_i;
+assign wbs4_stb_o = wbm_stb_i & wbs4_sel;
+assign wbs4_cyc_o = wbm_cyc_i & wbs4_sel;
+
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_mux_6.v b/ip/third_party/verilog-wishbone/rtl/wb_mux_6.v
new file mode 100644
index 0000000..36fc3b9
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_mux_6.v
@@ -0,0 +1,275 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 6 port multiplexer
+ */
+module wb_mux_6 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave 0 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
+ output wire wbs0_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
+ output wire wbs0_stb_o, // STB_O strobe output
+ input wire wbs0_ack_i, // ACK_I acknowledge input
+ input wire wbs0_err_i, // ERR_I error input
+ input wire wbs0_rty_i, // RTY_I retry input
+ output wire wbs0_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 0 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 1 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
+ output wire wbs1_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
+ output wire wbs1_stb_o, // STB_O strobe output
+ input wire wbs1_ack_i, // ACK_I acknowledge input
+ input wire wbs1_err_i, // ERR_I error input
+ input wire wbs1_rty_i, // RTY_I retry input
+ output wire wbs1_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 1 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs1_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 2 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs2_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs2_dat_o, // DAT_O() data out
+ output wire wbs2_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs2_sel_o, // SEL_O() select output
+ output wire wbs2_stb_o, // STB_O strobe output
+ input wire wbs2_ack_i, // ACK_I acknowledge input
+ input wire wbs2_err_i, // ERR_I error input
+ input wire wbs2_rty_i, // RTY_I retry input
+ output wire wbs2_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 2 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs2_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs2_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 3 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs3_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs3_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs3_dat_o, // DAT_O() data out
+ output wire wbs3_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs3_sel_o, // SEL_O() select output
+ output wire wbs3_stb_o, // STB_O strobe output
+ input wire wbs3_ack_i, // ACK_I acknowledge input
+ input wire wbs3_err_i, // ERR_I error input
+ input wire wbs3_rty_i, // RTY_I retry input
+ output wire wbs3_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 3 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs3_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs3_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 4 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs4_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs4_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs4_dat_o, // DAT_O() data out
+ output wire wbs4_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs4_sel_o, // SEL_O() select output
+ output wire wbs4_stb_o, // STB_O strobe output
+ input wire wbs4_ack_i, // ACK_I acknowledge input
+ input wire wbs4_err_i, // ERR_I error input
+ input wire wbs4_rty_i, // RTY_I retry input
+ output wire wbs4_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 4 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs4_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs4_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 5 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs5_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs5_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs5_dat_o, // DAT_O() data out
+ output wire wbs5_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs5_sel_o, // SEL_O() select output
+ output wire wbs5_stb_o, // STB_O strobe output
+ input wire wbs5_ack_i, // ACK_I acknowledge input
+ input wire wbs5_err_i, // ERR_I error input
+ input wire wbs5_rty_i, // RTY_I retry input
+ output wire wbs5_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 5 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs5_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs5_addr_msk // Slave address prefix mask
+);
+
+wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
+wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
+wire wbs2_match = ~|((wbm_adr_i ^ wbs2_addr) & wbs2_addr_msk);
+wire wbs3_match = ~|((wbm_adr_i ^ wbs3_addr) & wbs3_addr_msk);
+wire wbs4_match = ~|((wbm_adr_i ^ wbs4_addr) & wbs4_addr_msk);
+wire wbs5_match = ~|((wbm_adr_i ^ wbs5_addr) & wbs5_addr_msk);
+
+wire wbs0_sel = wbs0_match;
+wire wbs1_sel = wbs1_match & ~(wbs0_match);
+wire wbs2_sel = wbs2_match & ~(wbs0_match | wbs1_match);
+wire wbs3_sel = wbs3_match & ~(wbs0_match | wbs1_match | wbs2_match);
+wire wbs4_sel = wbs4_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match);
+wire wbs5_sel = wbs5_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match | wbs4_match);
+
+wire master_cycle = wbm_cyc_i & wbm_stb_i;
+
+wire select_error = ~(wbs0_sel | wbs1_sel | wbs2_sel | wbs3_sel | wbs4_sel | wbs5_sel) & master_cycle;
+
+// master
+assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
+ wbs1_sel ? wbs1_dat_i :
+ wbs2_sel ? wbs2_dat_i :
+ wbs3_sel ? wbs3_dat_i :
+ wbs4_sel ? wbs4_dat_i :
+ wbs5_sel ? wbs5_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbm_ack_o = wbs0_ack_i |
+ wbs1_ack_i |
+ wbs2_ack_i |
+ wbs3_ack_i |
+ wbs4_ack_i |
+ wbs5_ack_i;
+
+assign wbm_err_o = wbs0_err_i |
+ wbs1_err_i |
+ wbs2_err_i |
+ wbs3_err_i |
+ wbs4_err_i |
+ wbs5_err_i |
+ select_error;
+
+assign wbm_rty_o = wbs0_rty_i |
+ wbs1_rty_i |
+ wbs2_rty_i |
+ wbs3_rty_i |
+ wbs4_rty_i |
+ wbs5_rty_i;
+
+// slave 0
+assign wbs0_adr_o = wbm_adr_i;
+assign wbs0_dat_o = wbm_dat_i;
+assign wbs0_we_o = wbm_we_i & wbs0_sel;
+assign wbs0_sel_o = wbm_sel_i;
+assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
+assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
+
+// slave 1
+assign wbs1_adr_o = wbm_adr_i;
+assign wbs1_dat_o = wbm_dat_i;
+assign wbs1_we_o = wbm_we_i & wbs1_sel;
+assign wbs1_sel_o = wbm_sel_i;
+assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
+assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
+
+// slave 2
+assign wbs2_adr_o = wbm_adr_i;
+assign wbs2_dat_o = wbm_dat_i;
+assign wbs2_we_o = wbm_we_i & wbs2_sel;
+assign wbs2_sel_o = wbm_sel_i;
+assign wbs2_stb_o = wbm_stb_i & wbs2_sel;
+assign wbs2_cyc_o = wbm_cyc_i & wbs2_sel;
+
+// slave 3
+assign wbs3_adr_o = wbm_adr_i;
+assign wbs3_dat_o = wbm_dat_i;
+assign wbs3_we_o = wbm_we_i & wbs3_sel;
+assign wbs3_sel_o = wbm_sel_i;
+assign wbs3_stb_o = wbm_stb_i & wbs3_sel;
+assign wbs3_cyc_o = wbm_cyc_i & wbs3_sel;
+
+// slave 4
+assign wbs4_adr_o = wbm_adr_i;
+assign wbs4_dat_o = wbm_dat_i;
+assign wbs4_we_o = wbm_we_i & wbs4_sel;
+assign wbs4_sel_o = wbm_sel_i;
+assign wbs4_stb_o = wbm_stb_i & wbs4_sel;
+assign wbs4_cyc_o = wbm_cyc_i & wbs4_sel;
+
+// slave 5
+assign wbs5_adr_o = wbm_adr_i;
+assign wbs5_dat_o = wbm_dat_i;
+assign wbs5_we_o = wbm_we_i & wbs5_sel;
+assign wbs5_sel_o = wbm_sel_i;
+assign wbs5_stb_o = wbm_stb_i & wbs5_sel;
+assign wbs5_cyc_o = wbm_cyc_i & wbs5_sel;
+
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_mux_7.v b/ip/third_party/verilog-wishbone/rtl/wb_mux_7.v
new file mode 100644
index 0000000..017ce9e
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_mux_7.v
@@ -0,0 +1,309 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 7 port multiplexer
+ */
+module wb_mux_7 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave 0 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
+ output wire wbs0_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
+ output wire wbs0_stb_o, // STB_O strobe output
+ input wire wbs0_ack_i, // ACK_I acknowledge input
+ input wire wbs0_err_i, // ERR_I error input
+ input wire wbs0_rty_i, // RTY_I retry input
+ output wire wbs0_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 0 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 1 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
+ output wire wbs1_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
+ output wire wbs1_stb_o, // STB_O strobe output
+ input wire wbs1_ack_i, // ACK_I acknowledge input
+ input wire wbs1_err_i, // ERR_I error input
+ input wire wbs1_rty_i, // RTY_I retry input
+ output wire wbs1_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 1 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs1_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 2 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs2_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs2_dat_o, // DAT_O() data out
+ output wire wbs2_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs2_sel_o, // SEL_O() select output
+ output wire wbs2_stb_o, // STB_O strobe output
+ input wire wbs2_ack_i, // ACK_I acknowledge input
+ input wire wbs2_err_i, // ERR_I error input
+ input wire wbs2_rty_i, // RTY_I retry input
+ output wire wbs2_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 2 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs2_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs2_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 3 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs3_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs3_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs3_dat_o, // DAT_O() data out
+ output wire wbs3_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs3_sel_o, // SEL_O() select output
+ output wire wbs3_stb_o, // STB_O strobe output
+ input wire wbs3_ack_i, // ACK_I acknowledge input
+ input wire wbs3_err_i, // ERR_I error input
+ input wire wbs3_rty_i, // RTY_I retry input
+ output wire wbs3_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 3 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs3_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs3_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 4 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs4_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs4_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs4_dat_o, // DAT_O() data out
+ output wire wbs4_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs4_sel_o, // SEL_O() select output
+ output wire wbs4_stb_o, // STB_O strobe output
+ input wire wbs4_ack_i, // ACK_I acknowledge input
+ input wire wbs4_err_i, // ERR_I error input
+ input wire wbs4_rty_i, // RTY_I retry input
+ output wire wbs4_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 4 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs4_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs4_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 5 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs5_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs5_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs5_dat_o, // DAT_O() data out
+ output wire wbs5_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs5_sel_o, // SEL_O() select output
+ output wire wbs5_stb_o, // STB_O strobe output
+ input wire wbs5_ack_i, // ACK_I acknowledge input
+ input wire wbs5_err_i, // ERR_I error input
+ input wire wbs5_rty_i, // RTY_I retry input
+ output wire wbs5_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 5 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs5_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs5_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 6 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs6_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs6_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs6_dat_o, // DAT_O() data out
+ output wire wbs6_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs6_sel_o, // SEL_O() select output
+ output wire wbs6_stb_o, // STB_O strobe output
+ input wire wbs6_ack_i, // ACK_I acknowledge input
+ input wire wbs6_err_i, // ERR_I error input
+ input wire wbs6_rty_i, // RTY_I retry input
+ output wire wbs6_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 6 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs6_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs6_addr_msk // Slave address prefix mask
+);
+
+wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
+wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
+wire wbs2_match = ~|((wbm_adr_i ^ wbs2_addr) & wbs2_addr_msk);
+wire wbs3_match = ~|((wbm_adr_i ^ wbs3_addr) & wbs3_addr_msk);
+wire wbs4_match = ~|((wbm_adr_i ^ wbs4_addr) & wbs4_addr_msk);
+wire wbs5_match = ~|((wbm_adr_i ^ wbs5_addr) & wbs5_addr_msk);
+wire wbs6_match = ~|((wbm_adr_i ^ wbs6_addr) & wbs6_addr_msk);
+
+wire wbs0_sel = wbs0_match;
+wire wbs1_sel = wbs1_match & ~(wbs0_match);
+wire wbs2_sel = wbs2_match & ~(wbs0_match | wbs1_match);
+wire wbs3_sel = wbs3_match & ~(wbs0_match | wbs1_match | wbs2_match);
+wire wbs4_sel = wbs4_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match);
+wire wbs5_sel = wbs5_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match | wbs4_match);
+wire wbs6_sel = wbs6_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match | wbs4_match | wbs5_match);
+
+wire master_cycle = wbm_cyc_i & wbm_stb_i;
+
+wire select_error = ~(wbs0_sel | wbs1_sel | wbs2_sel | wbs3_sel | wbs4_sel | wbs5_sel | wbs6_sel) & master_cycle;
+
+// master
+assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
+ wbs1_sel ? wbs1_dat_i :
+ wbs2_sel ? wbs2_dat_i :
+ wbs3_sel ? wbs3_dat_i :
+ wbs4_sel ? wbs4_dat_i :
+ wbs5_sel ? wbs5_dat_i :
+ wbs6_sel ? wbs6_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbm_ack_o = wbs0_ack_i |
+ wbs1_ack_i |
+ wbs2_ack_i |
+ wbs3_ack_i |
+ wbs4_ack_i |
+ wbs5_ack_i |
+ wbs6_ack_i;
+
+assign wbm_err_o = wbs0_err_i |
+ wbs1_err_i |
+ wbs2_err_i |
+ wbs3_err_i |
+ wbs4_err_i |
+ wbs5_err_i |
+ wbs6_err_i |
+ select_error;
+
+assign wbm_rty_o = wbs0_rty_i |
+ wbs1_rty_i |
+ wbs2_rty_i |
+ wbs3_rty_i |
+ wbs4_rty_i |
+ wbs5_rty_i |
+ wbs6_rty_i;
+
+// slave 0
+assign wbs0_adr_o = wbm_adr_i;
+assign wbs0_dat_o = wbm_dat_i;
+assign wbs0_we_o = wbm_we_i & wbs0_sel;
+assign wbs0_sel_o = wbm_sel_i;
+assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
+assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
+
+// slave 1
+assign wbs1_adr_o = wbm_adr_i;
+assign wbs1_dat_o = wbm_dat_i;
+assign wbs1_we_o = wbm_we_i & wbs1_sel;
+assign wbs1_sel_o = wbm_sel_i;
+assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
+assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
+
+// slave 2
+assign wbs2_adr_o = wbm_adr_i;
+assign wbs2_dat_o = wbm_dat_i;
+assign wbs2_we_o = wbm_we_i & wbs2_sel;
+assign wbs2_sel_o = wbm_sel_i;
+assign wbs2_stb_o = wbm_stb_i & wbs2_sel;
+assign wbs2_cyc_o = wbm_cyc_i & wbs2_sel;
+
+// slave 3
+assign wbs3_adr_o = wbm_adr_i;
+assign wbs3_dat_o = wbm_dat_i;
+assign wbs3_we_o = wbm_we_i & wbs3_sel;
+assign wbs3_sel_o = wbm_sel_i;
+assign wbs3_stb_o = wbm_stb_i & wbs3_sel;
+assign wbs3_cyc_o = wbm_cyc_i & wbs3_sel;
+
+// slave 4
+assign wbs4_adr_o = wbm_adr_i;
+assign wbs4_dat_o = wbm_dat_i;
+assign wbs4_we_o = wbm_we_i & wbs4_sel;
+assign wbs4_sel_o = wbm_sel_i;
+assign wbs4_stb_o = wbm_stb_i & wbs4_sel;
+assign wbs4_cyc_o = wbm_cyc_i & wbs4_sel;
+
+// slave 5
+assign wbs5_adr_o = wbm_adr_i;
+assign wbs5_dat_o = wbm_dat_i;
+assign wbs5_we_o = wbm_we_i & wbs5_sel;
+assign wbs5_sel_o = wbm_sel_i;
+assign wbs5_stb_o = wbm_stb_i & wbs5_sel;
+assign wbs5_cyc_o = wbm_cyc_i & wbs5_sel;
+
+// slave 6
+assign wbs6_adr_o = wbm_adr_i;
+assign wbs6_dat_o = wbm_dat_i;
+assign wbs6_we_o = wbm_we_i & wbs6_sel;
+assign wbs6_sel_o = wbm_sel_i;
+assign wbs6_stb_o = wbm_stb_i & wbs6_sel;
+assign wbs6_cyc_o = wbm_cyc_i & wbs6_sel;
+
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_mux_8.v b/ip/third_party/verilog-wishbone/rtl/wb_mux_8.v
new file mode 100644
index 0000000..41b1e09
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_mux_8.v
@@ -0,0 +1,343 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Wishbone 8 port multiplexer
+ */
+module wb_mux_8 #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ /*
+ * Wishbone master input
+ */
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ /*
+ * Wishbone slave 0 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
+ output wire wbs0_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
+ output wire wbs0_stb_o, // STB_O strobe output
+ input wire wbs0_ack_i, // ACK_I acknowledge input
+ input wire wbs0_err_i, // ERR_I error input
+ input wire wbs0_rty_i, // RTY_I retry input
+ output wire wbs0_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 0 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 1 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
+ output wire wbs1_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
+ output wire wbs1_stb_o, // STB_O strobe output
+ input wire wbs1_ack_i, // ACK_I acknowledge input
+ input wire wbs1_err_i, // ERR_I error input
+ input wire wbs1_rty_i, // RTY_I retry input
+ output wire wbs1_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 1 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs1_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 2 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs2_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs2_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs2_dat_o, // DAT_O() data out
+ output wire wbs2_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs2_sel_o, // SEL_O() select output
+ output wire wbs2_stb_o, // STB_O strobe output
+ input wire wbs2_ack_i, // ACK_I acknowledge input
+ input wire wbs2_err_i, // ERR_I error input
+ input wire wbs2_rty_i, // RTY_I retry input
+ output wire wbs2_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 2 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs2_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs2_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 3 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs3_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs3_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs3_dat_o, // DAT_O() data out
+ output wire wbs3_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs3_sel_o, // SEL_O() select output
+ output wire wbs3_stb_o, // STB_O strobe output
+ input wire wbs3_ack_i, // ACK_I acknowledge input
+ input wire wbs3_err_i, // ERR_I error input
+ input wire wbs3_rty_i, // RTY_I retry input
+ output wire wbs3_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 3 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs3_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs3_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 4 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs4_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs4_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs4_dat_o, // DAT_O() data out
+ output wire wbs4_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs4_sel_o, // SEL_O() select output
+ output wire wbs4_stb_o, // STB_O strobe output
+ input wire wbs4_ack_i, // ACK_I acknowledge input
+ input wire wbs4_err_i, // ERR_I error input
+ input wire wbs4_rty_i, // RTY_I retry input
+ output wire wbs4_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 4 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs4_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs4_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 5 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs5_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs5_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs5_dat_o, // DAT_O() data out
+ output wire wbs5_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs5_sel_o, // SEL_O() select output
+ output wire wbs5_stb_o, // STB_O strobe output
+ input wire wbs5_ack_i, // ACK_I acknowledge input
+ input wire wbs5_err_i, // ERR_I error input
+ input wire wbs5_rty_i, // RTY_I retry input
+ output wire wbs5_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 5 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs5_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs5_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 6 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs6_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs6_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs6_dat_o, // DAT_O() data out
+ output wire wbs6_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs6_sel_o, // SEL_O() select output
+ output wire wbs6_stb_o, // STB_O strobe output
+ input wire wbs6_ack_i, // ACK_I acknowledge input
+ input wire wbs6_err_i, // ERR_I error input
+ input wire wbs6_rty_i, // RTY_I retry input
+ output wire wbs6_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 6 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs6_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs6_addr_msk, // Slave address prefix mask
+
+ /*
+ * Wishbone slave 7 output
+ */
+ output wire [ADDR_WIDTH-1:0] wbs7_adr_o, // ADR_O() address output
+ input wire [DATA_WIDTH-1:0] wbs7_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs7_dat_o, // DAT_O() data out
+ output wire wbs7_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs7_sel_o, // SEL_O() select output
+ output wire wbs7_stb_o, // STB_O strobe output
+ input wire wbs7_ack_i, // ACK_I acknowledge input
+ input wire wbs7_err_i, // ERR_I error input
+ input wire wbs7_rty_i, // RTY_I retry input
+ output wire wbs7_cyc_o, // CYC_O cycle output
+
+ /*
+ * Wishbone slave 7 address configuration
+ */
+ input wire [ADDR_WIDTH-1:0] wbs7_addr, // Slave address prefix
+ input wire [ADDR_WIDTH-1:0] wbs7_addr_msk // Slave address prefix mask
+);
+
+wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
+wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
+wire wbs2_match = ~|((wbm_adr_i ^ wbs2_addr) & wbs2_addr_msk);
+wire wbs3_match = ~|((wbm_adr_i ^ wbs3_addr) & wbs3_addr_msk);
+wire wbs4_match = ~|((wbm_adr_i ^ wbs4_addr) & wbs4_addr_msk);
+wire wbs5_match = ~|((wbm_adr_i ^ wbs5_addr) & wbs5_addr_msk);
+wire wbs6_match = ~|((wbm_adr_i ^ wbs6_addr) & wbs6_addr_msk);
+wire wbs7_match = ~|((wbm_adr_i ^ wbs7_addr) & wbs7_addr_msk);
+
+wire wbs0_sel = wbs0_match;
+wire wbs1_sel = wbs1_match & ~(wbs0_match);
+wire wbs2_sel = wbs2_match & ~(wbs0_match | wbs1_match);
+wire wbs3_sel = wbs3_match & ~(wbs0_match | wbs1_match | wbs2_match);
+wire wbs4_sel = wbs4_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match);
+wire wbs5_sel = wbs5_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match | wbs4_match);
+wire wbs6_sel = wbs6_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match | wbs4_match | wbs5_match);
+wire wbs7_sel = wbs7_match & ~(wbs0_match | wbs1_match | wbs2_match | wbs3_match | wbs4_match | wbs5_match | wbs6_match);
+
+wire master_cycle = wbm_cyc_i & wbm_stb_i;
+
+wire select_error = ~(wbs0_sel | wbs1_sel | wbs2_sel | wbs3_sel | wbs4_sel | wbs5_sel | wbs6_sel | wbs7_sel) & master_cycle;
+
+// master
+assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
+ wbs1_sel ? wbs1_dat_i :
+ wbs2_sel ? wbs2_dat_i :
+ wbs3_sel ? wbs3_dat_i :
+ wbs4_sel ? wbs4_dat_i :
+ wbs5_sel ? wbs5_dat_i :
+ wbs6_sel ? wbs6_dat_i :
+ wbs7_sel ? wbs7_dat_i :
+ {DATA_WIDTH{1'b0}};
+
+assign wbm_ack_o = wbs0_ack_i |
+ wbs1_ack_i |
+ wbs2_ack_i |
+ wbs3_ack_i |
+ wbs4_ack_i |
+ wbs5_ack_i |
+ wbs6_ack_i |
+ wbs7_ack_i;
+
+assign wbm_err_o = wbs0_err_i |
+ wbs1_err_i |
+ wbs2_err_i |
+ wbs3_err_i |
+ wbs4_err_i |
+ wbs5_err_i |
+ wbs6_err_i |
+ wbs7_err_i |
+ select_error;
+
+assign wbm_rty_o = wbs0_rty_i |
+ wbs1_rty_i |
+ wbs2_rty_i |
+ wbs3_rty_i |
+ wbs4_rty_i |
+ wbs5_rty_i |
+ wbs6_rty_i |
+ wbs7_rty_i;
+
+// slave 0
+assign wbs0_adr_o = wbm_adr_i;
+assign wbs0_dat_o = wbm_dat_i;
+assign wbs0_we_o = wbm_we_i & wbs0_sel;
+assign wbs0_sel_o = wbm_sel_i;
+assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
+assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
+
+// slave 1
+assign wbs1_adr_o = wbm_adr_i;
+assign wbs1_dat_o = wbm_dat_i;
+assign wbs1_we_o = wbm_we_i & wbs1_sel;
+assign wbs1_sel_o = wbm_sel_i;
+assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
+assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
+
+// slave 2
+assign wbs2_adr_o = wbm_adr_i;
+assign wbs2_dat_o = wbm_dat_i;
+assign wbs2_we_o = wbm_we_i & wbs2_sel;
+assign wbs2_sel_o = wbm_sel_i;
+assign wbs2_stb_o = wbm_stb_i & wbs2_sel;
+assign wbs2_cyc_o = wbm_cyc_i & wbs2_sel;
+
+// slave 3
+assign wbs3_adr_o = wbm_adr_i;
+assign wbs3_dat_o = wbm_dat_i;
+assign wbs3_we_o = wbm_we_i & wbs3_sel;
+assign wbs3_sel_o = wbm_sel_i;
+assign wbs3_stb_o = wbm_stb_i & wbs3_sel;
+assign wbs3_cyc_o = wbm_cyc_i & wbs3_sel;
+
+// slave 4
+assign wbs4_adr_o = wbm_adr_i;
+assign wbs4_dat_o = wbm_dat_i;
+assign wbs4_we_o = wbm_we_i & wbs4_sel;
+assign wbs4_sel_o = wbm_sel_i;
+assign wbs4_stb_o = wbm_stb_i & wbs4_sel;
+assign wbs4_cyc_o = wbm_cyc_i & wbs4_sel;
+
+// slave 5
+assign wbs5_adr_o = wbm_adr_i;
+assign wbs5_dat_o = wbm_dat_i;
+assign wbs5_we_o = wbm_we_i & wbs5_sel;
+assign wbs5_sel_o = wbm_sel_i;
+assign wbs5_stb_o = wbm_stb_i & wbs5_sel;
+assign wbs5_cyc_o = wbm_cyc_i & wbs5_sel;
+
+// slave 6
+assign wbs6_adr_o = wbm_adr_i;
+assign wbs6_dat_o = wbm_dat_i;
+assign wbs6_we_o = wbm_we_i & wbs6_sel;
+assign wbs6_sel_o = wbm_sel_i;
+assign wbs6_stb_o = wbm_stb_i & wbs6_sel;
+assign wbs6_cyc_o = wbm_cyc_i & wbs6_sel;
+
+// slave 7
+assign wbs7_adr_o = wbm_adr_i;
+assign wbs7_dat_o = wbm_dat_i;
+assign wbs7_we_o = wbm_we_i & wbs7_sel;
+assign wbs7_sel_o = wbm_sel_i;
+assign wbs7_stb_o = wbm_stb_i & wbs7_sel;
+assign wbs7_cyc_o = wbm_cyc_i & wbs7_sel;
+
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_ram.v b/ip/third_party/verilog-wishbone/rtl/wb_ram.v
new file mode 100644
index 0000000..c167520
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_ram.v
@@ -0,0 +1,94 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Wishbone RAM
+ */
+module wb_ram #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 16, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+
+ input wire [ADDR_WIDTH-1:0] adr_i, // ADR_I() address
+ input wire [DATA_WIDTH-1:0] dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] dat_o, // DAT_O() data out
+ input wire we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] sel_i, // SEL_I() select input
+ input wire stb_i, // STB_I strobe input
+ output wire ack_o, // ACK_O acknowledge output
+ input wire cyc_i // CYC_I cycle input
+);
+
+// for interfaces that are more than one word wide, disable address lines
+parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(SELECT_WIDTH);
+// width of data port in words (1, 2, 4, or 8)
+parameter WORD_WIDTH = SELECT_WIDTH;
+// size of words (8, 16, 32, or 64 bits)
+parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
+
+reg [DATA_WIDTH-1:0] dat_o_reg = {DATA_WIDTH{1'b0}};
+reg ack_o_reg = 1'b0;
+
+// (* RAM_STYLE="BLOCK" *)
+reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
+
+wire [VALID_ADDR_WIDTH-1:0] adr_i_valid = adr_i >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+
+assign dat_o = dat_o_reg;
+assign ack_o = ack_o_reg;
+
+integer i, j;
+
+initial begin
+ // two nested loops for smaller number of iterations per loop
+ // workaround for synthesizer complaints about large loop counts
+ for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
+ for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
+ mem[j] = 0;
+ end
+ end
+end
+
+always @(posedge clk) begin
+ ack_o_reg <= 1'b0;
+ for (i = 0; i < WORD_WIDTH; i = i + 1) begin
+ if (cyc_i & stb_i & ~ack_o) begin
+ if (we_i & sel_i[i]) begin
+ mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE] <= dat_i[WORD_SIZE*i +: WORD_SIZE];
+ end
+ dat_o_reg[WORD_SIZE*i +: WORD_SIZE] <= mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE];
+ ack_o_reg <= 1'b1;
+ end
+ end
+end
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/rtl/wb_reg.v b/ip/third_party/verilog-wishbone/rtl/wb_reg.v
new file mode 100644
index 0000000..c26d912
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/rtl/wb_reg.v
@@ -0,0 +1,131 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Wishbone register
+ */
+module wb_reg #
+(
+ parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
+ parameter ADDR_WIDTH = 32, // width of address bus in bits
+ parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
+)
+(
+ input wire clk,
+ input wire rst,
+
+ // master side
+ input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address
+ input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
+ input wire wbm_we_i, // WE_I write enable input
+ input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
+ input wire wbm_stb_i, // STB_I strobe input
+ output wire wbm_ack_o, // ACK_O acknowledge output
+ output wire wbm_err_o, // ERR_O error output
+ output wire wbm_rty_o, // RTY_O retry output
+ input wire wbm_cyc_i, // CYC_I cycle input
+
+ // slave side
+ output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address
+ input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
+ output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
+ output wire wbs_we_o, // WE_O write enable output
+ output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
+ output wire wbs_stb_o, // STB_O strobe output
+ input wire wbs_ack_i, // ACK_I acknowledge input
+ input wire wbs_err_i, // ERR_I error input
+ input wire wbs_rty_i, // RTY_I retry input
+ output wire wbs_cyc_o // CYC_O cycle output
+);
+
+reg [DATA_WIDTH-1:0] wbm_dat_o_reg = 0;
+reg wbm_ack_o_reg = 0;
+reg wbm_err_o_reg = 0;
+reg wbm_rty_o_reg = 0;
+
+reg [ADDR_WIDTH-1:0] wbs_adr_o_reg = 0;
+reg [DATA_WIDTH-1:0] wbs_dat_o_reg = 0;
+reg wbs_we_o_reg = 0;
+reg [SELECT_WIDTH-1:0] wbs_sel_o_reg = 0;
+reg wbs_stb_o_reg = 0;
+reg wbs_cyc_o_reg = 0;
+
+assign wbm_dat_o = wbm_dat_o_reg;
+assign wbm_ack_o = wbm_ack_o_reg;
+assign wbm_err_o = wbm_err_o_reg;
+assign wbm_rty_o = wbm_rty_o_reg;
+
+assign wbs_adr_o = wbs_adr_o_reg;
+assign wbs_dat_o = wbs_dat_o_reg;
+assign wbs_we_o = wbs_we_o_reg;
+assign wbs_sel_o = wbs_sel_o_reg;
+assign wbs_stb_o = wbs_stb_o_reg;
+assign wbs_cyc_o = wbs_cyc_o_reg;
+
+always @(posedge clk) begin
+ if (rst) begin
+ wbm_dat_o_reg <= 0;
+ wbm_ack_o_reg <= 0;
+ wbm_err_o_reg <= 0;
+ wbm_rty_o_reg <= 0;
+ wbs_adr_o_reg <= 0;
+ wbs_dat_o_reg <= 0;
+ wbs_we_o_reg <= 0;
+ wbs_sel_o_reg <= 0;
+ wbs_stb_o_reg <= 0;
+ wbs_cyc_o_reg <= 0;
+ end else begin
+ if (wbs_cyc_o_reg & wbs_stb_o_reg) begin
+ // cycle - hold values
+ if (wbs_ack_i | wbs_err_i | wbs_rty_i) begin
+ // end of cycle - pass through slave to master
+ wbm_dat_o_reg <= wbs_dat_i;
+ wbm_ack_o_reg <= wbs_ack_i;
+ wbm_err_o_reg <= wbs_err_i;
+ wbm_rty_o_reg <= wbs_rty_i;
+ wbs_we_o_reg <= 0;
+ wbs_stb_o_reg <= 0;
+ end
+ end else begin
+ // idle - pass through master to slave
+ wbm_dat_o_reg <= 0;
+ wbm_ack_o_reg <= 0;
+ wbm_err_o_reg <= 0;
+ wbm_rty_o_reg <= 0;
+ wbs_adr_o_reg <= wbm_adr_i;
+ wbs_dat_o_reg <= wbm_dat_i;
+ wbs_we_o_reg <= wbm_we_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
+ wbs_sel_o_reg <= wbm_sel_i;
+ wbs_stb_o_reg <= wbm_stb_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
+ wbs_cyc_o_reg <= wbm_cyc_i;
+ end
+ end
+end
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/axis_ep.py b/ip/third_party/verilog-wishbone/tb/axis_ep.py
new file mode 100644
index 0000000..de4528e
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/axis_ep.py
@@ -0,0 +1,512 @@
+"""
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+
+skip_asserts = False
+
+class AXIStreamFrame(object):
+ def __init__(self, data=b'', keep=None, id=None, dest=None, user=None, last_cycle_user=None):
+ self.B = 0
+ self.N = 8
+ self.M = 1
+ self.WL = 8
+ self.data = b''
+ self.keep = None
+ self.id = 0
+ self.dest = 0
+ self.user = None
+ self.last_cycle_user = None
+
+ if type(data) in (bytes, bytearray):
+ self.data = bytearray(data)
+ self.keep = keep
+ self.id = id
+ self.dest = dest
+ self.user = user
+ self.last_cycle_user = last_cycle_user
+ elif type(data) is AXIStreamFrame:
+ self.N = data.N
+ self.WL = data.WL
+ if type(data.data) is bytearray:
+ self.data = bytearray(data.data)
+ else:
+ self.data = list(data.data)
+ if data.keep is not None:
+ self.keep = list(data.keep)
+ if data.id is not None:
+ if type(data.id) in (int, bool):
+ self.id = data.id
+ else:
+ self.id = list(data.id)
+ if data.dest is not None:
+ if type(data.dest) in (int, bool):
+ self.dest = data.dest
+ else:
+ self.dest = list(data.dest)
+ if data.user is not None:
+ if type(data.user) in (int, bool):
+ self.user = data.user
+ else:
+ self.user = list(data.user)
+ self.last_cycle_user = data.last_cycle_user
+ else:
+ self.data = list(data)
+ self.keep = keep
+ self.id = id
+ self.dest = dest
+ self.user = user
+ self.last_cycle_user = last_cycle_user
+
+ def build(self):
+ if self.data is None:
+ return
+
+ f = list(self.data)
+ tdata = []
+ tkeep = []
+ tid = []
+ tdest = []
+ tuser = []
+ i = 0
+
+ while len(f) > 0:
+ if self.B == 0:
+ data = 0
+ keep = 0
+ for j in range(self.M):
+ data = data | (f.pop(0) << (j*self.WL))
+ keep = keep | (1 << j)
+ if len(f) == 0: break
+ tdata.append(data)
+
+ if self.keep is None:
+ tkeep.append(keep)
+ else:
+ tkeep.append(self.keep[i])
+ else:
+ # multiple tdata signals
+ data = 0
+ tdata.append(f.pop(0))
+ tkeep.append(0)
+
+ if self.id is None:
+ tid.append(0)
+ elif type(self.id) is int:
+ tid.append(self.id)
+ else:
+ tid.append(self.id[i])
+
+ if self.dest is None:
+ tdest.append(0)
+ elif type(self.dest) is int:
+ tdest.append(self.dest)
+ else:
+ tdest.append(self.dest[i])
+
+ if self.user is None:
+ tuser.append(0)
+ elif type(self.user) is int:
+ tuser.append(self.user)
+ else:
+ tuser.append(self.user[i])
+ i += 1
+
+ if self.last_cycle_user:
+ tuser[-1] = self.last_cycle_user
+
+ return tdata, tkeep, tid, tdest, tuser
+
+ def parse(self, tdata, tkeep, tid, tdest, tuser):
+ if tdata is None or tkeep is None or tuser is None:
+ return
+ if len(tdata) != len(tkeep) or len(tdata) != len(tid) or len(tdata) != len(tdest) or len(tdata) != len(tuser):
+ raise Exception("Invalid data")
+
+ self.data = []
+ self.keep = []
+ self.id = []
+ self.dest = []
+ self.user = []
+
+ if self.B == 0:
+ mask = 2**self.WL-1
+
+ for i in range(len(tdata)):
+ for j in range(self.M):
+ if tkeep[i] & (1 << j):
+ self.data.append((tdata[i] >> (j*self.WL)) & mask)
+ self.keep.append(tkeep[i])
+ self.id.append(tid[i])
+ self.dest.append(tdest[i])
+ self.user.append(tuser[i])
+ else:
+ for i in range(len(tdata)):
+ self.data.append(tdata[i])
+ self.keep.append(tkeep[i])
+ self.id.append(tid[i])
+ self.dest.append(tdest[i])
+ self.user.append(tuser[i])
+
+ if self.WL == 8:
+ self.data = bytearray(self.data)
+
+ self.last_cycle_user = self.user[-1]
+
+ def __eq__(self, other):
+ if not isinstance(other, AXIStreamFrame):
+ return False
+ if self.data != other.data:
+ return False
+ if self.keep is not None and other.keep is not None:
+ if self.keep != other.keep:
+ return False
+ if self.id is not None and other.id is not None:
+ if type(self.id) in (int, bool) and type(other.id) is list:
+ for k in other.id:
+ if self.id != k:
+ return False
+ elif type(other.id) in (int, bool) and type(self.id) is list:
+ for k in self.id:
+ if other.id != k:
+ return False
+ elif self.id != other.id:
+ return False
+ if self.dest is not None and other.dest is not None:
+ if type(self.dest) in (int, bool) and type(other.dest) is list:
+ for k in other.dest:
+ if self.dest != k:
+ return False
+ elif type(other.dest) in (int, bool) and type(self.dest) is list:
+ for k in self.dest:
+ if other.dest != k:
+ return False
+ elif self.dest != other.dest:
+ return False
+ if self.last_cycle_user is not None and other.last_cycle_user is not None:
+ if self.last_cycle_user != other.last_cycle_user:
+ return False
+ if self.user is not None and other.user is not None:
+ if type(self.user) in (int, bool) and type(other.user) is list:
+ for k in other.user[:-1]:
+ if self.user != k:
+ return False
+ elif type(other.user) in (int, bool) and type(self.user) is list:
+ for k in self.user[:-1]:
+ if other.user != k:
+ return False
+ elif self.user != other.user:
+ return False
+ else:
+ if self.user is not None and other.user is not None:
+ if type(self.user) in (int, bool) and type(other.user) is list:
+ for k in other.user:
+ if self.user != k:
+ return False
+ elif type(other.user) in (int, bool) and type(self.user) is list:
+ for k in self.user:
+ if other.user != k:
+ return False
+ elif self.user != other.user:
+ return False
+ return True
+
+ def __repr__(self):
+ return (
+ ('AXIStreamFrame(data=%s, ' % repr(self.data)) +
+ ('keep=%s, ' % repr(self.keep)) +
+ ('id=%s, ' % repr(self.id)) +
+ ('dest=%s, ' % repr(self.dest)) +
+ ('user=%s, ' % repr(self.user)) +
+ ('last_cycle_user=%s)' % repr(self.last_cycle_user))
+ )
+
+ def __iter__(self):
+ return self.data.__iter__()
+
+
+class AXIStreamSource(object):
+ def __init__(self):
+ self.has_logic = False
+ self.queue = []
+
+ def send(self, frame):
+ self.queue.append(AXIStreamFrame(frame))
+
+ def write(self, data):
+ self.send(data)
+
+ def count(self):
+ return len(self.queue)
+
+ def empty(self):
+ return self.count() == 0
+
+ def create_logic(self,
+ clk,
+ rst,
+ tdata=None,
+ tkeep=Signal(bool(True)),
+ tvalid=Signal(bool(False)),
+ tready=Signal(bool(True)),
+ tlast=Signal(bool(False)),
+ tid=Signal(intbv(0)),
+ tdest=Signal(intbv(0)),
+ tuser=Signal(intbv(0)),
+ pause=0,
+ name=None
+ ):
+
+ assert not self.has_logic
+
+ self.has_logic = True
+
+ tready_int = Signal(bool(False))
+ tvalid_int = Signal(bool(False))
+
+ @always_comb
+ def pause_logic():
+ tready_int.next = tready and not pause
+ tvalid.next = tvalid_int and not pause
+
+ @instance
+ def logic():
+ frame = AXIStreamFrame()
+ data = []
+ keep = []
+ id = []
+ dest = []
+ user = []
+ B = 0
+ N = len(tdata)
+ M = len(tkeep)
+ WL = int((len(tdata)+M-1)/M)
+
+ if type(tdata) is list or type(tdata) is tuple:
+ # multiple tdata signals
+ B = len(tdata)
+ N = [len(b) for b in tdata]
+ M = 1
+ WL = [1]*B
+
+ while True:
+ yield clk.posedge, rst.posedge
+
+ if rst:
+ if B > 0:
+ for s in tdata:
+ s.next = 0
+ else:
+ tdata.next = 0
+ tkeep.next = 0
+ tid.next = 0
+ tdest.next = 0
+ tuser.next = False
+ tvalid_int.next = False
+ tlast.next = False
+ else:
+ if tready_int and tvalid:
+ if len(data) > 0:
+ if B > 0:
+ l = data.pop(0)
+ for i in range(B):
+ tdata[i].next = l[i]
+ else:
+ tdata.next = data.pop(0)
+ tkeep.next = keep.pop(0)
+ tid.next = id.pop(0)
+ tdest.next = dest.pop(0)
+ tuser.next = user.pop(0)
+ tvalid_int.next = True
+ tlast.next = len(data) == 0
+ else:
+ tvalid_int.next = False
+ tlast.next = False
+ if (tlast and tready_int and tvalid) or not tvalid_int:
+ if len(self.queue) > 0:
+ frame = self.queue.pop(0)
+ frame.B = B
+ frame.N = N
+ frame.M = M
+ frame.WL = WL
+ data, keep, id, dest, user = frame.build()
+ if name is not None:
+ print("[%s] Sending frame %s" % (name, repr(frame)))
+ if B > 0:
+ l = data.pop(0)
+ for i in range(B):
+ tdata[i].next = l[i]
+ else:
+ tdata.next = data.pop(0)
+ tkeep.next = keep.pop(0)
+ tid.next = id.pop(0)
+ tdest.next = dest.pop(0)
+ tuser.next = user.pop(0)
+ tvalid_int.next = True
+ tlast.next = len(data) == 0
+
+ return instances()
+
+
+class AXIStreamSink(object):
+ def __init__(self):
+ self.has_logic = False
+ self.queue = []
+ self.read_queue = []
+
+ def recv(self):
+ if len(self.queue) > 0:
+ return self.queue.pop(0)
+ return None
+
+ def read(self, count=-1):
+ while len(self.queue) > 0:
+ self.read_queue.extend(self.queue.pop(0).data)
+ if count < 0:
+ count = len(self.read_queue)
+ data = self.read_queue[:count]
+ del self.read_queue[:count]
+ return data
+
+ def count(self):
+ return len(self.queue)
+
+ def empty(self):
+ return self.count() == 0
+
+ def create_logic(self,
+ clk,
+ rst,
+ tdata=None,
+ tkeep=Signal(bool(True)),
+ tvalid=Signal(bool(False)),
+ tready=Signal(bool(True)),
+ tlast=Signal(bool(True)),
+ tid=Signal(intbv(0)),
+ tdest=Signal(intbv(0)),
+ tuser=Signal(intbv(0)),
+ pause=0,
+ name=None
+ ):
+
+ assert not self.has_logic
+
+ self.has_logic = True
+
+ tready_int = Signal(bool(False))
+ tvalid_int = Signal(bool(False))
+
+ @always_comb
+ def pause_logic():
+ tready.next = tready_int and not pause
+ tvalid_int.next = tvalid and not pause
+
+ @instance
+ def logic():
+ frame = AXIStreamFrame()
+ data = []
+ keep = []
+ id = []
+ dest = []
+ user = []
+ B = 0
+ N = len(tdata)
+ M = len(tkeep)
+ WL = int((len(tdata)+M-1)/M)
+ first = True
+
+ if type(tdata) is list or type(tdata) is tuple:
+ # multiple tdata signals
+ B = len(tdata)
+ N = [len(b) for b in tdata]
+ M = 1
+ WL = [1]*B
+
+ while True:
+ yield clk.posedge, rst.posedge
+
+ if rst:
+ tready_int.next = False
+ frame = AXIStreamFrame()
+ data = []
+ keep = []
+ id = []
+ dest = []
+ user = []
+ first = True
+ else:
+ tready_int.next = True
+
+ if tvalid_int:
+
+ if not skip_asserts:
+ # zero tkeep not allowed
+ assert int(tkeep) != 0
+ # tkeep must be contiguous
+ # i.e. 0b00011110 allowed, but 0b00011010 not allowed
+ b = int(tkeep)
+ while b & 1 == 0:
+ b = b >> 1
+ while b & 1 == 1:
+ b = b >> 1
+ assert b == 0
+ # tkeep must not have gaps across cycles
+ if not first:
+ # not first cycle; lowest bit must be set
+ assert int(tkeep) & 1
+ if not tlast:
+ # not last cycle; highest bit must be set
+ assert int(tkeep) & (1 << len(tkeep)-1)
+
+ if B > 0:
+ l = []
+ for i in range(B):
+ l.append(int(tdata[i]))
+ data.append(l)
+ else:
+ data.append(int(tdata))
+ keep.append(int(tkeep))
+ id.append(int(tid))
+ dest.append(int(tdest))
+ user.append(int(tuser))
+ first = False
+ if tlast:
+ frame.B = B
+ frame.N = N
+ frame.M = M
+ frame.WL = WL
+ frame.parse(data, keep, id, dest, user)
+ self.queue.append(frame)
+ if name is not None:
+ print("[%s] Got frame %s" % (name, repr(frame)))
+ frame = AXIStreamFrame()
+ data = []
+ keep = []
+ id = []
+ dest = []
+ user = []
+ first = True
+
+ return instances()
+
diff --git a/ip/third_party/verilog-wishbone/tb/test_arbiter.py b/ip/third_party/verilog-wishbone/tb/test_arbiter.py
new file mode 100755
index 0000000..afb89f7
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_arbiter.py
@@ -0,0 +1,176 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2014-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+module = 'arbiter'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ PORTS = 32
+ TYPE = "PRIORITY"
+ BLOCK = "REQUEST"
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ request = Signal(intbv(0)[PORTS:])
+ acknowledge = Signal(intbv(0)[PORTS:])
+
+ # Outputs
+ grant = Signal(intbv(0)[PORTS:])
+ grant_valid = Signal(bool(0))
+ grant_encoded = Signal(intbv(0)[5:])
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+
+ request=request,
+ acknowledge=acknowledge,
+
+ grant=grant,
+ grant_valid=grant_valid,
+ grant_encoded=grant_encoded
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+
+ print("test 1: one bit")
+ current_test.next = 1
+
+ yield clk.posedge
+
+ for i in range(32):
+ l = [i]
+ k = 0
+ for y in l:
+ k = k | 1 << y
+ request.next = k
+ yield clk.posedge
+ request.next = 0
+ yield clk.posedge
+
+ assert grant == 1 << i
+ assert grant_encoded == i
+
+ yield clk.posedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ print("test 2: two bits")
+ current_test.next = 2
+
+ for i in range(32):
+ for j in range(32):
+ l = [i, j]
+ k = 0
+ for y in l:
+ k = k | 1 << y
+ request.next = k
+ yield clk.posedge
+ request.next = 0
+ yield clk.posedge
+
+ assert grant == 1 << max(l)
+ assert grant_encoded == max(l)
+
+ request.next = 0
+
+ yield clk.posedge
+
+ print("test 3: five bits")
+ current_test.next = 3
+
+ for i in range(32):
+ l = [(i*x) % 32 for x in [1,2,3,4,5]]
+ k = 0
+ for y in l:
+ k = k | 1 << y
+ request.next = k
+ yield clk.posedge
+ request.next = 0
+ yield clk.posedge
+
+ assert grant == 1 << max(l)
+ assert grant_encoded == max(l)
+
+ prev = int(grant_encoded)
+
+ yield clk.posedge
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ os.chdir(os.path.dirname(os.path.abspath(__file__)))
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
+
diff --git a/ip/third_party/verilog-wishbone/tb/test_arbiter.v b/ip/third_party/verilog-wishbone/tb/test_arbiter.v
new file mode 100644
index 0000000..ce9481a
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_arbiter.v
@@ -0,0 +1,87 @@
+/*
+
+Copyright (c) 2014-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for arbiter
+ */
+module test_arbiter;
+
+// Parameters
+localparam PORTS = 32;
+localparam TYPE = "PRIORITY";
+localparam BLOCK = "REQUEST";
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [PORTS-1:0] request = 0;
+reg [PORTS-1:0] acknowledge = 0;
+
+// Outputs
+wire [PORTS-1:0] grant;
+wire grant_valid;
+wire [$clog2(PORTS)-1:0] grant_encoded;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ request,
+ acknowledge
+ );
+ $to_myhdl(
+ grant,
+ grant_valid,
+ grant_encoded
+ );
+
+ // dump file
+ $dumpfile("test_arbiter.lxt");
+ $dumpvars(0, test_arbiter);
+end
+
+arbiter #(
+ .PORTS(PORTS),
+ .TYPE(TYPE),
+ .BLOCK(BLOCK)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .request(request),
+ .acknowledge(acknowledge),
+ .grant(grant),
+ .grant_valid(grant_valid),
+ .grant_encoded(grant_encoded)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.py b/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.py
new file mode 100755
index 0000000..671001f
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.py
@@ -0,0 +1,236 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2014-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+module = 'arbiter'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("%s_rr.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ PORTS = 32
+ TYPE = "ROUND_ROBIN"
+ BLOCK = "REQUEST"
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ request = Signal(intbv(0)[PORTS:])
+ acknowledge = Signal(intbv(0)[PORTS:])
+
+ # Outputs
+ grant = Signal(intbv(0)[PORTS:])
+ grant_valid = Signal(bool(0))
+ grant_encoded = Signal(intbv(0)[5:])
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+
+ request=request,
+ acknowledge=acknowledge,
+
+ grant=grant,
+ grant_valid=grant_valid,
+ grant_encoded=grant_encoded
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+
+ prev = 0
+
+ print("test 1: one bit")
+ current_test.next = 1
+
+ yield clk.posedge
+
+ for i in range(32):
+ l = [i]
+ k = 0
+ for y in l:
+ k = k | 1 << y
+ request.next = k
+ yield clk.posedge
+ request.next = 0
+ yield clk.posedge
+
+ # emulate round robin
+ l2 = [x for x in l if x < prev]
+ if len(l2) == 0:
+ l2 = l
+ g = max(l2)
+
+ assert grant == 1 << g
+ assert grant_encoded == g
+
+ prev = int(grant_encoded)
+
+ yield clk.posedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ print("test 2: cycle")
+ current_test.next = 2
+
+ for i in range(32):
+ l = [0, 5, 10, 15, 20, 25, 30]
+ k = 0
+ for y in l:
+ k = k | 1 << y
+ request.next = k
+ yield clk.posedge
+ request.next = 0
+ yield clk.posedge
+
+ # emulate round robin
+ l2 = [x for x in l if x < prev]
+ if len(l2) == 0:
+ l2 = l
+ g = max(l2)
+
+ assert grant == 1 << g
+ assert grant_encoded == g
+
+ prev = int(grant_encoded)
+
+ yield clk.posedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ print("test 3: two bits")
+ current_test.next = 3
+
+ for i in range(32):
+ for j in range(32):
+ l = [i, j]
+ k = 0
+ for y in l:
+ k = k | 1 << y
+ request.next = k
+ yield clk.posedge
+ request.next = 0
+ yield clk.posedge
+
+ # emulate round robin
+ l2 = [x for x in l if x < prev]
+ if len(l2) == 0:
+ l2 = l
+ g = max(l2)
+
+ assert grant == 1 << g
+ assert grant_encoded == g
+
+ prev = int(grant_encoded)
+
+ yield clk.posedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ print("test 4: five bits")
+ current_test.next = 4
+
+ for i in range(32):
+ l = [(i*x) % 32 for x in [1,2,3,4,5]]
+ k = 0
+ for y in l:
+ k = k | 1 << y
+ request.next = k
+ yield clk.posedge
+ request.next = 0
+ yield clk.posedge
+
+ # emulate round robin
+ l2 = [x for x in l if x < prev]
+ if len(l2) == 0:
+ l2 = l
+ g = max(l2)
+
+ assert grant == 1 << g
+ assert grant_encoded == g
+
+ prev = int(grant_encoded)
+
+ yield clk.posedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ os.chdir(os.path.dirname(os.path.abspath(__file__)))
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
+
diff --git a/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.v b/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.v
new file mode 100644
index 0000000..31c8824
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.v
@@ -0,0 +1,87 @@
+/*
+
+Copyright (c) 2014-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for arbiter
+ */
+module test_arbiter_rr;
+
+// Parameters
+localparam PORTS = 32;
+localparam TYPE = "ROUND_ROBIN";
+localparam BLOCK = "REQUEST";
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [PORTS-1:0] request = 0;
+reg [PORTS-1:0] acknowledge = 0;
+
+// Outputs
+wire [PORTS-1:0] grant;
+wire grant_valid;
+wire [$clog2(PORTS)-1:0] grant_encoded;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ request,
+ acknowledge
+ );
+ $to_myhdl(
+ grant,
+ grant_valid,
+ grant_encoded
+ );
+
+ // dump file
+ $dumpfile("test_arbiter_rr.lxt");
+ $dumpvars(0, test_arbiter_rr);
+end
+
+arbiter #(
+ .PORTS(PORTS),
+ .TYPE(TYPE),
+ .BLOCK(BLOCK)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .request(request),
+ .acknowledge(acknowledge),
+ .grant(grant),
+ .grant_valid(grant_valid),
+ .grant_encoded(grant_encoded)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32.py b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32.py
new file mode 100755
index 0000000..30d658d
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32.py
@@ -0,0 +1,362 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+import struct
+
+import axis_ep
+import wb
+
+module = 'axis_wb_master'
+testbench = 'test_%s_8_32' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ IMPLICIT_FRAMING = 0
+ COUNT_SIZE = 16
+ AXIS_DATA_WIDTH = 8
+ AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)
+ WB_DATA_WIDTH = 32
+ WB_ADDR_WIDTH = 32
+ WB_SELECT_WIDTH = (WB_DATA_WIDTH/8)
+ READ_REQ = 0xA1
+ WRITE_REQ = 0xA2
+ READ_RESP = 0xA3
+ WRITE_RESP = 0xA4
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ input_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
+ input_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
+ input_axis_tvalid = Signal(bool(0))
+ input_axis_tlast = Signal(bool(0))
+ input_axis_tuser = Signal(bool(0))
+ output_axis_tready = Signal(bool(0))
+ wb_dat_i = Signal(intbv(0)[WB_DATA_WIDTH:])
+ wb_ack_i = Signal(bool(0))
+ wb_err_i = Signal(bool(0))
+
+ # Outputs
+ input_axis_tready = Signal(bool(0))
+ output_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
+ output_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
+ output_axis_tvalid = Signal(bool(0))
+ output_axis_tlast = Signal(bool(0))
+ output_axis_tuser = Signal(bool(0))
+ wb_adr_o = Signal(intbv(0)[WB_ADDR_WIDTH:])
+ wb_dat_o = Signal(intbv(0)[WB_DATA_WIDTH:])
+ wb_we_o = Signal(bool(0))
+ wb_sel_o = Signal(intbv(0)[WB_SELECT_WIDTH:])
+ wb_stb_o = Signal(bool(0))
+ wb_cyc_o = Signal(bool(0))
+ busy = Signal(bool(0))
+
+ # sources and sinks
+ source_pause = Signal(bool(0))
+ sink_pause = Signal(bool(0))
+
+ source = axis_ep.AXIStreamSource()
+
+ source_logic = source.create_logic(
+ clk,
+ rst,
+ tdata=input_axis_tdata,
+ tkeep=input_axis_tkeep,
+ tvalid=input_axis_tvalid,
+ tready=input_axis_tready,
+ tlast=input_axis_tlast,
+ tuser=input_axis_tuser,
+ pause=source_pause,
+ name='source'
+ )
+
+ sink = axis_ep.AXIStreamSink()
+
+ sink_logic = sink.create_logic(
+ clk,
+ rst,
+ tdata=output_axis_tdata,
+ tkeep=output_axis_tkeep,
+ tvalid=output_axis_tvalid,
+ tready=output_axis_tready,
+ tlast=output_axis_tlast,
+ tuser=output_axis_tuser,
+ pause=sink_pause,
+ name='sink'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=wb_adr_o,
+ dat_i=wb_dat_o,
+ dat_o=wb_dat_i,
+ we_i=wb_we_o,
+ sel_i=wb_sel_o,
+ stb_i=wb_stb_o,
+ ack_o=wb_ack_i,
+ cyc_i=wb_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='port0'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+
+ input_axis_tdata=input_axis_tdata,
+ input_axis_tkeep=input_axis_tkeep,
+ input_axis_tvalid=input_axis_tvalid,
+ input_axis_tready=input_axis_tready,
+ input_axis_tlast=input_axis_tlast,
+ input_axis_tuser=input_axis_tuser,
+
+ output_axis_tdata=output_axis_tdata,
+ output_axis_tkeep=output_axis_tkeep,
+ output_axis_tvalid=output_axis_tvalid,
+ output_axis_tready=output_axis_tready,
+ output_axis_tlast=output_axis_tlast,
+ output_axis_tuser=output_axis_tuser,
+
+ wb_adr_o=wb_adr_o,
+ wb_dat_i=wb_dat_i,
+ wb_dat_o=wb_dat_o,
+ wb_we_o=wb_we_o,
+ wb_sel_o=wb_sel_o,
+ wb_stb_o=wb_stb_o,
+ wb_ack_i=wb_ack_i,
+ wb_err_i=wb_err_i,
+ wb_cyc_o=wb_cyc_o,
+
+ busy=busy
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ # testbench stimulus
+
+ yield clk.posedge
+ print("test 1: test write")
+ current_test.next = 1
+
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 0, 4)+b'\x11\x22\x33\x44'))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 0, 4)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: test read")
+ current_test.next = 2
+
+ source.write(bytearray(b'\xA1'+struct.pack('>IH', 0, 4)))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA3'+struct.pack('>IH', 0, 4)+b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: various writes")
+ current_test.next = 3
+
+ for length in range(1,9):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*16)
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 256*(16*offset+length)+offset, length)+b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(200)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 256*(16*offset+length)+offset, length)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: various reads")
+ current_test.next = 4
+
+ for length in range(1,9):
+ for offset in range(4,8):
+ source.write(bytearray(b'\xA1'+struct.pack('>IH', 256*(16*offset+length)+offset, length)))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(200)
+
+ yield clk.posedge
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA3'+struct.pack('>IH', 256*(16*offset+length)+offset, length)+b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 5: test leading padding")
+ current_test.next = 5
+
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 4, 1)+b'\xAA'))
+ source.write(bytearray(b'\x00'*8+b'\xA2'+struct.pack('>IH', 5, 1)+b'\xBB'))
+ source.write(bytearray(b'\x00'*8+b'\xA1'+struct.pack('>IH', 4, 1)))
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 6, 1)+b'\xCC'))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4, 3) == b'\xAA\x00\xCC'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 4, 1)+b'\xA4'+struct.pack('>IH', 6, 1)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 6: test trailing padding")
+ current_test.next = 6
+
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 7, 1)+b'\xAA'))
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 8, 1)+b'\xBB'+b'\x00'*8))
+ source.write(bytearray(b'\xA1'+struct.pack('>IH', 7, 1)+b'\x00'*8))
+ source.write(bytearray(b'\xA1'+struct.pack('>IH', 7, 1)+b'\x00'*1))
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 9, 1)+b'\xCC'))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(7, 3) == b'\xAA\xBB\xCC'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 7, 1)+\
+ b'\xA4'+struct.pack('>IH', 8, 1)+\
+ b'\xA3'+struct.pack('>IH', 7, 1)+b'\xAA'+\
+ b'\xA3'+struct.pack('>IH', 7, 1)+b'\xAA'+\
+ b'\xA4'+struct.pack('>IH', 9, 1)
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32.v b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32.v
new file mode 100644
index 0000000..934d19c
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32.v
@@ -0,0 +1,154 @@
+/*
+
+Copyright (c) 2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for axis_wb_master
+ */
+module test_axis_wb_master_8_32;
+
+// Parameters
+parameter IMPLICIT_FRAMING = 0;
+parameter COUNT_SIZE = 16;
+parameter AXIS_DATA_WIDTH = 8;
+parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
+parameter WB_DATA_WIDTH = 32;
+parameter WB_ADDR_WIDTH = 32;
+parameter WB_SELECT_WIDTH = (WB_DATA_WIDTH/8);
+parameter READ_REQ = 8'hA1;
+parameter WRITE_REQ = 8'hA2;
+parameter READ_RESP = 8'hA3;
+parameter WRITE_RESP = 8'hA4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [AXIS_DATA_WIDTH-1:0] input_axis_tdata = 0;
+reg [AXIS_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
+reg input_axis_tvalid = 0;
+reg input_axis_tlast = 0;
+reg input_axis_tuser = 0;
+reg output_axis_tready = 0;
+reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
+reg wb_ack_i = 0;
+reg wb_err_i = 0;
+
+// Outputs
+wire input_axis_tready;
+wire [AXIS_DATA_WIDTH-1:0] output_axis_tdata;
+wire [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep;
+wire output_axis_tvalid;
+wire output_axis_tlast;
+wire output_axis_tuser;
+wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
+wire [WB_DATA_WIDTH-1:0] wb_dat_o;
+wire wb_we_o;
+wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
+wire wb_stb_o;
+wire wb_cyc_o;
+wire busy;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ input_axis_tdata,
+ input_axis_tkeep,
+ input_axis_tvalid,
+ input_axis_tlast,
+ input_axis_tuser,
+ output_axis_tready,
+ wb_dat_i,
+ wb_ack_i,
+ wb_err_i
+ );
+ $to_myhdl(
+ input_axis_tready,
+ output_axis_tdata,
+ output_axis_tkeep,
+ output_axis_tvalid,
+ output_axis_tlast,
+ output_axis_tuser,
+ wb_adr_o,
+ wb_dat_o,
+ wb_we_o,
+ wb_sel_o,
+ wb_stb_o,
+ wb_cyc_o,
+ busy
+ );
+
+ // dump file
+ $dumpfile("test_axis_wb_master_8_32.lxt");
+ $dumpvars(0, test_axis_wb_master_8_32);
+end
+
+axis_wb_master #(
+ .IMPLICIT_FRAMING(IMPLICIT_FRAMING),
+ .COUNT_SIZE(COUNT_SIZE),
+ .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+ .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+ .WB_DATA_WIDTH(WB_DATA_WIDTH),
+ .WB_ADDR_WIDTH(WB_ADDR_WIDTH),
+ .WB_SELECT_WIDTH(WB_SELECT_WIDTH),
+ .READ_REQ(READ_REQ),
+ .WRITE_REQ(WRITE_REQ),
+ .READ_RESP(READ_RESP),
+ .WRITE_RESP(WRITE_RESP)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .input_axis_tdata(input_axis_tdata),
+ .input_axis_tkeep(input_axis_tkeep),
+ .input_axis_tvalid(input_axis_tvalid),
+ .input_axis_tready(input_axis_tready),
+ .input_axis_tlast(input_axis_tlast),
+ .input_axis_tuser(input_axis_tuser),
+ .output_axis_tdata(output_axis_tdata),
+ .output_axis_tkeep(output_axis_tkeep),
+ .output_axis_tvalid(output_axis_tvalid),
+ .output_axis_tready(output_axis_tready),
+ .output_axis_tlast(output_axis_tlast),
+ .output_axis_tuser(output_axis_tuser),
+ .wb_adr_o(wb_adr_o),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(wb_dat_o),
+ .wb_we_o(wb_we_o),
+ .wb_sel_o(wb_sel_o),
+ .wb_stb_o(wb_stb_o),
+ .wb_ack_i(wb_ack_i),
+ .wb_err_i(wb_err_i),
+ .wb_cyc_o(wb_cyc_o),
+ .busy(busy)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_16.py b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_16.py
new file mode 100755
index 0000000..f98d260
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_16.py
@@ -0,0 +1,362 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+import struct
+
+import axis_ep
+import wb
+
+module = 'axis_wb_master'
+testbench = 'test_%s_8_32_16' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ IMPLICIT_FRAMING = 0
+ COUNT_SIZE = 16
+ AXIS_DATA_WIDTH = 8
+ AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)
+ WB_DATA_WIDTH = 32
+ WB_ADDR_WIDTH = 31
+ WB_SELECT_WIDTH = 2
+ READ_REQ = 0xA1
+ WRITE_REQ = 0xA2
+ READ_RESP = 0xA3
+ WRITE_RESP = 0xA4
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ input_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
+ input_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
+ input_axis_tvalid = Signal(bool(0))
+ input_axis_tlast = Signal(bool(0))
+ input_axis_tuser = Signal(bool(0))
+ output_axis_tready = Signal(bool(0))
+ wb_dat_i = Signal(intbv(0)[WB_DATA_WIDTH:])
+ wb_ack_i = Signal(bool(0))
+ wb_err_i = Signal(bool(0))
+
+ # Outputs
+ input_axis_tready = Signal(bool(0))
+ output_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
+ output_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
+ output_axis_tvalid = Signal(bool(0))
+ output_axis_tlast = Signal(bool(0))
+ output_axis_tuser = Signal(bool(0))
+ wb_adr_o = Signal(intbv(0)[WB_ADDR_WIDTH:])
+ wb_dat_o = Signal(intbv(0)[WB_DATA_WIDTH:])
+ wb_we_o = Signal(bool(0))
+ wb_sel_o = Signal(intbv(0)[WB_SELECT_WIDTH:])
+ wb_stb_o = Signal(bool(0))
+ wb_cyc_o = Signal(bool(0))
+ busy = Signal(bool(0))
+
+ # sources and sinks
+ source_pause = Signal(bool(0))
+ sink_pause = Signal(bool(0))
+
+ source = axis_ep.AXIStreamSource()
+
+ source_logic = source.create_logic(
+ clk,
+ rst,
+ tdata=input_axis_tdata,
+ tkeep=input_axis_tkeep,
+ tvalid=input_axis_tvalid,
+ tready=input_axis_tready,
+ tlast=input_axis_tlast,
+ tuser=input_axis_tuser,
+ pause=source_pause,
+ name='source'
+ )
+
+ sink = axis_ep.AXIStreamSink()
+
+ sink_logic = sink.create_logic(
+ clk,
+ rst,
+ tdata=output_axis_tdata,
+ tkeep=output_axis_tkeep,
+ tvalid=output_axis_tvalid,
+ tready=output_axis_tready,
+ tlast=output_axis_tlast,
+ tuser=output_axis_tuser,
+ pause=sink_pause,
+ name='sink'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=wb_adr_o,
+ dat_i=wb_dat_o,
+ dat_o=wb_dat_i,
+ we_i=wb_we_o,
+ sel_i=wb_sel_o,
+ stb_i=wb_stb_o,
+ ack_o=wb_ack_i,
+ cyc_i=wb_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='port0'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+
+ input_axis_tdata=input_axis_tdata,
+ input_axis_tkeep=input_axis_tkeep,
+ input_axis_tvalid=input_axis_tvalid,
+ input_axis_tready=input_axis_tready,
+ input_axis_tlast=input_axis_tlast,
+ input_axis_tuser=input_axis_tuser,
+
+ output_axis_tdata=output_axis_tdata,
+ output_axis_tkeep=output_axis_tkeep,
+ output_axis_tvalid=output_axis_tvalid,
+ output_axis_tready=output_axis_tready,
+ output_axis_tlast=output_axis_tlast,
+ output_axis_tuser=output_axis_tuser,
+
+ wb_adr_o=wb_adr_o,
+ wb_dat_i=wb_dat_i,
+ wb_dat_o=wb_dat_o,
+ wb_we_o=wb_we_o,
+ wb_sel_o=wb_sel_o,
+ wb_stb_o=wb_stb_o,
+ wb_ack_i=wb_ack_i,
+ wb_err_i=wb_err_i,
+ wb_cyc_o=wb_cyc_o,
+
+ busy=busy
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ # testbench stimulus
+
+ yield clk.posedge
+ print("test 1: test write")
+ current_test.next = 1
+
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 0, 4)+b'\x11\x22\x33\x44'))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 0, 4)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: test read")
+ current_test.next = 2
+
+ source.write(bytearray(b'\xA1'+struct.pack('>IH', 0, 4)))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA3'+struct.pack('>IH', 0, 4)+b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: various writes")
+ current_test.next = 3
+
+ for length in range(1,9):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*32)
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 256*(16*offset+length)+offset, length)+b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(200)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-2, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length+1, 1) == b'\xAA'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 256*(16*offset+length)+offset, length)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: various reads")
+ current_test.next = 4
+
+ for length in range(1,9):
+ for offset in range(4,8):
+ source.write(bytearray(b'\xA1'+struct.pack('>IH', 256*(16*offset+length)+offset, length)))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(200)
+
+ yield clk.posedge
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA3'+struct.pack('>IH', 256*(16*offset+length)+offset, length)+b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 5: test leading padding")
+ current_test.next = 5
+
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 4, 2)+b'\xAA\xBB'))
+ source.write(bytearray(b'\x00'*8+b'\xA2'+struct.pack('>IH', 6, 2)+b'\xCC\xDD'))
+ source.write(bytearray(b'\x00'*8+b'\xA1'+struct.pack('>IH', 4, 2)))
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 8, 2)+b'\xEE\xFF'))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4, 6) == b'\xAA\xBB\x00\x00\xEE\xFF'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 4, 2)+b'\xA4'+struct.pack('>IH', 8, 2)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 6: test trailing padding")
+ current_test.next = 6
+
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 10, 2)+b'\xAA\xBB'))
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 12, 2)+b'\xCC\xDD'+b'\x00'*8))
+ source.write(bytearray(b'\xA1'+struct.pack('>IH', 10, 2)+b'\x00'*8))
+ source.write(bytearray(b'\xA1'+struct.pack('>IH', 10, 2)+b'\x00'*1))
+ source.write(bytearray(b'\xA2'+struct.pack('>IH', 14, 2)+b'\xEE\xFF'))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(10, 6) == b'\xAA\xBB\xCC\xDD\xEE\xFF'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 10, 2)+\
+ b'\xA4'+struct.pack('>IH', 12, 2)+\
+ b'\xA3'+struct.pack('>IH', 10, 2)+b'\xAA\xBB'+\
+ b'\xA3'+struct.pack('>IH', 10, 2)+b'\xAA\xBB'+\
+ b'\xA4'+struct.pack('>IH', 14, 2)
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_16.v b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_16.v
new file mode 100644
index 0000000..2f3fb60
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_16.v
@@ -0,0 +1,154 @@
+/*
+
+Copyright (c) 2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for axis_wb_master
+ */
+module test_axis_wb_master_8_32_16;
+
+// Parameters
+parameter IMPLICIT_FRAMING = 0;
+parameter COUNT_SIZE = 16;
+parameter AXIS_DATA_WIDTH = 8;
+parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
+parameter WB_DATA_WIDTH = 32;
+parameter WB_ADDR_WIDTH = 31;
+parameter WB_SELECT_WIDTH = 2;
+parameter READ_REQ = 8'hA1;
+parameter WRITE_REQ = 8'hA2;
+parameter READ_RESP = 8'hA3;
+parameter WRITE_RESP = 8'hA4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [AXIS_DATA_WIDTH-1:0] input_axis_tdata = 0;
+reg [AXIS_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
+reg input_axis_tvalid = 0;
+reg input_axis_tlast = 0;
+reg input_axis_tuser = 0;
+reg output_axis_tready = 0;
+reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
+reg wb_ack_i = 0;
+reg wb_err_i = 0;
+
+// Outputs
+wire input_axis_tready;
+wire [AXIS_DATA_WIDTH-1:0] output_axis_tdata;
+wire [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep;
+wire output_axis_tvalid;
+wire output_axis_tlast;
+wire output_axis_tuser;
+wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
+wire [WB_DATA_WIDTH-1:0] wb_dat_o;
+wire wb_we_o;
+wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
+wire wb_stb_o;
+wire wb_cyc_o;
+wire busy;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ input_axis_tdata,
+ input_axis_tkeep,
+ input_axis_tvalid,
+ input_axis_tlast,
+ input_axis_tuser,
+ output_axis_tready,
+ wb_dat_i,
+ wb_ack_i,
+ wb_err_i
+ );
+ $to_myhdl(
+ input_axis_tready,
+ output_axis_tdata,
+ output_axis_tkeep,
+ output_axis_tvalid,
+ output_axis_tlast,
+ output_axis_tuser,
+ wb_adr_o,
+ wb_dat_o,
+ wb_we_o,
+ wb_sel_o,
+ wb_stb_o,
+ wb_cyc_o,
+ busy
+ );
+
+ // dump file
+ $dumpfile("test_axis_wb_master_8_32_16.lxt");
+ $dumpvars(0, test_axis_wb_master_8_32_16);
+end
+
+axis_wb_master #(
+ .IMPLICIT_FRAMING(IMPLICIT_FRAMING),
+ .COUNT_SIZE(COUNT_SIZE),
+ .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+ .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+ .WB_DATA_WIDTH(WB_DATA_WIDTH),
+ .WB_ADDR_WIDTH(WB_ADDR_WIDTH),
+ .WB_SELECT_WIDTH(WB_SELECT_WIDTH),
+ .READ_REQ(READ_REQ),
+ .WRITE_REQ(WRITE_REQ),
+ .READ_RESP(READ_RESP),
+ .WRITE_RESP(WRITE_RESP)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .input_axis_tdata(input_axis_tdata),
+ .input_axis_tkeep(input_axis_tkeep),
+ .input_axis_tvalid(input_axis_tvalid),
+ .input_axis_tready(input_axis_tready),
+ .input_axis_tlast(input_axis_tlast),
+ .input_axis_tuser(input_axis_tuser),
+ .output_axis_tdata(output_axis_tdata),
+ .output_axis_tkeep(output_axis_tkeep),
+ .output_axis_tvalid(output_axis_tvalid),
+ .output_axis_tready(output_axis_tready),
+ .output_axis_tlast(output_axis_tlast),
+ .output_axis_tuser(output_axis_tuser),
+ .wb_adr_o(wb_adr_o),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(wb_dat_o),
+ .wb_we_o(wb_we_o),
+ .wb_sel_o(wb_sel_o),
+ .wb_stb_o(wb_stb_o),
+ .wb_ack_i(wb_ack_i),
+ .wb_err_i(wb_err_i),
+ .wb_cyc_o(wb_cyc_o),
+ .busy(busy)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_imp.py b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_imp.py
new file mode 100755
index 0000000..b0b8b42
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_imp.py
@@ -0,0 +1,357 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+import struct
+
+import axis_ep
+import wb
+
+module = 'axis_wb_master'
+testbench = 'test_%s_8_32_imp' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ IMPLICIT_FRAMING = 0
+ COUNT_SIZE = 16
+ AXIS_DATA_WIDTH = 8
+ AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)
+ WB_DATA_WIDTH = 32
+ WB_ADDR_WIDTH = 32
+ WB_SELECT_WIDTH = (WB_DATA_WIDTH/8)
+ READ_REQ = 0xA1
+ WRITE_REQ = 0xA2
+ READ_RESP = 0xA3
+ WRITE_RESP = 0xA4
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ input_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
+ input_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
+ input_axis_tvalid = Signal(bool(0))
+ input_axis_tlast = Signal(bool(0))
+ input_axis_tuser = Signal(bool(0))
+ output_axis_tready = Signal(bool(0))
+ wb_dat_i = Signal(intbv(0)[WB_DATA_WIDTH:])
+ wb_ack_i = Signal(bool(0))
+ wb_err_i = Signal(bool(0))
+
+ # Outputs
+ input_axis_tready = Signal(bool(0))
+ output_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
+ output_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
+ output_axis_tvalid = Signal(bool(0))
+ output_axis_tlast = Signal(bool(0))
+ output_axis_tuser = Signal(bool(0))
+ wb_adr_o = Signal(intbv(0)[WB_ADDR_WIDTH:])
+ wb_dat_o = Signal(intbv(0)[WB_DATA_WIDTH:])
+ wb_we_o = Signal(bool(0))
+ wb_sel_o = Signal(intbv(0)[WB_SELECT_WIDTH:])
+ wb_stb_o = Signal(bool(0))
+ wb_cyc_o = Signal(bool(0))
+ busy = Signal(bool(0))
+
+ # sources and sinks
+ source_pause = Signal(bool(0))
+ sink_pause = Signal(bool(0))
+
+ source = axis_ep.AXIStreamSource()
+
+ source_logic = source.create_logic(
+ clk,
+ rst,
+ tdata=input_axis_tdata,
+ tkeep=input_axis_tkeep,
+ tvalid=input_axis_tvalid,
+ tready=input_axis_tready,
+ tlast=input_axis_tlast,
+ tuser=input_axis_tuser,
+ pause=source_pause,
+ name='source'
+ )
+
+ sink = axis_ep.AXIStreamSink()
+
+ sink_logic = sink.create_logic(
+ clk,
+ rst,
+ tdata=output_axis_tdata,
+ tkeep=output_axis_tkeep,
+ tvalid=output_axis_tvalid,
+ tready=output_axis_tready,
+ tlast=output_axis_tlast,
+ tuser=output_axis_tuser,
+ pause=sink_pause,
+ name='sink'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=wb_adr_o,
+ dat_i=wb_dat_o,
+ dat_o=wb_dat_i,
+ we_i=wb_we_o,
+ sel_i=wb_sel_o,
+ stb_i=wb_stb_o,
+ ack_o=wb_ack_i,
+ cyc_i=wb_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='port0'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+
+ input_axis_tdata=input_axis_tdata,
+ input_axis_tkeep=input_axis_tkeep,
+ input_axis_tvalid=input_axis_tvalid,
+ input_axis_tready=input_axis_tready,
+ input_axis_tlast=input_axis_tlast,
+ input_axis_tuser=input_axis_tuser,
+
+ output_axis_tdata=output_axis_tdata,
+ output_axis_tkeep=output_axis_tkeep,
+ output_axis_tvalid=output_axis_tvalid,
+ output_axis_tready=output_axis_tready,
+ output_axis_tlast=output_axis_tlast,
+ output_axis_tuser=output_axis_tuser,
+
+ wb_adr_o=wb_adr_o,
+ wb_dat_i=wb_dat_i,
+ wb_dat_o=wb_dat_o,
+ wb_we_o=wb_we_o,
+ wb_sel_o=wb_sel_o,
+ wb_stb_o=wb_stb_o,
+ wb_ack_i=wb_ack_i,
+ wb_err_i=wb_err_i,
+ wb_cyc_o=wb_cyc_o,
+
+ busy=busy
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ # testbench stimulus
+
+ yield clk.posedge
+ print("test 1: test write")
+ current_test.next = 1
+
+ source.send(bytearray(b'\xA2'+struct.pack('>IH', 0, 4)+b'\x11\x22\x33\x44'))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 0, 4)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: test read")
+ current_test.next = 2
+
+ source.send(bytearray(b'\xA1'+struct.pack('>IH', 0, 4)))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA3'+struct.pack('>IH', 0, 4)+b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: various writes")
+ current_test.next = 3
+
+ for length in range(1,9):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*16)
+ source.send(bytearray(b'\xA2'+struct.pack('>IH', 256*(16*offset+length)+offset, length)+b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(200)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 256*(16*offset+length)+offset, length)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: various reads")
+ current_test.next = 4
+
+ for length in range(1,9):
+ for offset in range(4,8):
+ source.send(bytearray(b'\xA1'+struct.pack('>IH', 256*(16*offset+length)+offset, length)))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(200)
+
+ yield clk.posedge
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA3'+struct.pack('>IH', 256*(16*offset+length)+offset, length)+b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 5: test leading padding")
+ current_test.next = 5
+
+ source.send(bytearray(b'\xA2'+struct.pack('>IH', 4, 1)+b'\xAA'))
+ source.send(bytearray(b'\x00'*8+b'\xA2'+struct.pack('>IH', 5, 1)+b'\xBB'))
+ source.send(bytearray(b'\x00'*8+b'\xA1'+struct.pack('>IH', 4, 1)))
+ source.send(bytearray(b'\xA2'+struct.pack('>IH', 6, 1)+b'\xCC'))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4, 3) == b'\xAA\xBB\xCC'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 4, 1)+b'\xA4'+struct.pack('>IH', 5, 1)+b'\xA3'+struct.pack('>IH', 4, 1)+b'\xAA'+b'\xA4'+struct.pack('>IH', 6, 1)
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 6: test trailing padding")
+ current_test.next = 6
+
+ source.send(bytearray(b'\xA2'+struct.pack('>IH', 7, 1)+b'\xAA'))
+ source.send(bytearray(b'\xA2'+struct.pack('>IH', 8, 1)+b'\xBB'+b'\x00'*8))
+ source.send(bytearray(b'\xA1'+struct.pack('>IH', 7, 1)+b'\x00'*8))
+ source.send(bytearray(b'\xA2'+struct.pack('>IH', 9, 1)+b'\xCC'))
+ yield clk.posedge
+
+ yield input_axis_tvalid.negedge
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(7, 3) == b'\xAA\xBB\xCC'
+
+ rx_data = bytearray(sink.read())
+ print(repr(rx_data))
+ assert rx_data == b'\xA4'+struct.pack('>IH', 7, 1)+b'\xA4'+struct.pack('>IH', 8, 1)+b'\xA3'+struct.pack('>IH', 7, 1)+b'\xAA'+b'\xA4'+struct.pack('>IH', 9, 1)
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_imp.v b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_imp.v
new file mode 100644
index 0000000..2ce0b2b
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_axis_wb_master_8_32_imp.v
@@ -0,0 +1,154 @@
+/*
+
+Copyright (c) 2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for axis_wb_master
+ */
+module test_axis_wb_master_8_32_imp;
+
+// Parameters
+parameter IMPLICIT_FRAMING = 1;
+parameter COUNT_SIZE = 16;
+parameter AXIS_DATA_WIDTH = 8;
+parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
+parameter WB_DATA_WIDTH = 32;
+parameter WB_ADDR_WIDTH = 32;
+parameter WB_SELECT_WIDTH = (WB_DATA_WIDTH/8);
+parameter READ_REQ = 8'hA1;
+parameter WRITE_REQ = 8'hA2;
+parameter READ_RESP = 8'hA3;
+parameter WRITE_RESP = 8'hA4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [AXIS_DATA_WIDTH-1:0] input_axis_tdata = 0;
+reg [AXIS_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
+reg input_axis_tvalid = 0;
+reg input_axis_tlast = 0;
+reg input_axis_tuser = 0;
+reg output_axis_tready = 0;
+reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
+reg wb_ack_i = 0;
+reg wb_err_i = 0;
+
+// Outputs
+wire input_axis_tready;
+wire [AXIS_DATA_WIDTH-1:0] output_axis_tdata;
+wire [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep;
+wire output_axis_tvalid;
+wire output_axis_tlast;
+wire output_axis_tuser;
+wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
+wire [WB_DATA_WIDTH-1:0] wb_dat_o;
+wire wb_we_o;
+wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
+wire wb_stb_o;
+wire wb_cyc_o;
+wire busy;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ input_axis_tdata,
+ input_axis_tkeep,
+ input_axis_tvalid,
+ input_axis_tlast,
+ input_axis_tuser,
+ output_axis_tready,
+ wb_dat_i,
+ wb_ack_i,
+ wb_err_i
+ );
+ $to_myhdl(
+ input_axis_tready,
+ output_axis_tdata,
+ output_axis_tkeep,
+ output_axis_tvalid,
+ output_axis_tlast,
+ output_axis_tuser,
+ wb_adr_o,
+ wb_dat_o,
+ wb_we_o,
+ wb_sel_o,
+ wb_stb_o,
+ wb_cyc_o,
+ busy
+ );
+
+ // dump file
+ $dumpfile("test_axis_wb_master_8_32_imp.lxt");
+ $dumpvars(0, test_axis_wb_master_8_32_imp);
+end
+
+axis_wb_master #(
+ .IMPLICIT_FRAMING(IMPLICIT_FRAMING),
+ .COUNT_SIZE(COUNT_SIZE),
+ .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+ .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+ .WB_DATA_WIDTH(WB_DATA_WIDTH),
+ .WB_ADDR_WIDTH(WB_ADDR_WIDTH),
+ .WB_SELECT_WIDTH(WB_SELECT_WIDTH),
+ .READ_REQ(READ_REQ),
+ .WRITE_REQ(WRITE_REQ),
+ .READ_RESP(READ_RESP),
+ .WRITE_RESP(WRITE_RESP)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .input_axis_tdata(input_axis_tdata),
+ .input_axis_tkeep(input_axis_tkeep),
+ .input_axis_tvalid(input_axis_tvalid),
+ .input_axis_tready(input_axis_tready),
+ .input_axis_tlast(input_axis_tlast),
+ .input_axis_tuser(input_axis_tuser),
+ .output_axis_tdata(output_axis_tdata),
+ .output_axis_tkeep(output_axis_tkeep),
+ .output_axis_tvalid(output_axis_tvalid),
+ .output_axis_tready(output_axis_tready),
+ .output_axis_tlast(output_axis_tlast),
+ .output_axis_tuser(output_axis_tuser),
+ .wb_adr_o(wb_adr_o),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(wb_dat_o),
+ .wb_we_o(wb_we_o),
+ .wb_sel_o(wb_sel_o),
+ .wb_stb_o(wb_stb_o),
+ .wb_ack_i(wb_ack_i),
+ .wb_err_i(wb_err_i),
+ .wb_cyc_o(wb_cyc_o),
+ .busy(busy)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_priority_encoder.py b/ip/third_party/verilog-wishbone/tb/test_priority_encoder.py
new file mode 100755
index 0000000..747e96e
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_priority_encoder.py
@@ -0,0 +1,134 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2014-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+module = 'priority_encoder'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ WIDTH = 32
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ input_unencoded = Signal(intbv(0)[WIDTH:])
+
+ # Outputs
+ output_valid = Signal(bool(0))
+ output_encoded = Signal(intbv(0)[5:])
+ output_unencoded = Signal(intbv(0)[WIDTH:])
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+
+ input_unencoded=input_unencoded,
+
+ output_valid=output_valid,
+ output_encoded=output_encoded,
+ output_unencoded=output_unencoded
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+
+ print("test 1: one bit")
+ current_test.next = 1
+
+ for i in range(32):
+ input_unencoded.next = 1 << i
+
+ yield clk.posedge
+
+ assert output_encoded == i
+ assert output_unencoded == 1 << i
+
+ yield delay(100)
+
+ yield clk.posedge
+
+ print("test 2: two bits")
+ current_test.next = 2
+
+ for i in range(32):
+ for j in range(32):
+
+ input_unencoded.next = (1 << i) | (1 << j)
+
+ yield clk.posedge
+
+ assert output_encoded == max(i,j)
+ assert output_unencoded == 1 << max(i,j)
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ os.chdir(os.path.dirname(os.path.abspath(__file__)))
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
+
diff --git a/ip/third_party/verilog-wishbone/tb/test_priority_encoder.v b/ip/third_party/verilog-wishbone/tb/test_priority_encoder.v
new file mode 100644
index 0000000..8d6787e
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_priority_encoder.v
@@ -0,0 +1,78 @@
+/*
+
+Copyright (c) 2014-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for priority_encoder
+ */
+module test_priority_encoder;
+
+// Parameters
+localparam WIDTH = 32;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [WIDTH-1:0] input_unencoded = 0;
+
+// Outputs
+wire output_valid;
+wire [$clog2(WIDTH)-1:0] output_encoded;
+wire [WIDTH-1:0] output_unencoded;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ input_unencoded
+ );
+ $to_myhdl(
+ output_valid,
+ output_encoded,
+ output_unencoded
+ );
+
+ // dump file
+ $dumpfile("test_priority_encoder.lxt");
+ $dumpvars(0, test_priority_encoder);
+end
+
+priority_encoder #(
+ .WIDTH(WIDTH)
+)
+UUT (
+ .input_unencoded(input_unencoded),
+ .output_valid(output_valid),
+ .output_encoded(output_encoded),
+ .output_unencoded(output_unencoded)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb.py b/ip/third_party/verilog-wishbone/tb/test_wb.py
new file mode 100755
index 0000000..ef3e62f
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb.py
@@ -0,0 +1,257 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+def bench():
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ port0_adr_i = Signal(intbv(0)[32:])
+ port0_dat_i = Signal(intbv(0)[32:])
+ port0_we_i = Signal(bool(0))
+ port0_sel_i = Signal(intbv(0)[4:])
+ port0_stb_i = Signal(bool(0))
+ port0_cyc_i = Signal(bool(0))
+
+ # Outputs
+ port0_dat_o = Signal(intbv(0)[32:])
+ port0_ack_o = Signal(bool(0))
+
+ # WB master
+ wb_master_inst = wb.WBMaster()
+
+ wb_master_logic = wb_master_inst.create_logic(
+ clk,
+ adr_o=port0_adr_i,
+ dat_i=port0_dat_o,
+ dat_o=port0_dat_i,
+ we_o=port0_we_i,
+ sel_o=port0_sel_i,
+ stb_o=port0_stb_i,
+ ack_i=port0_ack_o,
+ cyc_o=port0_cyc_i,
+ name='master'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=port0_adr_i,
+ dat_i=port0_dat_i,
+ dat_o=port0_dat_o,
+ we_i=port0_we_i,
+ sel_i=port0_sel_i,
+ stb_i=port0_stb_i,
+ ack_o=port0_ack_o,
+ cyc_i=port0_cyc_i,
+ latency=1,
+ asynchronous=False,
+ name='port0'
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+ print("test 1: baseline")
+ current_test.next = 1
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: direct write")
+ current_test.next = 2
+
+ wb_ram_inst.write_mem(0, b'test')
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(0,4) == b'test'
+
+ yield clk.posedge
+ print("test 3: write via port0")
+ current_test.next = 3
+
+ wb_master_inst.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: read via port0")
+ current_test.next = 4
+
+ wb_master_inst.init_read(4, 4)
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_master_inst.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 5: various writes")
+ current_test.next = 5
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*32)
+ wb_master_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 6: various reads")
+ current_test.next = 6
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_master_inst.init_read(256*(16*offset+length)+offset, length)
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_master_inst.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 7: write words")
+ current_test.next = 7
+
+ for offset in range(4):
+ wb_master_inst.init_write_words((0x4000+offset*64+0)/2+offset, [0x1234])
+ wb_master_inst.init_write_dwords((0x4000+offset*64+16)/4+offset, [0x12345678])
+ wb_master_inst.init_write_qwords((0x4000+offset*64+32)/8+offset, [0x1234567887654321])
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0x4000+offset*64, 64)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem((0x4000+offset*64+0)+offset*2, 2) == b'\x34\x12'
+ assert wb_ram_inst.read_mem((0x4000+offset*64+16)+offset*4, 4) == b'\x78\x56\x34\x12'
+ assert wb_ram_inst.read_mem((0x4000+offset*64+32)+offset*8, 8) == b'\x21\x43\x65\x87\x78\x56\x34\x12'
+
+ assert wb_ram_inst.read_words((0x4000+offset*64+0)/2+offset, 1)[0] == 0x1234
+ assert wb_ram_inst.read_dwords((0x4000+offset*64+16)/4+offset, 1)[0] == 0x12345678
+ assert wb_ram_inst.read_qwords((0x4000+offset*64+32)/8+offset, 1)[0] == 0x1234567887654321
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 8: read words")
+ current_test.next = 8
+
+ for offset in range(4):
+ wb_master_inst.init_read_words((0x4000+offset*64+0)/2+offset, 1)
+ wb_master_inst.init_read_dwords((0x4000+offset*64+16)/4+offset, 1)
+ wb_master_inst.init_read_qwords((0x4000+offset*64+32)/8+offset, 1)
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_master_inst.get_read_data_words()
+ assert data[0] == (0x4000+offset*64+0)/2+offset
+ assert data[1][0] == 0x1234
+
+ data = wb_master_inst.get_read_data_dwords()
+ assert data[0] == (0x4000+offset*64+16)/4+offset
+ assert data[1][0] == 0x12345678
+
+ data = wb_master_inst.get_read_data_qwords()
+ assert data[0] == (0x4000+offset*64+32)/8+offset
+ assert data[1][0] == 0x1234567887654321
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ os.chdir(os.path.dirname(os.path.abspath(__file__)))
+ #sim = Simulation(bench())
+ traceSignals.name = os.path.basename(__file__).rsplit('.',1)[0]
+ sim = Simulation(traceSignals(bench))
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
+
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_16.py b/ip/third_party/verilog-wishbone/tb/test_wb_16.py
new file mode 100755
index 0000000..8496d2a
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_16.py
@@ -0,0 +1,257 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+def bench():
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ port0_adr_i = Signal(intbv(0)[32:])
+ port0_dat_i = Signal(intbv(0)[32:])
+ port0_we_i = Signal(bool(0))
+ port0_sel_i = Signal(intbv(0)[2:])
+ port0_stb_i = Signal(bool(0))
+ port0_cyc_i = Signal(bool(0))
+
+ # Outputs
+ port0_dat_o = Signal(intbv(0)[32:])
+ port0_ack_o = Signal(bool(0))
+
+ # WB master
+ wb_master_inst = wb.WBMaster()
+
+ wb_master_logic = wb_master_inst.create_logic(
+ clk,
+ adr_o=port0_adr_i,
+ dat_i=port0_dat_o,
+ dat_o=port0_dat_i,
+ we_o=port0_we_i,
+ sel_o=port0_sel_i,
+ stb_o=port0_stb_i,
+ ack_i=port0_ack_o,
+ cyc_o=port0_cyc_i,
+ name='master'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=port0_adr_i,
+ dat_i=port0_dat_i,
+ dat_o=port0_dat_o,
+ we_i=port0_we_i,
+ sel_i=port0_sel_i,
+ stb_i=port0_stb_i,
+ ack_o=port0_ack_o,
+ cyc_i=port0_cyc_i,
+ latency=1,
+ asynchronous=False,
+ name='port0'
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+ print("test 1: baseline")
+ current_test.next = 1
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: direct write")
+ current_test.next = 2
+
+ wb_ram_inst.write_mem(0, b'test')
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(0,4) == b'test'
+
+ yield clk.posedge
+ print("test 3: write via port0")
+ current_test.next = 3
+
+ wb_master_inst.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: read via port0")
+ current_test.next = 4
+
+ wb_master_inst.init_read(4, 4)
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_master_inst.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 5: various writes")
+ current_test.next = 5
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*32)
+ wb_master_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-2, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length+1, 1) == b'\xAA'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 6: various reads")
+ current_test.next = 6
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_master_inst.init_read(256*(16*offset+length)+offset, length)
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_master_inst.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 7: write words")
+ current_test.next = 7
+
+ for offset in range(4):
+ wb_master_inst.init_write_words((0x4000+offset*64+0)/2+offset, [0x1234])
+ wb_master_inst.init_write_dwords((0x4000+offset*64+16)/4+offset, [0x12345678])
+ wb_master_inst.init_write_qwords((0x4000+offset*64+32)/8+offset, [0x1234567887654321])
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0x4000+offset*64, 64)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem((0x4000+offset*64+0)+offset*2, 2) == b'\x34\x12'
+ assert wb_ram_inst.read_mem((0x4000+offset*64+16)+offset*4, 4) == b'\x78\x56\x34\x12'
+ assert wb_ram_inst.read_mem((0x4000+offset*64+32)+offset*8, 8) == b'\x21\x43\x65\x87\x78\x56\x34\x12'
+
+ assert wb_ram_inst.read_words((0x4000+offset*64+0)/2+offset, 1)[0] == 0x1234
+ assert wb_ram_inst.read_dwords((0x4000+offset*64+16)/4+offset, 1)[0] == 0x12345678
+ assert wb_ram_inst.read_qwords((0x4000+offset*64+32)/8+offset, 1)[0] == 0x1234567887654321
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 8: read words")
+ current_test.next = 8
+
+ for offset in range(4):
+ wb_master_inst.init_read_words((0x4000+offset*64+0)/2+offset, 1)
+ wb_master_inst.init_read_dwords((0x4000+offset*64+16)/4+offset, 1)
+ wb_master_inst.init_read_qwords((0x4000+offset*64+32)/8+offset, 1)
+
+ yield wb_master_inst.wait()
+ yield clk.posedge
+
+ data = wb_master_inst.get_read_data_words()
+ assert data[0] == (0x4000+offset*64+0)/2+offset
+ assert data[1][0] == 0x1234
+
+ data = wb_master_inst.get_read_data_dwords()
+ assert data[0] == (0x4000+offset*64+16)/4+offset
+ assert data[1][0] == 0x12345678
+
+ data = wb_master_inst.get_read_data_qwords()
+ assert data[0] == (0x4000+offset*64+32)/8+offset
+ assert data[1][0] == 0x1234567887654321
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ os.chdir(os.path.dirname(os.path.abspath(__file__)))
+ #sim = Simulation(bench())
+ traceSignals.name = os.path.basename(__file__).rsplit('.',1)[0]
+ sim = Simulation(traceSignals(bench))
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
+
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_adapter_16_32.py b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_16_32.py
new file mode 100755
index 0000000..3b32b46
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_16_32.py
@@ -0,0 +1,242 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_adapter'
+testbench = 'test_%s_16_32' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ ADDR_WIDTH = 32
+ WBM_DATA_WIDTH = 16
+ WBM_SELECT_WIDTH = 2
+ WBS_DATA_WIDTH = 32
+ WBS_SELECT_WIDTH = 4
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ wbm_dat_i = Signal(intbv(0)[WBM_DATA_WIDTH:])
+ wbm_we_i = Signal(bool(0))
+ wbm_sel_i = Signal(intbv(0)[WBM_SELECT_WIDTH:])
+ wbm_stb_i = Signal(bool(0))
+ wbm_cyc_i = Signal(bool(0))
+ wbs_dat_i = Signal(intbv(0)[WBS_DATA_WIDTH:])
+ wbs_ack_i = Signal(bool(0))
+ wbs_err_i = Signal(bool(0))
+ wbs_rty_i = Signal(bool(0))
+
+ # Outputs
+ wbm_dat_o = Signal(intbv(0)[WBM_DATA_WIDTH:])
+ wbm_ack_o = Signal(bool(0))
+ wbm_err_o = Signal(bool(0))
+ wbm_rty_o = Signal(bool(0))
+ wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs_dat_o = Signal(intbv(0)[WBS_DATA_WIDTH:])
+ wbs_we_o = Signal(bool(0))
+ wbs_sel_o = Signal(intbv(0)[WBS_SELECT_WIDTH:])
+ wbs_stb_o = Signal(bool(0))
+ wbs_cyc_o = Signal(bool(0))
+
+ # WB master
+ wbm_inst = wb.WBMaster()
+
+ wbm_logic = wbm_inst.create_logic(
+ clk,
+ adr_o=wbm_adr_i,
+ dat_i=wbm_dat_o,
+ dat_o=wbm_dat_i,
+ we_o=wbm_we_i,
+ sel_o=wbm_sel_i,
+ stb_o=wbm_stb_i,
+ ack_i=wbm_ack_o,
+ cyc_o=wbm_cyc_i,
+ name='master'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=wbs_adr_o,
+ dat_i=wbs_dat_o,
+ dat_o=wbs_dat_i,
+ we_i=wbs_we_o,
+ sel_i=wbs_sel_o,
+ stb_i=wbs_stb_o,
+ ack_o=wbs_ack_i,
+ cyc_i=wbs_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='slave'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+ wbm_adr_i=wbm_adr_i,
+ wbm_dat_i=wbm_dat_i,
+ wbm_dat_o=wbm_dat_o,
+ wbm_we_i=wbm_we_i,
+ wbm_sel_i=wbm_sel_i,
+ wbm_stb_i=wbm_stb_i,
+ wbm_ack_o=wbm_ack_o,
+ wbm_err_o=wbm_err_o,
+ wbm_rty_o=wbm_rty_o,
+ wbm_cyc_i=wbm_cyc_i,
+ wbs_adr_o=wbs_adr_o,
+ wbs_dat_i=wbs_dat_i,
+ wbs_dat_o=wbs_dat_o,
+ wbs_we_o=wbs_we_o,
+ wbs_sel_o=wbs_sel_o,
+ wbs_stb_o=wbs_stb_o,
+ wbs_ack_i=wbs_ack_i,
+ wbs_err_i=wbs_err_i,
+ wbs_rty_i=wbs_rty_i,
+ wbs_cyc_o=wbs_cyc_o
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+ print("test 1: write")
+ current_test.next = 1
+
+ wbm_inst.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: read")
+ current_test.next = 2
+
+ wbm_inst.init_read(4, 4)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: various writes")
+ current_test.next = 3
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*32)
+ wbm_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: various reads")
+ current_test.next = 4
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wbm_inst.init_read(256*(16*offset+length)+offset, length)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_adapter_16_32.v b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_16_32.v
new file mode 100644
index 0000000..cb658f8
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_16_32.v
@@ -0,0 +1,136 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_adapter
+ */
+module test_wb_adapter_16_32;
+
+// Parameters
+parameter ADDR_WIDTH = 32;
+parameter WBM_DATA_WIDTH = 16;
+parameter WBM_SELECT_WIDTH = 2;
+parameter WBS_DATA_WIDTH = 32;
+parameter WBS_SELECT_WIDTH = 4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
+reg [WBM_DATA_WIDTH-1:0] wbm_dat_i = 0;
+reg wbm_we_i = 0;
+reg [WBM_SELECT_WIDTH-1:0] wbm_sel_i = 0;
+reg wbm_stb_i = 0;
+reg wbm_cyc_i = 0;
+reg [WBS_DATA_WIDTH-1:0] wbs_dat_i = 0;
+reg wbs_ack_i = 0;
+reg wbs_err_i = 0;
+reg wbs_rty_i = 0;
+
+// Outputs
+wire [WBM_DATA_WIDTH-1:0] wbm_dat_o;
+wire wbm_ack_o;
+wire wbm_err_o;
+wire wbm_rty_o;
+wire [ADDR_WIDTH-1:0] wbs_adr_o;
+wire [WBS_DATA_WIDTH-1:0] wbs_dat_o;
+wire wbs_we_o;
+wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o;
+wire wbs_stb_o;
+wire wbs_cyc_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ wbm_adr_i,
+ wbm_dat_i,
+ wbm_we_i,
+ wbm_sel_i,
+ wbm_stb_i,
+ wbm_cyc_i,
+ wbs_dat_i,
+ wbs_ack_i,
+ wbs_err_i,
+ wbs_rty_i
+ );
+ $to_myhdl(
+ wbm_dat_o,
+ wbm_ack_o,
+ wbm_err_o,
+ wbm_rty_o,
+ wbs_adr_o,
+ wbs_dat_o,
+ wbs_we_o,
+ wbs_sel_o,
+ wbs_stb_o,
+ wbs_cyc_o
+ );
+
+ // dump file
+ $dumpfile("test_wb_adapter_16_32.lxt");
+ $dumpvars(0, test_wb_adapter_16_32);
+end
+
+wb_adapter #(
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .WBM_DATA_WIDTH(WBM_DATA_WIDTH),
+ .WBM_SELECT_WIDTH(WBM_SELECT_WIDTH),
+ .WBS_DATA_WIDTH(WBS_DATA_WIDTH),
+ .WBS_SELECT_WIDTH(WBS_SELECT_WIDTH)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .wbm_adr_i(wbm_adr_i),
+ .wbm_dat_i(wbm_dat_i),
+ .wbm_dat_o(wbm_dat_o),
+ .wbm_we_i(wbm_we_i),
+ .wbm_sel_i(wbm_sel_i),
+ .wbm_stb_i(wbm_stb_i),
+ .wbm_ack_o(wbm_ack_o),
+ .wbm_err_o(wbm_err_o),
+ .wbm_rty_o(wbm_rty_o),
+ .wbm_cyc_i(wbm_cyc_i),
+ .wbs_adr_o(wbs_adr_o),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_dat_o(wbs_dat_o),
+ .wbs_we_o(wbs_we_o),
+ .wbs_sel_o(wbs_sel_o),
+ .wbs_stb_o(wbs_stb_o),
+ .wbs_ack_i(wbs_ack_i),
+ .wbs_err_i(wbs_err_i),
+ .wbs_rty_i(wbs_rty_i),
+ .wbs_cyc_o(wbs_cyc_o)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_16.py b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_16.py
new file mode 100755
index 0000000..a2cb1b1
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_16.py
@@ -0,0 +1,242 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_adapter'
+testbench = 'test_%s_32_16' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ ADDR_WIDTH = 32
+ WBM_DATA_WIDTH = 32
+ WBM_SELECT_WIDTH = 4
+ WBS_DATA_WIDTH = 16
+ WBS_SELECT_WIDTH = 2
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ wbm_dat_i = Signal(intbv(0)[WBM_DATA_WIDTH:])
+ wbm_we_i = Signal(bool(0))
+ wbm_sel_i = Signal(intbv(0)[WBM_SELECT_WIDTH:])
+ wbm_stb_i = Signal(bool(0))
+ wbm_cyc_i = Signal(bool(0))
+ wbs_dat_i = Signal(intbv(0)[WBS_DATA_WIDTH:])
+ wbs_ack_i = Signal(bool(0))
+ wbs_err_i = Signal(bool(0))
+ wbs_rty_i = Signal(bool(0))
+
+ # Outputs
+ wbm_dat_o = Signal(intbv(0)[WBM_DATA_WIDTH:])
+ wbm_ack_o = Signal(bool(0))
+ wbm_err_o = Signal(bool(0))
+ wbm_rty_o = Signal(bool(0))
+ wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs_dat_o = Signal(intbv(0)[WBS_DATA_WIDTH:])
+ wbs_we_o = Signal(bool(0))
+ wbs_sel_o = Signal(intbv(0)[WBS_SELECT_WIDTH:])
+ wbs_stb_o = Signal(bool(0))
+ wbs_cyc_o = Signal(bool(0))
+
+ # WB master
+ wbm_inst = wb.WBMaster()
+
+ wbm_logic = wbm_inst.create_logic(
+ clk,
+ adr_o=wbm_adr_i,
+ dat_i=wbm_dat_o,
+ dat_o=wbm_dat_i,
+ we_o=wbm_we_i,
+ sel_o=wbm_sel_i,
+ stb_o=wbm_stb_i,
+ ack_i=wbm_ack_o,
+ cyc_o=wbm_cyc_i,
+ name='master'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=wbs_adr_o,
+ dat_i=wbs_dat_o,
+ dat_o=wbs_dat_i,
+ we_i=wbs_we_o,
+ sel_i=wbs_sel_o,
+ stb_i=wbs_stb_o,
+ ack_o=wbs_ack_i,
+ cyc_i=wbs_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='slave'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+ wbm_adr_i=wbm_adr_i,
+ wbm_dat_i=wbm_dat_i,
+ wbm_dat_o=wbm_dat_o,
+ wbm_we_i=wbm_we_i,
+ wbm_sel_i=wbm_sel_i,
+ wbm_stb_i=wbm_stb_i,
+ wbm_ack_o=wbm_ack_o,
+ wbm_err_o=wbm_err_o,
+ wbm_rty_o=wbm_rty_o,
+ wbm_cyc_i=wbm_cyc_i,
+ wbs_adr_o=wbs_adr_o,
+ wbs_dat_i=wbs_dat_i,
+ wbs_dat_o=wbs_dat_o,
+ wbs_we_o=wbs_we_o,
+ wbs_sel_o=wbs_sel_o,
+ wbs_stb_o=wbs_stb_o,
+ wbs_ack_i=wbs_ack_i,
+ wbs_err_i=wbs_err_i,
+ wbs_rty_i=wbs_rty_i,
+ wbs_cyc_o=wbs_cyc_o
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+ print("test 1: write")
+ current_test.next = 1
+
+ wbm_inst.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: read")
+ current_test.next = 2
+
+ wbm_inst.init_read(4, 4)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: various writes")
+ current_test.next = 3
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*32)
+ wbm_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: various reads")
+ current_test.next = 4
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wbm_inst.init_read(256*(16*offset+length)+offset, length)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_16.v b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_16.v
new file mode 100644
index 0000000..9267962
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_16.v
@@ -0,0 +1,136 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_adapter
+ */
+module test_wb_adapter_32_16;
+
+// Parameters
+parameter ADDR_WIDTH = 32;
+parameter WBM_DATA_WIDTH = 32;
+parameter WBM_SELECT_WIDTH = 4;
+parameter WBS_DATA_WIDTH = 16;
+parameter WBS_SELECT_WIDTH = 2;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
+reg [WBM_DATA_WIDTH-1:0] wbm_dat_i = 0;
+reg wbm_we_i = 0;
+reg [WBM_SELECT_WIDTH-1:0] wbm_sel_i = 0;
+reg wbm_stb_i = 0;
+reg wbm_cyc_i = 0;
+reg [WBS_DATA_WIDTH-1:0] wbs_dat_i = 0;
+reg wbs_ack_i = 0;
+reg wbs_err_i = 0;
+reg wbs_rty_i = 0;
+
+// Outputs
+wire [WBM_DATA_WIDTH-1:0] wbm_dat_o;
+wire wbm_ack_o;
+wire wbm_err_o;
+wire wbm_rty_o;
+wire [ADDR_WIDTH-1:0] wbs_adr_o;
+wire [WBS_DATA_WIDTH-1:0] wbs_dat_o;
+wire wbs_we_o;
+wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o;
+wire wbs_stb_o;
+wire wbs_cyc_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ wbm_adr_i,
+ wbm_dat_i,
+ wbm_we_i,
+ wbm_sel_i,
+ wbm_stb_i,
+ wbm_cyc_i,
+ wbs_dat_i,
+ wbs_ack_i,
+ wbs_err_i,
+ wbs_rty_i
+ );
+ $to_myhdl(
+ wbm_dat_o,
+ wbm_ack_o,
+ wbm_err_o,
+ wbm_rty_o,
+ wbs_adr_o,
+ wbs_dat_o,
+ wbs_we_o,
+ wbs_sel_o,
+ wbs_stb_o,
+ wbs_cyc_o
+ );
+
+ // dump file
+ $dumpfile("test_wb_adapter_32_16.lxt");
+ $dumpvars(0, test_wb_adapter_32_16);
+end
+
+wb_adapter #(
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .WBM_DATA_WIDTH(WBM_DATA_WIDTH),
+ .WBM_SELECT_WIDTH(WBM_SELECT_WIDTH),
+ .WBS_DATA_WIDTH(WBS_DATA_WIDTH),
+ .WBS_SELECT_WIDTH(WBS_SELECT_WIDTH)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .wbm_adr_i(wbm_adr_i),
+ .wbm_dat_i(wbm_dat_i),
+ .wbm_dat_o(wbm_dat_o),
+ .wbm_we_i(wbm_we_i),
+ .wbm_sel_i(wbm_sel_i),
+ .wbm_stb_i(wbm_stb_i),
+ .wbm_ack_o(wbm_ack_o),
+ .wbm_err_o(wbm_err_o),
+ .wbm_rty_o(wbm_rty_o),
+ .wbm_cyc_i(wbm_cyc_i),
+ .wbs_adr_o(wbs_adr_o),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_dat_o(wbs_dat_o),
+ .wbs_we_o(wbs_we_o),
+ .wbs_sel_o(wbs_sel_o),
+ .wbs_stb_o(wbs_stb_o),
+ .wbs_ack_i(wbs_ack_i),
+ .wbs_err_i(wbs_err_i),
+ .wbs_rty_i(wbs_rty_i),
+ .wbs_cyc_o(wbs_cyc_o)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_8.py b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_8.py
new file mode 100755
index 0000000..c03b030
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_8.py
@@ -0,0 +1,242 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_adapter'
+testbench = 'test_%s_32_8' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ ADDR_WIDTH = 32
+ WBM_DATA_WIDTH = 32
+ WBM_SELECT_WIDTH = 4
+ WBS_DATA_WIDTH = 8
+ WBS_SELECT_WIDTH = 1
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ wbm_dat_i = Signal(intbv(0)[WBM_DATA_WIDTH:])
+ wbm_we_i = Signal(bool(0))
+ wbm_sel_i = Signal(intbv(0)[WBM_SELECT_WIDTH:])
+ wbm_stb_i = Signal(bool(0))
+ wbm_cyc_i = Signal(bool(0))
+ wbs_dat_i = Signal(intbv(0)[WBS_DATA_WIDTH:])
+ wbs_ack_i = Signal(bool(0))
+ wbs_err_i = Signal(bool(0))
+ wbs_rty_i = Signal(bool(0))
+
+ # Outputs
+ wbm_dat_o = Signal(intbv(0)[WBM_DATA_WIDTH:])
+ wbm_ack_o = Signal(bool(0))
+ wbm_err_o = Signal(bool(0))
+ wbm_rty_o = Signal(bool(0))
+ wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs_dat_o = Signal(intbv(0)[WBS_DATA_WIDTH:])
+ wbs_we_o = Signal(bool(0))
+ wbs_sel_o = Signal(intbv(0)[WBS_SELECT_WIDTH:])
+ wbs_stb_o = Signal(bool(0))
+ wbs_cyc_o = Signal(bool(0))
+
+ # WB master
+ wbm_inst = wb.WBMaster()
+
+ wbm_logic = wbm_inst.create_logic(
+ clk,
+ adr_o=wbm_adr_i,
+ dat_i=wbm_dat_o,
+ dat_o=wbm_dat_i,
+ we_o=wbm_we_i,
+ sel_o=wbm_sel_i,
+ stb_o=wbm_stb_i,
+ ack_i=wbm_ack_o,
+ cyc_o=wbm_cyc_i,
+ name='master'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=wbs_adr_o,
+ dat_i=wbs_dat_o,
+ dat_o=wbs_dat_i,
+ we_i=wbs_we_o,
+ sel_i=wbs_sel_o,
+ stb_i=wbs_stb_o,
+ ack_o=wbs_ack_i,
+ cyc_i=wbs_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='slave'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+ wbm_adr_i=wbm_adr_i,
+ wbm_dat_i=wbm_dat_i,
+ wbm_dat_o=wbm_dat_o,
+ wbm_we_i=wbm_we_i,
+ wbm_sel_i=wbm_sel_i,
+ wbm_stb_i=wbm_stb_i,
+ wbm_ack_o=wbm_ack_o,
+ wbm_err_o=wbm_err_o,
+ wbm_rty_o=wbm_rty_o,
+ wbm_cyc_i=wbm_cyc_i,
+ wbs_adr_o=wbs_adr_o,
+ wbs_dat_i=wbs_dat_i,
+ wbs_dat_o=wbs_dat_o,
+ wbs_we_o=wbs_we_o,
+ wbs_sel_o=wbs_sel_o,
+ wbs_stb_o=wbs_stb_o,
+ wbs_ack_i=wbs_ack_i,
+ wbs_err_i=wbs_err_i,
+ wbs_rty_i=wbs_rty_i,
+ wbs_cyc_o=wbs_cyc_o
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+ print("test 1: write")
+ current_test.next = 1
+
+ wbm_inst.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: read")
+ current_test.next = 2
+
+ wbm_inst.init_read(4, 4)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: various writes")
+ current_test.next = 3
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*16)
+ wbm_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: various reads")
+ current_test.next = 4
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wbm_inst.init_read(256*(16*offset+length)+offset, length)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_8.v b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_8.v
new file mode 100644
index 0000000..f4b1960
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_32_8.v
@@ -0,0 +1,136 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_adapter
+ */
+module test_wb_adapter_32_8;
+
+// Parameters
+parameter ADDR_WIDTH = 32;
+parameter WBM_DATA_WIDTH = 32;
+parameter WBM_SELECT_WIDTH = 4;
+parameter WBS_DATA_WIDTH = 8;
+parameter WBS_SELECT_WIDTH = 1;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
+reg [WBM_DATA_WIDTH-1:0] wbm_dat_i = 0;
+reg wbm_we_i = 0;
+reg [WBM_SELECT_WIDTH-1:0] wbm_sel_i = 0;
+reg wbm_stb_i = 0;
+reg wbm_cyc_i = 0;
+reg [WBS_DATA_WIDTH-1:0] wbs_dat_i = 0;
+reg wbs_ack_i = 0;
+reg wbs_err_i = 0;
+reg wbs_rty_i = 0;
+
+// Outputs
+wire [WBM_DATA_WIDTH-1:0] wbm_dat_o;
+wire wbm_ack_o;
+wire wbm_err_o;
+wire wbm_rty_o;
+wire [ADDR_WIDTH-1:0] wbs_adr_o;
+wire [WBS_DATA_WIDTH-1:0] wbs_dat_o;
+wire wbs_we_o;
+wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o;
+wire wbs_stb_o;
+wire wbs_cyc_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ wbm_adr_i,
+ wbm_dat_i,
+ wbm_we_i,
+ wbm_sel_i,
+ wbm_stb_i,
+ wbm_cyc_i,
+ wbs_dat_i,
+ wbs_ack_i,
+ wbs_err_i,
+ wbs_rty_i
+ );
+ $to_myhdl(
+ wbm_dat_o,
+ wbm_ack_o,
+ wbm_err_o,
+ wbm_rty_o,
+ wbs_adr_o,
+ wbs_dat_o,
+ wbs_we_o,
+ wbs_sel_o,
+ wbs_stb_o,
+ wbs_cyc_o
+ );
+
+ // dump file
+ $dumpfile("test_wb_adapter_32_8.lxt");
+ $dumpvars(0, test_wb_adapter_32_8);
+end
+
+wb_adapter #(
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .WBM_DATA_WIDTH(WBM_DATA_WIDTH),
+ .WBM_SELECT_WIDTH(WBM_SELECT_WIDTH),
+ .WBS_DATA_WIDTH(WBS_DATA_WIDTH),
+ .WBS_SELECT_WIDTH(WBS_SELECT_WIDTH)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .wbm_adr_i(wbm_adr_i),
+ .wbm_dat_i(wbm_dat_i),
+ .wbm_dat_o(wbm_dat_o),
+ .wbm_we_i(wbm_we_i),
+ .wbm_sel_i(wbm_sel_i),
+ .wbm_stb_i(wbm_stb_i),
+ .wbm_ack_o(wbm_ack_o),
+ .wbm_err_o(wbm_err_o),
+ .wbm_rty_o(wbm_rty_o),
+ .wbm_cyc_i(wbm_cyc_i),
+ .wbs_adr_o(wbs_adr_o),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_dat_o(wbs_dat_o),
+ .wbs_we_o(wbs_we_o),
+ .wbs_sel_o(wbs_sel_o),
+ .wbs_stb_o(wbs_stb_o),
+ .wbs_ack_i(wbs_ack_i),
+ .wbs_err_i(wbs_err_i),
+ .wbs_rty_i(wbs_rty_i),
+ .wbs_cyc_o(wbs_cyc_o)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_adapter_8_32.py b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_8_32.py
new file mode 100755
index 0000000..8b5c026
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_8_32.py
@@ -0,0 +1,242 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_adapter'
+testbench = 'test_%s_8_32' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ ADDR_WIDTH = 32
+ WBM_DATA_WIDTH = 8
+ WBM_SELECT_WIDTH = 1
+ WBS_DATA_WIDTH = 32
+ WBS_SELECT_WIDTH = 4
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ wbm_dat_i = Signal(intbv(0)[WBM_DATA_WIDTH:])
+ wbm_we_i = Signal(bool(0))
+ wbm_sel_i = Signal(intbv(0)[WBM_SELECT_WIDTH:])
+ wbm_stb_i = Signal(bool(0))
+ wbm_cyc_i = Signal(bool(0))
+ wbs_dat_i = Signal(intbv(0)[WBS_DATA_WIDTH:])
+ wbs_ack_i = Signal(bool(0))
+ wbs_err_i = Signal(bool(0))
+ wbs_rty_i = Signal(bool(0))
+
+ # Outputs
+ wbm_dat_o = Signal(intbv(0)[WBM_DATA_WIDTH:])
+ wbm_ack_o = Signal(bool(0))
+ wbm_err_o = Signal(bool(0))
+ wbm_rty_o = Signal(bool(0))
+ wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs_dat_o = Signal(intbv(0)[WBS_DATA_WIDTH:])
+ wbs_we_o = Signal(bool(0))
+ wbs_sel_o = Signal(intbv(0)[WBS_SELECT_WIDTH:])
+ wbs_stb_o = Signal(bool(0))
+ wbs_cyc_o = Signal(bool(0))
+
+ # WB master
+ wbm_inst = wb.WBMaster()
+
+ wbm_logic = wbm_inst.create_logic(
+ clk,
+ adr_o=wbm_adr_i,
+ dat_i=wbm_dat_o,
+ dat_o=wbm_dat_i,
+ we_o=wbm_we_i,
+ sel_o=wbm_sel_i,
+ stb_o=wbm_stb_i,
+ ack_i=wbm_ack_o,
+ cyc_o=wbm_cyc_i,
+ name='master'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=wbs_adr_o,
+ dat_i=wbs_dat_o,
+ dat_o=wbs_dat_i,
+ we_i=wbs_we_o,
+ sel_i=wbs_sel_o,
+ stb_i=wbs_stb_o,
+ ack_o=wbs_ack_i,
+ cyc_i=wbs_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='slave'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+ wbm_adr_i=wbm_adr_i,
+ wbm_dat_i=wbm_dat_i,
+ wbm_dat_o=wbm_dat_o,
+ wbm_we_i=wbm_we_i,
+ wbm_sel_i=wbm_sel_i,
+ wbm_stb_i=wbm_stb_i,
+ wbm_ack_o=wbm_ack_o,
+ wbm_err_o=wbm_err_o,
+ wbm_rty_o=wbm_rty_o,
+ wbm_cyc_i=wbm_cyc_i,
+ wbs_adr_o=wbs_adr_o,
+ wbs_dat_i=wbs_dat_i,
+ wbs_dat_o=wbs_dat_o,
+ wbs_we_o=wbs_we_o,
+ wbs_sel_o=wbs_sel_o,
+ wbs_stb_o=wbs_stb_o,
+ wbs_ack_i=wbs_ack_i,
+ wbs_err_i=wbs_err_i,
+ wbs_rty_i=wbs_rty_i,
+ wbs_cyc_o=wbs_cyc_o
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+ print("test 1: write")
+ current_test.next = 1
+
+ wbm_inst.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: read")
+ current_test.next = 2
+
+ wbm_inst.init_read(4, 4)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: various writes")
+ current_test.next = 3
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*16)
+ wbm_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: various reads")
+ current_test.next = 4
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wbm_inst.init_read(256*(16*offset+length)+offset, length)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_adapter_8_32.v b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_8_32.v
new file mode 100644
index 0000000..6f5a627
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_adapter_8_32.v
@@ -0,0 +1,136 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_adapter
+ */
+module test_wb_adapter_8_32;
+
+// Parameters
+parameter ADDR_WIDTH = 32;
+parameter WBM_DATA_WIDTH = 8;
+parameter WBM_SELECT_WIDTH = 1;
+parameter WBS_DATA_WIDTH = 32;
+parameter WBS_SELECT_WIDTH = 4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
+reg [WBM_DATA_WIDTH-1:0] wbm_dat_i = 0;
+reg wbm_we_i = 0;
+reg [WBM_SELECT_WIDTH-1:0] wbm_sel_i = 0;
+reg wbm_stb_i = 0;
+reg wbm_cyc_i = 0;
+reg [WBS_DATA_WIDTH-1:0] wbs_dat_i = 0;
+reg wbs_ack_i = 0;
+reg wbs_err_i = 0;
+reg wbs_rty_i = 0;
+
+// Outputs
+wire [WBM_DATA_WIDTH-1:0] wbm_dat_o;
+wire wbm_ack_o;
+wire wbm_err_o;
+wire wbm_rty_o;
+wire [ADDR_WIDTH-1:0] wbs_adr_o;
+wire [WBS_DATA_WIDTH-1:0] wbs_dat_o;
+wire wbs_we_o;
+wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o;
+wire wbs_stb_o;
+wire wbs_cyc_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ wbm_adr_i,
+ wbm_dat_i,
+ wbm_we_i,
+ wbm_sel_i,
+ wbm_stb_i,
+ wbm_cyc_i,
+ wbs_dat_i,
+ wbs_ack_i,
+ wbs_err_i,
+ wbs_rty_i
+ );
+ $to_myhdl(
+ wbm_dat_o,
+ wbm_ack_o,
+ wbm_err_o,
+ wbm_rty_o,
+ wbs_adr_o,
+ wbs_dat_o,
+ wbs_we_o,
+ wbs_sel_o,
+ wbs_stb_o,
+ wbs_cyc_o
+ );
+
+ // dump file
+ $dumpfile("test_wb_adapter_8_32.lxt");
+ $dumpvars(0, test_wb_adapter_8_32);
+end
+
+wb_adapter #(
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .WBM_DATA_WIDTH(WBM_DATA_WIDTH),
+ .WBM_SELECT_WIDTH(WBM_SELECT_WIDTH),
+ .WBS_DATA_WIDTH(WBS_DATA_WIDTH),
+ .WBS_SELECT_WIDTH(WBS_SELECT_WIDTH)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .wbm_adr_i(wbm_adr_i),
+ .wbm_dat_i(wbm_dat_i),
+ .wbm_dat_o(wbm_dat_o),
+ .wbm_we_i(wbm_we_i),
+ .wbm_sel_i(wbm_sel_i),
+ .wbm_stb_i(wbm_stb_i),
+ .wbm_ack_o(wbm_ack_o),
+ .wbm_err_o(wbm_err_o),
+ .wbm_rty_o(wbm_rty_o),
+ .wbm_cyc_i(wbm_cyc_i),
+ .wbs_adr_o(wbs_adr_o),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_dat_o(wbs_dat_o),
+ .wbs_we_o(wbs_we_o),
+ .wbs_sel_o(wbs_sel_o),
+ .wbs_stb_o(wbs_stb_o),
+ .wbs_ack_i(wbs_ack_i),
+ .wbs_err_i(wbs_err_i),
+ .wbs_rty_i(wbs_rty_i),
+ .wbs_cyc_o(wbs_cyc_o)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_arbiter_2.py b/ip/third_party/verilog-wishbone/tb/test_wb_arbiter_2.py
new file mode 100755
index 0000000..f4b5448
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_arbiter_2.py
@@ -0,0 +1,315 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_arbiter_2'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../rtl/arbiter.v")
+srcs.append("../rtl/priority_encoder.v")
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ DATA_WIDTH = 32
+ ADDR_WIDTH = 32
+ SELECT_WIDTH = (DATA_WIDTH/8)
+ ARB_TYPE = "PRIORITY"
+ LSB_PRIORITY = "HIGH"
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ wbm0_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ wbm0_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbm0_we_i = Signal(bool(0))
+ wbm0_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
+ wbm0_stb_i = Signal(bool(0))
+ wbm0_cyc_i = Signal(bool(0))
+ wbm1_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ wbm1_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbm1_we_i = Signal(bool(0))
+ wbm1_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
+ wbm1_stb_i = Signal(bool(0))
+ wbm1_cyc_i = Signal(bool(0))
+ wbs_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbs_ack_i = Signal(bool(0))
+ wbs_err_i = Signal(bool(0))
+ wbs_rty_i = Signal(bool(0))
+
+ # Outputs
+ wbm0_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbm0_ack_o = Signal(bool(0))
+ wbm0_err_o = Signal(bool(0))
+ wbm0_rty_o = Signal(bool(0))
+ wbm1_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbm1_ack_o = Signal(bool(0))
+ wbm1_err_o = Signal(bool(0))
+ wbm1_rty_o = Signal(bool(0))
+ wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbs_we_o = Signal(bool(0))
+ wbs_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
+ wbs_stb_o = Signal(bool(0))
+ wbs_cyc_o = Signal(bool(0))
+
+ # WB master
+ wbm0_inst = wb.WBMaster()
+
+ wbm0_logic = wbm0_inst.create_logic(
+ clk,
+ adr_o=wbm0_adr_i,
+ dat_i=wbm0_dat_o,
+ dat_o=wbm0_dat_i,
+ we_o=wbm0_we_i,
+ sel_o=wbm0_sel_i,
+ stb_o=wbm0_stb_i,
+ ack_i=wbm0_ack_o,
+ cyc_o=wbm0_cyc_i,
+ name='master0'
+ )
+
+ # WB master
+ wbm1_inst = wb.WBMaster()
+
+ wbm1_logic = wbm1_inst.create_logic(
+ clk,
+ adr_o=wbm1_adr_i,
+ dat_i=wbm1_dat_o,
+ dat_o=wbm1_dat_i,
+ we_o=wbm1_we_i,
+ sel_o=wbm1_sel_i,
+ stb_o=wbm1_stb_i,
+ ack_i=wbm1_ack_o,
+ cyc_o=wbm1_cyc_i,
+ name='master1'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=wbs_adr_o,
+ dat_i=wbs_dat_o,
+ dat_o=wbs_dat_i,
+ we_i=wbs_we_o,
+ sel_i=wbs_sel_o,
+ stb_i=wbs_stb_o,
+ ack_o=wbs_ack_i,
+ cyc_i=wbs_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='slave'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+
+ wbm0_adr_i=wbm0_adr_i,
+ wbm0_dat_i=wbm0_dat_i,
+ wbm0_dat_o=wbm0_dat_o,
+ wbm0_we_i=wbm0_we_i,
+ wbm0_sel_i=wbm0_sel_i,
+ wbm0_stb_i=wbm0_stb_i,
+ wbm0_ack_o=wbm0_ack_o,
+ wbm0_err_o=wbm0_err_o,
+ wbm0_rty_o=wbm0_rty_o,
+ wbm0_cyc_i=wbm0_cyc_i,
+
+ wbm1_adr_i=wbm1_adr_i,
+ wbm1_dat_i=wbm1_dat_i,
+ wbm1_dat_o=wbm1_dat_o,
+ wbm1_we_i=wbm1_we_i,
+ wbm1_sel_i=wbm1_sel_i,
+ wbm1_stb_i=wbm1_stb_i,
+ wbm1_ack_o=wbm1_ack_o,
+ wbm1_err_o=wbm1_err_o,
+ wbm1_rty_o=wbm1_rty_o,
+ wbm1_cyc_i=wbm1_cyc_i,
+
+ wbs_adr_o=wbs_adr_o,
+ wbs_dat_i=wbs_dat_i,
+ wbs_dat_o=wbs_dat_o,
+ wbs_we_o=wbs_we_o,
+ wbs_sel_o=wbs_sel_o,
+ wbs_stb_o=wbs_stb_o,
+ wbs_ack_i=wbs_ack_i,
+ wbs_err_i=wbs_err_i,
+ wbs_rty_i=wbs_rty_i,
+ wbs_cyc_o=wbs_cyc_o
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ # testbench stimulus
+
+ yield clk.posedge
+ print("test 1: master 0")
+ current_test.next = 1
+
+ wbm0_inst.init_write(0x00000000, b'\x11\x22\x33\x44')
+
+ yield wbm0_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0x00000000, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(0,4) == b'\x11\x22\x33\x44'
+
+ wbm0_inst.init_read(0x00000000, 4)
+
+ yield wbm0_inst.wait()
+ yield clk.posedge
+
+ data = wbm0_inst.get_read_data()
+ assert data[0] == 0x00000000
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: master 1")
+ current_test.next = 2
+
+ wbm1_inst.init_write(0x00001000, b'\x11\x22\x33\x44')
+
+ yield wbm1_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0x00001000, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(0,4) == b'\x11\x22\x33\x44'
+
+ wbm1_inst.init_read(0x00001000, 4)
+
+ yield wbm0_inst.wait()
+ yield wbm1_inst.wait()
+ yield clk.posedge
+
+ data = wbm1_inst.get_read_data()
+ assert data[0] == 0x00001000
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: arbitration")
+ current_test.next = 3
+
+ wbm0_inst.init_write(0x00000010, bytearray(range(16)))
+ wbm0_inst.init_write(0x00000020, bytearray(range(16)))
+ wbm1_inst.init_write(0x00001010, bytearray(range(16)))
+ wbm1_inst.init_write(0x00001020, bytearray(range(16)))
+
+ yield wbm1_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0x00000010, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ data = wb_ram_inst.read_mem(0x00001010, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(0,4) == b'\x11\x22\x33\x44'
+
+ wbm0_inst.init_read(0x00000010, 16)
+ wbm0_inst.init_read(0x00000020, 16)
+ wbm1_inst.init_read(0x00001010, 16)
+ wbm1_inst.init_read(0x00001020, 16)
+
+ yield wbm0_inst.wait()
+ yield wbm1_inst.wait()
+ yield clk.posedge
+
+ data = wbm0_inst.get_read_data()
+ assert data[0] == 0x00000010
+ assert data[1] == bytearray(range(16))
+
+ data = wbm0_inst.get_read_data()
+ assert data[0] == 0x00000020
+ assert data[1] == bytearray(range(16))
+
+ data = wbm1_inst.get_read_data()
+ assert data[0] == 0x00001010
+ assert data[1] == bytearray(range(16))
+
+ data = wbm1_inst.get_read_data()
+ assert data[0] == 0x00001020
+ assert data[1] == bytearray(range(16))
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_arbiter_2.v b/ip/third_party/verilog-wishbone/tb/test_wb_arbiter_2.v
new file mode 100644
index 0000000..10c291b
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_arbiter_2.v
@@ -0,0 +1,166 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_arbiter_2
+ */
+module test_wb_arbiter_2;
+
+// Parameters
+parameter DATA_WIDTH = 32;
+parameter ADDR_WIDTH = 32;
+parameter SELECT_WIDTH = (DATA_WIDTH/8);
+parameter ARB_TYPE = "PRIORITY";
+parameter LSB_PRIORITY = "HIGH";
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] wbm0_adr_i = 0;
+reg [DATA_WIDTH-1:0] wbm0_dat_i = 0;
+reg wbm0_we_i = 0;
+reg [SELECT_WIDTH-1:0] wbm0_sel_i = 0;
+reg wbm0_stb_i = 0;
+reg wbm0_cyc_i = 0;
+reg [ADDR_WIDTH-1:0] wbm1_adr_i = 0;
+reg [DATA_WIDTH-1:0] wbm1_dat_i = 0;
+reg wbm1_we_i = 0;
+reg [SELECT_WIDTH-1:0] wbm1_sel_i = 0;
+reg wbm1_stb_i = 0;
+reg wbm1_cyc_i = 0;
+reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
+reg wbs_ack_i = 0;
+reg wbs_err_i = 0;
+reg wbs_rty_i = 0;
+
+// Outputs
+wire [DATA_WIDTH-1:0] wbm0_dat_o;
+wire wbm0_ack_o;
+wire wbm0_err_o;
+wire wbm0_rty_o;
+wire [DATA_WIDTH-1:0] wbm1_dat_o;
+wire wbm1_ack_o;
+wire wbm1_err_o;
+wire wbm1_rty_o;
+wire [ADDR_WIDTH-1:0] wbs_adr_o;
+wire [DATA_WIDTH-1:0] wbs_dat_o;
+wire wbs_we_o;
+wire [SELECT_WIDTH-1:0] wbs_sel_o;
+wire wbs_stb_o;
+wire wbs_cyc_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ wbm0_adr_i,
+ wbm0_dat_i,
+ wbm0_we_i,
+ wbm0_sel_i,
+ wbm0_stb_i,
+ wbm0_cyc_i,
+ wbm1_adr_i,
+ wbm1_dat_i,
+ wbm1_we_i,
+ wbm1_sel_i,
+ wbm1_stb_i,
+ wbm1_cyc_i,
+ wbs_dat_i,
+ wbs_ack_i,
+ wbs_err_i,
+ wbs_rty_i
+ );
+ $to_myhdl(
+ wbm0_dat_o,
+ wbm0_ack_o,
+ wbm0_err_o,
+ wbm0_rty_o,
+ wbm1_dat_o,
+ wbm1_ack_o,
+ wbm1_err_o,
+ wbm1_rty_o,
+ wbs_adr_o,
+ wbs_dat_o,
+ wbs_we_o,
+ wbs_sel_o,
+ wbs_stb_o,
+ wbs_cyc_o
+ );
+
+ // dump file
+ $dumpfile("test_wb_arbiter_2.lxt");
+ $dumpvars(0, test_wb_arbiter_2);
+end
+
+wb_arbiter_2 #(
+ .DATA_WIDTH(DATA_WIDTH),
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .SELECT_WIDTH(SELECT_WIDTH),
+ .ARB_TYPE(ARB_TYPE),
+ .LSB_PRIORITY(LSB_PRIORITY)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .wbm0_adr_i(wbm0_adr_i),
+ .wbm0_dat_i(wbm0_dat_i),
+ .wbm0_dat_o(wbm0_dat_o),
+ .wbm0_we_i(wbm0_we_i),
+ .wbm0_sel_i(wbm0_sel_i),
+ .wbm0_stb_i(wbm0_stb_i),
+ .wbm0_ack_o(wbm0_ack_o),
+ .wbm0_err_o(wbm0_err_o),
+ .wbm0_rty_o(wbm0_rty_o),
+ .wbm0_cyc_i(wbm0_cyc_i),
+ .wbm1_adr_i(wbm1_adr_i),
+ .wbm1_dat_i(wbm1_dat_i),
+ .wbm1_dat_o(wbm1_dat_o),
+ .wbm1_we_i(wbm1_we_i),
+ .wbm1_sel_i(wbm1_sel_i),
+ .wbm1_stb_i(wbm1_stb_i),
+ .wbm1_ack_o(wbm1_ack_o),
+ .wbm1_err_o(wbm1_err_o),
+ .wbm1_rty_o(wbm1_rty_o),
+ .wbm1_cyc_i(wbm1_cyc_i),
+ .wbs_adr_o(wbs_adr_o),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_dat_o(wbs_dat_o),
+ .wbs_we_o(wbs_we_o),
+ .wbs_sel_o(wbs_sel_o),
+ .wbs_stb_o(wbs_stb_o),
+ .wbs_ack_i(wbs_ack_i),
+ .wbs_err_i(wbs_err_i),
+ .wbs_rty_i(wbs_rty_i),
+ .wbs_cyc_o(wbs_cyc_o)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_async_reg.py b/ip/third_party/verilog-wishbone/tb/test_wb_async_reg.py
new file mode 100755
index 0000000..0148b84
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_async_reg.py
@@ -0,0 +1,251 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_async_reg'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ DATA_WIDTH = 32
+ ADDR_WIDTH = 32
+ SELECT_WIDTH = 4
+
+ # Inputs
+ wbm_clk = Signal(bool(0))
+ wbm_rst = Signal(bool(0))
+ wbs_clk = Signal(bool(0))
+ wbs_rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ wbm_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbm_we_i = Signal(bool(0))
+ wbm_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
+ wbm_stb_i = Signal(bool(0))
+ wbm_cyc_i = Signal(bool(0))
+ wbs_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbs_ack_i = Signal(bool(0))
+ wbs_err_i = Signal(bool(0))
+ wbs_rty_i = Signal(bool(0))
+
+ # Outputs
+ wbm_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbm_ack_o = Signal(bool(0))
+ wbm_err_o = Signal(bool(0))
+ wbm_rty_o = Signal(bool(0))
+ wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbs_we_o = Signal(bool(0))
+ wbs_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
+ wbs_stb_o = Signal(bool(0))
+ wbs_cyc_o = Signal(bool(0))
+
+ # WB master
+ wbm_inst = wb.WBMaster()
+
+ wbm_logic = wbm_inst.create_logic(
+ wbm_clk,
+ adr_o=wbm_adr_i,
+ dat_i=wbm_dat_o,
+ dat_o=wbm_dat_i,
+ we_o=wbm_we_i,
+ sel_o=wbm_sel_i,
+ stb_o=wbm_stb_i,
+ ack_i=wbm_ack_o,
+ cyc_o=wbm_cyc_i,
+ name='master'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ wbs_clk,
+ adr_i=wbs_adr_o,
+ dat_i=wbs_dat_o,
+ dat_o=wbs_dat_i,
+ we_i=wbs_we_o,
+ sel_i=wbs_sel_o,
+ stb_i=wbs_stb_o,
+ ack_o=wbs_ack_i,
+ cyc_i=wbs_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='slave'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ wbm_clk=wbm_clk,
+ wbm_rst=wbm_rst,
+ wbs_clk=wbs_clk,
+ wbs_rst=wbs_rst,
+ current_test=current_test,
+ wbm_adr_i=wbm_adr_i,
+ wbm_dat_i=wbm_dat_i,
+ wbm_dat_o=wbm_dat_o,
+ wbm_we_i=wbm_we_i,
+ wbm_sel_i=wbm_sel_i,
+ wbm_stb_i=wbm_stb_i,
+ wbm_ack_o=wbm_ack_o,
+ wbm_err_o=wbm_err_o,
+ wbm_rty_o=wbm_rty_o,
+ wbm_cyc_i=wbm_cyc_i,
+ wbs_adr_o=wbs_adr_o,
+ wbs_dat_i=wbs_dat_i,
+ wbs_dat_o=wbs_dat_o,
+ wbs_we_o=wbs_we_o,
+ wbs_sel_o=wbs_sel_o,
+ wbs_stb_o=wbs_stb_o,
+ wbs_ack_i=wbs_ack_i,
+ wbs_err_i=wbs_err_i,
+ wbs_rty_i=wbs_rty_i,
+ wbs_cyc_o=wbs_cyc_o
+ )
+
+ @always(delay(4))
+ def wbm_clkgen():
+ wbm_clk.next = not wbm_clk
+
+ @always(delay(5))
+ def wbs_clkgen():
+ wbs_clk.next = not wbs_clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield wbm_clk.posedge
+ wbm_rst.next = 1
+ wbs_rst.next = 1
+ yield wbm_clk.posedge
+ yield wbm_clk.posedge
+ yield wbm_clk.posedge
+ wbm_rst.next = 0
+ wbs_rst.next = 0
+ yield wbm_clk.posedge
+ yield delay(100)
+ yield wbm_clk.posedge
+
+ yield wbm_clk.posedge
+ print("test 1: write")
+ current_test.next = 1
+
+ wbm_inst.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wbm_inst.wait()
+ yield wbm_clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield wbm_clk.posedge
+ print("test 2: read")
+ current_test.next = 2
+
+ wbm_inst.init_read(4, 4)
+
+ yield wbm_inst.wait()
+ yield wbm_clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield wbm_clk.posedge
+ print("test 3: various writes")
+ current_test.next = 3
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*32)
+ wbm_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wbm_inst.wait()
+ yield wbm_clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
+
+ yield delay(100)
+
+ yield wbm_clk.posedge
+ print("test 4: various reads")
+ current_test.next = 4
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wbm_inst.init_read(256*(16*offset+length)+offset, length)
+
+ yield wbm_inst.wait()
+ yield wbm_clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_async_reg.v b/ip/third_party/verilog-wishbone/tb/test_wb_async_reg.v
new file mode 100644
index 0000000..461ef24
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_async_reg.v
@@ -0,0 +1,138 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_async_reg
+ */
+module test_wb_async_reg;
+
+// Parameters
+parameter DATA_WIDTH = 32;
+parameter ADDR_WIDTH = 32;
+parameter SELECT_WIDTH = 4;
+
+// Inputs
+reg wbm_clk = 0;
+reg wbm_rst = 0;
+reg wbs_clk = 0;
+reg wbs_rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
+reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
+reg wbm_we_i = 0;
+reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
+reg wbm_stb_i = 0;
+reg wbm_cyc_i = 0;
+reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
+reg wbs_ack_i = 0;
+reg wbs_err_i = 0;
+reg wbs_rty_i = 0;
+
+// Outputs
+wire [DATA_WIDTH-1:0] wbm_dat_o;
+wire wbm_ack_o;
+wire wbm_err_o;
+wire wbm_rty_o;
+wire [ADDR_WIDTH-1:0] wbs_adr_o;
+wire [DATA_WIDTH-1:0] wbs_dat_o;
+wire wbs_we_o;
+wire [SELECT_WIDTH-1:0] wbs_sel_o;
+wire wbs_stb_o;
+wire wbs_cyc_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ wbm_clk,
+ wbm_rst,
+ wbs_clk,
+ wbs_rst,
+ current_test,
+ wbm_adr_i,
+ wbm_dat_i,
+ wbm_we_i,
+ wbm_sel_i,
+ wbm_stb_i,
+ wbm_cyc_i,
+ wbs_dat_i,
+ wbs_ack_i,
+ wbs_err_i,
+ wbs_rty_i
+ );
+ $to_myhdl(
+ wbm_dat_o,
+ wbm_ack_o,
+ wbm_err_o,
+ wbm_rty_o,
+ wbs_adr_o,
+ wbs_dat_o,
+ wbs_we_o,
+ wbs_sel_o,
+ wbs_stb_o,
+ wbs_cyc_o
+ );
+
+ // dump file
+ $dumpfile("test_wb_async_reg.lxt");
+ $dumpvars(0, test_wb_async_reg);
+end
+
+wb_async_reg #(
+ .DATA_WIDTH(DATA_WIDTH),
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .SELECT_WIDTH(SELECT_WIDTH)
+)
+UUT (
+ .wbm_clk(wbm_clk),
+ .wbm_rst(wbm_rst),
+ .wbm_adr_i(wbm_adr_i),
+ .wbm_dat_i(wbm_dat_i),
+ .wbm_dat_o(wbm_dat_o),
+ .wbm_we_i(wbm_we_i),
+ .wbm_sel_i(wbm_sel_i),
+ .wbm_stb_i(wbm_stb_i),
+ .wbm_ack_o(wbm_ack_o),
+ .wbm_err_o(wbm_err_o),
+ .wbm_rty_o(wbm_rty_o),
+ .wbm_cyc_i(wbm_cyc_i),
+ .wbs_clk(wbs_clk),
+ .wbs_rst(wbs_rst),
+ .wbs_adr_o(wbs_adr_o),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_dat_o(wbs_dat_o),
+ .wbs_we_o(wbs_we_o),
+ .wbs_sel_o(wbs_sel_o),
+ .wbs_stb_o(wbs_stb_o),
+ .wbs_ack_i(wbs_ack_i),
+ .wbs_err_i(wbs_err_i),
+ .wbs_rty_i(wbs_rty_i),
+ .wbs_cyc_o(wbs_cyc_o)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_dp_ram.py b/ip/third_party/verilog-wishbone/tb/test_wb_dp_ram.py
new file mode 100755
index 0000000..8e24768
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_dp_ram.py
@@ -0,0 +1,285 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_dp_ram'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ DATA_WIDTH = 32
+ ADDR_WIDTH = 32
+ SELECT_WIDTH = 4
+
+ # Inputs
+ a_clk = Signal(bool(0))
+ a_rst = Signal(bool(0))
+ b_clk = Signal(bool(0))
+ b_rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ a_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ a_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ a_we_i = Signal(bool(0))
+ a_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
+ a_stb_i = Signal(bool(0))
+ a_cyc_i = Signal(bool(0))
+ b_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ b_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ b_we_i = Signal(bool(0))
+ b_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
+ b_stb_i = Signal(bool(0))
+ b_cyc_i = Signal(bool(0))
+
+ # Outputs
+ a_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ a_ack_o = Signal(bool(0))
+ b_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ b_ack_o = Signal(bool(0))
+
+ # WB master A
+ wbm_inst_a = wb.WBMaster()
+
+ wbm_logic_a = wbm_inst_a.create_logic(
+ a_clk,
+ adr_o=a_adr_i,
+ dat_i=a_dat_o,
+ dat_o=a_dat_i,
+ we_o=a_we_i,
+ sel_o=a_sel_i,
+ stb_o=a_stb_i,
+ ack_i=a_ack_o,
+ cyc_o=a_cyc_i,
+ name='master_a'
+ )
+
+ # WB master B
+ wbm_inst_b = wb.WBMaster()
+
+ wbm_logic_b = wbm_inst_b.create_logic(
+ b_clk,
+ adr_o=b_adr_i,
+ dat_i=b_dat_o,
+ dat_o=b_dat_i,
+ we_o=b_we_i,
+ sel_o=b_sel_i,
+ stb_o=b_stb_i,
+ ack_i=b_ack_o,
+ cyc_o=b_cyc_i,
+ name='master_'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ a_clk=a_clk,
+ a_rst=a_rst,
+ b_clk=b_clk,
+ b_rst=b_rst,
+ current_test=current_test,
+ a_adr_i=a_adr_i,
+ a_dat_i=a_dat_i,
+ a_dat_o=a_dat_o,
+ a_we_i=a_we_i,
+ a_sel_i=a_sel_i,
+ a_stb_i=a_stb_i,
+ a_ack_o=a_ack_o,
+ a_cyc_i=a_cyc_i,
+ b_adr_i=b_adr_i,
+ b_dat_i=b_dat_i,
+ b_dat_o=b_dat_o,
+ b_we_i=b_we_i,
+ b_sel_i=b_sel_i,
+ b_stb_i=b_stb_i,
+ b_ack_o=b_ack_o,
+ b_cyc_i=b_cyc_i
+ )
+
+ @always(delay(4))
+ def a_clkgen():
+ a_clk.next = not a_clk
+
+ @always(delay(5))
+ def b_clkgen():
+ b_clk.next = not b_clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield a_clk.posedge
+ a_rst.next = 1
+ b_rst.next = 1
+ yield a_clk.posedge
+ yield a_clk.posedge
+ yield a_clk.posedge
+ a_rst.next = 0
+ b_rst.next = 0
+ yield a_clk.posedge
+ yield delay(100)
+ yield a_clk.posedge
+
+ yield a_clk.posedge
+ print("test 1: read and write (port A)")
+ current_test.next = 1
+
+ wbm_inst_a.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wbm_inst_a.wait()
+ yield a_clk.posedge
+
+ wbm_inst_a.init_read(4, 4)
+
+ yield wbm_inst_a.wait()
+ yield a_clk.posedge
+
+ data = wbm_inst_a.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield a_clk.posedge
+ print("test 2: read and write (port B)")
+ current_test.next = 2
+
+ wbm_inst_b.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wbm_inst_b.wait()
+ yield b_clk.posedge
+
+ wbm_inst_b.init_read(4, 4)
+
+ yield wbm_inst_b.wait()
+ yield b_clk.posedge
+
+ data = wbm_inst_b.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield a_clk.posedge
+ print("test 3: various reads and writes (port A)")
+ current_test.next = 3
+
+ for length in range(1,8):
+ for offset in range(4):
+ wbm_inst_a.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wbm_inst_a.wait()
+ yield a_clk.posedge
+
+ for length in range(1,8):
+ for offset in range(4):
+ wbm_inst_a.init_read(256*(16*offset+length)+offset, length)
+
+ yield wbm_inst_a.wait()
+ yield a_clk.posedge
+
+ data = wbm_inst_a.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ yield a_clk.posedge
+ print("test 4: various reads and writes (port B)")
+ current_test.next = 4
+
+ for length in range(1,8):
+ for offset in range(4):
+ wbm_inst_b.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wbm_inst_b.wait()
+ yield b_clk.posedge
+
+ for length in range(1,8):
+ for offset in range(4):
+ wbm_inst_b.init_read(256*(16*offset+length)+offset, length)
+
+ yield wbm_inst_b.wait()
+ yield b_clk.posedge
+
+ data = wbm_inst_b.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ yield a_clk.posedge
+ print("test 5: simultaneous read and write")
+ current_test.next = 5
+
+ wbm_inst_a.init_write(8, b'\xAA\xAA\xAA\xAA')
+ wbm_inst_b.init_write(12, b'\xBB\xBB\xBB\xBB')
+
+ yield wbm_inst_a.wait()
+ yield wbm_inst_b.wait()
+ yield a_clk.posedge
+
+ wbm_inst_a.init_read(12, 4)
+ wbm_inst_b.init_read(8, 4)
+
+ yield wbm_inst_a.wait()
+ yield wbm_inst_b.wait()
+ yield a_clk.posedge
+
+ data = wbm_inst_a.get_read_data()
+ assert data[0] == 12
+ assert data[1] == b'\xBB\xBB\xBB\xBB'
+ data = wbm_inst_b.get_read_data()
+ assert data[0] == 8
+ assert data[1] == b'\xAA\xAA\xAA\xAA'
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_dp_ram.v b/ip/third_party/verilog-wishbone/tb/test_wb_dp_ram.v
new file mode 100644
index 0000000..d6b12b5
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_dp_ram.v
@@ -0,0 +1,124 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_dp_ram
+ */
+module test_wb_dp_ram;
+
+// Parameters
+parameter DATA_WIDTH = 32;
+parameter ADDR_WIDTH = 16;
+parameter SELECT_WIDTH = 4;
+
+// Inputs
+reg a_clk = 0;
+reg a_rst = 0;
+reg b_clk = 0;
+reg b_rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] a_adr_i = 0;
+reg [DATA_WIDTH-1:0] a_dat_i = 0;
+reg a_we_i = 0;
+reg [SELECT_WIDTH-1:0] a_sel_i = 0;
+reg a_stb_i = 0;
+reg a_cyc_i = 0;
+reg [ADDR_WIDTH-1:0] b_adr_i = 0;
+reg [DATA_WIDTH-1:0] b_dat_i = 0;
+reg b_we_i = 0;
+reg [SELECT_WIDTH-1:0] b_sel_i = 0;
+reg b_stb_i = 0;
+reg b_cyc_i = 0;
+
+// Outputs
+wire [DATA_WIDTH-1:0] a_dat_o;
+wire a_ack_o;
+wire [DATA_WIDTH-1:0] b_dat_o;
+wire b_ack_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ a_clk,
+ a_rst,
+ b_clk,
+ b_rst,
+ current_test,
+ a_adr_i,
+ a_dat_i,
+ a_we_i,
+ a_sel_i,
+ a_stb_i,
+ a_cyc_i,
+ b_adr_i,
+ b_dat_i,
+ b_we_i,
+ b_sel_i,
+ b_stb_i,
+ b_cyc_i
+ );
+ $to_myhdl(
+ a_dat_o,
+ a_ack_o,
+ b_dat_o,
+ b_ack_o
+ );
+
+ // dump file
+ $dumpfile("test_wb_dp_ram.lxt");
+ $dumpvars(0, test_wb_dp_ram);
+end
+
+wb_dp_ram #(
+ .DATA_WIDTH(DATA_WIDTH),
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .SELECT_WIDTH(SELECT_WIDTH)
+)
+UUT (
+ .a_clk(a_clk),
+ .a_adr_i(a_adr_i),
+ .a_dat_i(a_dat_i),
+ .a_dat_o(a_dat_o),
+ .a_we_i(a_we_i),
+ .a_sel_i(a_sel_i),
+ .a_stb_i(a_stb_i),
+ .a_ack_o(a_ack_o),
+ .a_cyc_i(a_cyc_i),
+ .b_clk(b_clk),
+ .b_adr_i(b_adr_i),
+ .b_dat_i(b_dat_i),
+ .b_dat_o(b_dat_o),
+ .b_we_i(b_we_i),
+ .b_sel_i(b_sel_i),
+ .b_stb_i(b_stb_i),
+ .b_ack_o(b_ack_o),
+ .b_cyc_i(b_cyc_i)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_mux_2.py b/ip/third_party/verilog-wishbone/tb/test_wb_mux_2.py
new file mode 100755
index 0000000..8891790
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_mux_2.py
@@ -0,0 +1,284 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_mux_2'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ DATA_WIDTH = 32
+ ADDR_WIDTH = 32
+ SELECT_WIDTH = 4
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ wbm_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbm_we_i = Signal(bool(0))
+ wbm_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
+ wbm_stb_i = Signal(bool(0))
+ wbm_cyc_i = Signal(bool(0))
+ wbs0_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbs0_ack_i = Signal(bool(0))
+ wbs0_err_i = Signal(bool(0))
+ wbs0_rty_i = Signal(bool(0))
+ wbs0_addr = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs0_addr_msk = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs1_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbs1_ack_i = Signal(bool(0))
+ wbs1_err_i = Signal(bool(0))
+ wbs1_rty_i = Signal(bool(0))
+ wbs1_addr = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs1_addr_msk = Signal(intbv(0)[ADDR_WIDTH:])
+
+ # Outputs
+ wbm_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbm_ack_o = Signal(bool(0))
+ wbm_err_o = Signal(bool(0))
+ wbm_rty_o = Signal(bool(0))
+ wbs0_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs0_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbs0_we_o = Signal(bool(0))
+ wbs0_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
+ wbs0_stb_o = Signal(bool(0))
+ wbs0_cyc_o = Signal(bool(0))
+ wbs1_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs1_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbs1_we_o = Signal(bool(0))
+ wbs1_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
+ wbs1_stb_o = Signal(bool(0))
+ wbs1_cyc_o = Signal(bool(0))
+
+ # WB master
+ wbm_inst = wb.WBMaster()
+
+ wbm_logic = wbm_inst.create_logic(
+ clk,
+ adr_o=wbm_adr_i,
+ dat_i=wbm_dat_o,
+ dat_o=wbm_dat_i,
+ we_o=wbm_we_i,
+ sel_o=wbm_sel_i,
+ stb_o=wbm_stb_i,
+ ack_i=wbm_ack_o,
+ cyc_o=wbm_cyc_i,
+ name='master'
+ )
+
+ # WB RAM model
+ wb_ram0_inst = wb.WBRam(2**16)
+
+ wb_ram0_port0 = wb_ram0_inst.create_port(
+ clk,
+ adr_i=wbs0_adr_o,
+ dat_i=wbs0_dat_o,
+ dat_o=wbs0_dat_i,
+ we_i=wbs0_we_o,
+ sel_i=wbs0_sel_o,
+ stb_i=wbs0_stb_o,
+ ack_o=wbs0_ack_i,
+ cyc_i=wbs0_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='slave0'
+ )
+
+ # WB RAM model
+ wb_ram1_inst = wb.WBRam(2**16)
+
+ wb_ram1_port0 = wb_ram1_inst.create_port(
+ clk,
+ adr_i=wbs1_adr_o,
+ dat_i=wbs1_dat_o,
+ dat_o=wbs1_dat_i,
+ we_i=wbs1_we_o,
+ sel_i=wbs1_sel_o,
+ stb_i=wbs1_stb_o,
+ ack_o=wbs1_ack_i,
+ cyc_i=wbs1_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='slave1'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+ wbm_adr_i=wbm_adr_i,
+ wbm_dat_i=wbm_dat_i,
+ wbm_dat_o=wbm_dat_o,
+ wbm_we_i=wbm_we_i,
+ wbm_sel_i=wbm_sel_i,
+ wbm_stb_i=wbm_stb_i,
+ wbm_ack_o=wbm_ack_o,
+ wbm_err_o=wbm_err_o,
+ wbm_rty_o=wbm_rty_o,
+ wbm_cyc_i=wbm_cyc_i,
+ wbs0_adr_o=wbs0_adr_o,
+ wbs0_dat_i=wbs0_dat_i,
+ wbs0_dat_o=wbs0_dat_o,
+ wbs0_we_o=wbs0_we_o,
+ wbs0_sel_o=wbs0_sel_o,
+ wbs0_stb_o=wbs0_stb_o,
+ wbs0_ack_i=wbs0_ack_i,
+ wbs0_err_i=wbs0_err_i,
+ wbs0_rty_i=wbs0_rty_i,
+ wbs0_cyc_o=wbs0_cyc_o,
+ wbs0_addr=wbs0_addr,
+ wbs0_addr_msk=wbs0_addr_msk,
+ wbs1_adr_o=wbs1_adr_o,
+ wbs1_dat_i=wbs1_dat_i,
+ wbs1_dat_o=wbs1_dat_o,
+ wbs1_we_o=wbs1_we_o,
+ wbs1_sel_o=wbs1_sel_o,
+ wbs1_stb_o=wbs1_stb_o,
+ wbs1_ack_i=wbs1_ack_i,
+ wbs1_err_i=wbs1_err_i,
+ wbs1_rty_i=wbs1_rty_i,
+ wbs1_cyc_o=wbs1_cyc_o,
+ wbs1_addr=wbs1_addr,
+ wbs1_addr_msk=wbs1_addr_msk
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ wbs0_addr.next = 0x00000000
+ wbs0_addr_msk.next = 0xFFFF0000
+
+ wbs1_addr.next = 0x00010000
+ wbs1_addr_msk.next = 0xFFFF0000
+
+ yield clk.posedge
+ print("test 1: write to slave 0")
+ current_test.next = 1
+
+ wbm_inst.init_write(0x00000004, b'\x11\x22\x33\x44')
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram0_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram0_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: read from slave 0")
+ current_test.next = 2
+
+ wbm_inst.init_read(0x00000004, 4)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 0x00000004
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: write to slave 1")
+ current_test.next = 3
+
+ wbm_inst.init_write(0x00010004, b'\x11\x22\x33\x44')
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram1_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram1_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: read from slave 1")
+ current_test.next = 4
+
+ wbm_inst.init_read(0x00010004, 4)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 0x00010004
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_mux_2.v b/ip/third_party/verilog-wishbone/tb/test_wb_mux_2.v
new file mode 100644
index 0000000..81df242
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_mux_2.v
@@ -0,0 +1,170 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_mux_2
+ */
+module test_wb_mux_2;
+
+// Parameters
+parameter DATA_WIDTH = 32;
+parameter ADDR_WIDTH = 32;
+parameter SELECT_WIDTH = 4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
+reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
+reg wbm_we_i = 0;
+reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
+reg wbm_stb_i = 0;
+reg wbm_cyc_i = 0;
+reg [DATA_WIDTH-1:0] wbs0_dat_i = 0;
+reg wbs0_ack_i = 0;
+reg wbs0_err_i = 0;
+reg wbs0_rty_i = 0;
+reg [ADDR_WIDTH-1:0] wbs0_addr = 0;
+reg [ADDR_WIDTH-1:0] wbs0_addr_msk = 0;
+reg [DATA_WIDTH-1:0] wbs1_dat_i = 0;
+reg wbs1_ack_i = 0;
+reg wbs1_err_i = 0;
+reg wbs1_rty_i = 0;
+reg [ADDR_WIDTH-1:0] wbs1_addr = 0;
+reg [ADDR_WIDTH-1:0] wbs1_addr_msk = 0;
+
+// Outputs
+wire [DATA_WIDTH-1:0] wbm_dat_o;
+wire wbm_ack_o;
+wire wbm_err_o;
+wire wbm_rty_o;
+wire [ADDR_WIDTH-1:0] wbs0_adr_o;
+wire [DATA_WIDTH-1:0] wbs0_dat_o;
+wire wbs0_we_o;
+wire [SELECT_WIDTH-1:0] wbs0_sel_o;
+wire wbs0_stb_o;
+wire wbs0_cyc_o;
+wire [ADDR_WIDTH-1:0] wbs1_adr_o;
+wire [DATA_WIDTH-1:0] wbs1_dat_o;
+wire wbs1_we_o;
+wire [SELECT_WIDTH-1:0] wbs1_sel_o;
+wire wbs1_stb_o;
+wire wbs1_cyc_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(clk,
+ rst,
+ current_test,
+ wbm_adr_i,
+ wbm_dat_i,
+ wbm_we_i,
+ wbm_sel_i,
+ wbm_stb_i,
+ wbm_cyc_i,
+ wbs0_dat_i,
+ wbs0_ack_i,
+ wbs0_err_i,
+ wbs0_rty_i,
+ wbs0_addr,
+ wbs0_addr_msk,
+ wbs1_dat_i,
+ wbs1_ack_i,
+ wbs1_err_i,
+ wbs1_rty_i,
+ wbs1_addr,
+ wbs1_addr_msk);
+ $to_myhdl(wbm_dat_o,
+ wbm_ack_o,
+ wbm_err_o,
+ wbm_rty_o,
+ wbs0_adr_o,
+ wbs0_dat_o,
+ wbs0_we_o,
+ wbs0_sel_o,
+ wbs0_stb_o,
+ wbs0_cyc_o,
+ wbs1_adr_o,
+ wbs1_dat_o,
+ wbs1_we_o,
+ wbs1_sel_o,
+ wbs1_stb_o,
+ wbs1_cyc_o);
+
+ // dump file
+ $dumpfile("test_wb_mux_2.lxt");
+ $dumpvars(0, test_wb_mux_2);
+end
+
+wb_mux_2 #(
+ .DATA_WIDTH(DATA_WIDTH),
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .SELECT_WIDTH(SELECT_WIDTH)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .wbm_adr_i(wbm_adr_i),
+ .wbm_dat_i(wbm_dat_i),
+ .wbm_dat_o(wbm_dat_o),
+ .wbm_we_i(wbm_we_i),
+ .wbm_sel_i(wbm_sel_i),
+ .wbm_stb_i(wbm_stb_i),
+ .wbm_ack_o(wbm_ack_o),
+ .wbm_err_o(wbm_err_o),
+ .wbm_rty_o(wbm_rty_o),
+ .wbm_cyc_i(wbm_cyc_i),
+ .wbs0_adr_o(wbs0_adr_o),
+ .wbs0_dat_i(wbs0_dat_i),
+ .wbs0_dat_o(wbs0_dat_o),
+ .wbs0_we_o(wbs0_we_o),
+ .wbs0_sel_o(wbs0_sel_o),
+ .wbs0_stb_o(wbs0_stb_o),
+ .wbs0_ack_i(wbs0_ack_i),
+ .wbs0_err_i(wbs0_err_i),
+ .wbs0_rty_i(wbs0_rty_i),
+ .wbs0_cyc_o(wbs0_cyc_o),
+ .wbs0_addr(wbs0_addr),
+ .wbs0_addr_msk(wbs0_addr_msk),
+ .wbs1_adr_o(wbs1_adr_o),
+ .wbs1_dat_i(wbs1_dat_i),
+ .wbs1_dat_o(wbs1_dat_o),
+ .wbs1_we_o(wbs1_we_o),
+ .wbs1_sel_o(wbs1_sel_o),
+ .wbs1_stb_o(wbs1_stb_o),
+ .wbs1_ack_i(wbs1_ack_i),
+ .wbs1_err_i(wbs1_err_i),
+ .wbs1_rty_i(wbs1_rty_i),
+ .wbs1_cyc_o(wbs1_cyc_o),
+ .wbs1_addr(wbs1_addr),
+ .wbs1_addr_msk(wbs1_addr_msk)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_ram.py b/ip/third_party/verilog-wishbone/tb/test_wb_ram.py
new file mode 100755
index 0000000..7b43232
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_ram.py
@@ -0,0 +1,170 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_ram'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ DATA_WIDTH = 32
+ ADDR_WIDTH = 16
+ SELECT_WIDTH = 4
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ we_i = Signal(bool(0))
+ sel_i = Signal(intbv(0)[SELECT_WIDTH:])
+ stb_i = Signal(bool(0))
+ cyc_i = Signal(bool(0))
+
+ # Outputs
+ dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ ack_o = Signal(bool(0))
+
+ # WB master
+ wbm_inst = wb.WBMaster()
+
+ wbm_logic = wbm_inst.create_logic(
+ clk,
+ adr_o=adr_i,
+ dat_i=dat_o,
+ dat_o=dat_i,
+ we_o=we_i,
+ sel_o=sel_i,
+ stb_o=stb_i,
+ ack_i=ack_o,
+ cyc_o=cyc_i,
+ name='master'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+ adr_i=adr_i,
+ dat_i=dat_i,
+ dat_o=dat_o,
+ we_i=we_i,
+ sel_i=sel_i,
+ stb_i=stb_i,
+ ack_o=ack_o,
+ cyc_i=cyc_i
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+ print("test 1: read and write")
+ current_test.next = 1
+
+ wbm_inst.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ wbm_inst.init_read(4, 4)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: various reads and writes")
+ current_test.next = 2
+
+ for length in range(1,8):
+ for offset in range(4):
+ wbm_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ for length in range(1,8):
+ for offset in range(4):
+ wbm_inst.init_read(256*(16*offset+length)+offset, length)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_ram.v b/ip/third_party/verilog-wishbone/tb/test_wb_ram.v
new file mode 100644
index 0000000..707d04c
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_ram.v
@@ -0,0 +1,95 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_ram
+ */
+module test_wb_ram;
+
+// Parameters
+parameter DATA_WIDTH = 32;
+parameter ADDR_WIDTH = 16;
+parameter SELECT_WIDTH = 4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] adr_i = 0;
+reg [DATA_WIDTH-1:0] dat_i = 0;
+reg we_i = 0;
+reg [SELECT_WIDTH-1:0] sel_i = 0;
+reg stb_i = 0;
+reg cyc_i = 0;
+
+// Outputs
+wire [DATA_WIDTH-1:0] dat_o;
+wire ack_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ adr_i,
+ dat_i,
+ we_i,
+ sel_i,
+ stb_i,
+ cyc_i
+ );
+ $to_myhdl(
+ dat_o,
+ ack_o
+ );
+
+ // dump file
+ $dumpfile("test_wb_ram.lxt");
+ $dumpvars(0, test_wb_ram);
+end
+
+wb_ram #(
+ .DATA_WIDTH(DATA_WIDTH),
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .SELECT_WIDTH(SELECT_WIDTH)
+)
+UUT (
+ .clk(clk),
+ .adr_i(adr_i),
+ .dat_i(dat_i),
+ .dat_o(dat_o),
+ .we_i(we_i),
+ .sel_i(sel_i),
+ .stb_i(stb_i),
+ .ack_o(ack_o),
+ .cyc_i(cyc_i)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_ram_model.py b/ip/third_party/verilog-wishbone/tb/test_wb_ram_model.py
new file mode 100755
index 0000000..5daeb7a
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_ram_model.py
@@ -0,0 +1,259 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+def bench():
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ port0_adr_i = Signal(intbv(0)[32:])
+ port0_dat_i = Signal(intbv(0)[32:])
+ port0_we_i = Signal(bool(0))
+ port0_sel_i = Signal(intbv(0)[4:])
+ port0_stb_i = Signal(bool(0))
+ port0_cyc_i = Signal(bool(0))
+
+ # Outputs
+ port0_dat_o = Signal(intbv(0)[32:])
+ port0_ack_o = Signal(bool(0))
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=port0_adr_i,
+ dat_i=port0_dat_i,
+ dat_o=port0_dat_o,
+ we_i=port0_we_i,
+ sel_i=port0_sel_i,
+ stb_i=port0_stb_i,
+ ack_o=port0_ack_o,
+ cyc_i=port0_cyc_i,
+ latency=1,
+ asynchronous=False,
+ name='port0'
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+ print("test 1: baseline")
+ current_test.next = 1
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: direct write")
+ current_test.next = 2
+
+ wb_ram_inst.write_mem(0, b'test')
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(0,4) == b'test'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: write via port0")
+ current_test.next = 2
+
+ yield clk.posedge
+ port0_adr_i.next = 4
+ port0_dat_i.next = 0x44332211
+ port0_sel_i.next = 0xF
+ port0_we_i.next = 1
+
+ port0_cyc_i.next = 1
+ port0_stb_i.next = 1
+
+ yield port0_ack_o.posedge
+ yield clk.posedge
+ port0_we_i.next = 0
+ port0_cyc_i.next = 0
+ port0_stb_i.next = 0
+
+ yield clk.posedge
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: read via port0")
+ current_test.next = 3
+
+ yield clk.posedge
+ port0_adr_i.next = 4
+ port0_we_i.next = 0
+
+ port0_cyc_i.next = 1
+ port0_stb_i.next = 1
+
+ yield port0_ack_o.posedge
+ yield clk.posedge
+ port0_we_i.next = 0
+ port0_cyc_i.next = 0
+ port0_stb_i.next = 0
+
+ assert port0_dat_o == 0x44332211
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: various writes")
+ current_test.next = 4
+
+ for length in range(1,8):
+ for offset in range(4):
+ yield clk.posedge
+ sel_start = ((2**(4)-1) << offset % 4) & (2**(4)-1)
+ sel_end = ((2**(4)-1) >> (4 - (((offset + int(length/1) - 1) % 4) + 1)))
+ cycles = int((length + 4-1 + (offset % 4)) / 4)
+ i = 1
+
+ port0_cyc_i.next = 1
+
+ port0_stb_i.next = 1
+ port0_we_i.next = 1
+ port0_adr_i.next = 256*(16*offset+length)
+ val = 0
+ for j in range(4):
+ if j >= offset % 4 and (cycles > 1 or j < (((offset + int(length/1) - 1) % 4) + 1)):
+ val |= (0x11 * i) << j*8
+ i += 1
+ port0_dat_i.next = val
+ if cycles == 1:
+ port0_sel_i.next = sel_start & sel_end
+ else:
+ port0_sel_i.next = sel_start
+
+ yield clk.posedge
+ while not port0_ack_o:
+ yield clk.posedge
+
+ port0_we_i.next = 0
+ port0_stb_i.next = 0
+
+ for k in range(1,cycles-1):
+ yield clk.posedge
+ port0_stb_i.next = 1
+ port0_we_i.next = 1
+ port0_adr_i.next = 256*(16*offset+length)+4*k
+ val = 0
+ for j in range(4):
+ val |= (0x11 * i) << j*8
+ i += 1
+ port0_dat_i.next = val
+ port0_sel_i.next = 2**(4)-1
+
+ yield clk.posedge
+ while not port0_ack_o:
+ yield clk.posedge
+
+ port0_we_i.next = 0
+ port0_stb_i.next = 0
+
+ if cycles > 1:
+ yield clk.posedge
+ port0_stb_i.next = 1
+ port0_we_i.next = 1
+ port0_adr_i.next = 256*(16*offset+length)+4*(cycles-1)
+ val = 0
+ for j in range(4):
+ if j < (((offset + int(length/1) - 1) % 4) + 1):
+ val |= (0x11 * i) << j*8
+ i += 1
+ port0_dat_i.next = val
+ port0_sel_i.next = sel_end
+
+ yield clk.posedge
+ while not port0_ack_o:
+ yield clk.posedge
+
+ port0_we_i.next = 0
+ port0_stb_i.next = 0
+
+ port0_we_i.next = 0
+ port0_stb_i.next = 0
+
+ port0_cyc_i.next = 0
+
+ yield clk.posedge
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset,length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ os.chdir(os.path.dirname(os.path.abspath(__file__)))
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
+
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_reg.py b/ip/third_party/verilog-wishbone/tb/test_wb_reg.py
new file mode 100755
index 0000000..0a682ec
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_reg.py
@@ -0,0 +1,239 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import wb
+
+module = 'wb_reg'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+ # Parameters
+ DATA_WIDTH = 32
+ ADDR_WIDTH = 32
+ SELECT_WIDTH = 4
+
+ # Inputs
+ clk = Signal(bool(0))
+ rst = Signal(bool(0))
+ current_test = Signal(intbv(0)[8:])
+
+ wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
+ wbm_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbm_we_i = Signal(bool(0))
+ wbm_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
+ wbm_stb_i = Signal(bool(0))
+ wbm_cyc_i = Signal(bool(0))
+ wbs_dat_i = Signal(intbv(0)[DATA_WIDTH:])
+ wbs_ack_i = Signal(bool(0))
+ wbs_err_i = Signal(bool(0))
+ wbs_rty_i = Signal(bool(0))
+
+ # Outputs
+ wbm_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbm_ack_o = Signal(bool(0))
+ wbm_err_o = Signal(bool(0))
+ wbm_rty_o = Signal(bool(0))
+ wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
+ wbs_dat_o = Signal(intbv(0)[DATA_WIDTH:])
+ wbs_we_o = Signal(bool(0))
+ wbs_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
+ wbs_stb_o = Signal(bool(0))
+ wbs_cyc_o = Signal(bool(0))
+
+ # WB master
+ wbm_inst = wb.WBMaster()
+
+ wbm_logic = wbm_inst.create_logic(
+ clk,
+ adr_o=wbm_adr_i,
+ dat_i=wbm_dat_o,
+ dat_o=wbm_dat_i,
+ we_o=wbm_we_i,
+ sel_o=wbm_sel_i,
+ stb_o=wbm_stb_i,
+ ack_i=wbm_ack_o,
+ cyc_o=wbm_cyc_i,
+ name='master'
+ )
+
+ # WB RAM model
+ wb_ram_inst = wb.WBRam(2**16)
+
+ wb_ram_port0 = wb_ram_inst.create_port(
+ clk,
+ adr_i=wbs_adr_o,
+ dat_i=wbs_dat_o,
+ dat_o=wbs_dat_i,
+ we_i=wbs_we_o,
+ sel_i=wbs_sel_o,
+ stb_i=wbs_stb_o,
+ ack_o=wbs_ack_i,
+ cyc_i=wbs_cyc_o,
+ latency=1,
+ asynchronous=False,
+ name='slave'
+ )
+
+ # DUT
+ if os.system(build_cmd):
+ raise Exception("Error running build command")
+
+ dut = Cosimulation(
+ "vvp -m myhdl %s.vvp -lxt2" % testbench,
+ clk=clk,
+ rst=rst,
+ current_test=current_test,
+ wbm_adr_i=wbm_adr_i,
+ wbm_dat_i=wbm_dat_i,
+ wbm_dat_o=wbm_dat_o,
+ wbm_we_i=wbm_we_i,
+ wbm_sel_i=wbm_sel_i,
+ wbm_stb_i=wbm_stb_i,
+ wbm_ack_o=wbm_ack_o,
+ wbm_err_o=wbm_err_o,
+ wbm_rty_o=wbm_rty_o,
+ wbm_cyc_i=wbm_cyc_i,
+ wbs_adr_o=wbs_adr_o,
+ wbs_dat_i=wbs_dat_i,
+ wbs_dat_o=wbs_dat_o,
+ wbs_we_o=wbs_we_o,
+ wbs_sel_o=wbs_sel_o,
+ wbs_stb_o=wbs_stb_o,
+ wbs_ack_i=wbs_ack_i,
+ wbs_err_i=wbs_err_i,
+ wbs_rty_i=wbs_rty_i,
+ wbs_cyc_o=wbs_cyc_o
+ )
+
+ @always(delay(4))
+ def clkgen():
+ clk.next = not clk
+
+ @instance
+ def check():
+ yield delay(100)
+ yield clk.posedge
+ rst.next = 1
+ yield clk.posedge
+ rst.next = 0
+ yield clk.posedge
+ yield delay(100)
+ yield clk.posedge
+
+ yield clk.posedge
+ print("test 1: write")
+ current_test.next = 1
+
+ wbm_inst.init_write(4, b'\x11\x22\x33\x44')
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(0, 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 2: read")
+ current_test.next = 2
+
+ wbm_inst.init_read(4, 4)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 4
+ assert data[1] == b'\x11\x22\x33\x44'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 3: various writes")
+ current_test.next = 3
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wb_ram_inst.write_mem(256*(16*offset+length), b'\xAA'*32)
+ wbm_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wb_ram_inst.read_mem(256*(16*offset+length), 32)
+ for i in range(0, len(data), 16):
+ print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
+
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset, length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset-1, 1) == b'\xAA'
+ assert wb_ram_inst.read_mem(256*(16*offset+length)+offset+length, 1) == b'\xAA'
+
+ yield delay(100)
+
+ yield clk.posedge
+ print("test 4: various reads")
+ current_test.next = 4
+
+ for length in range(1,8):
+ for offset in range(4,8):
+ wbm_inst.init_read(256*(16*offset+length)+offset, length)
+
+ yield wbm_inst.wait()
+ yield clk.posedge
+
+ data = wbm_inst.get_read_data()
+ assert data[0] == 256*(16*offset+length)+offset
+ assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
+
+ yield delay(100)
+
+ raise StopSimulation
+
+ return instances()
+
+def test_bench():
+ sim = Simulation(bench())
+ sim.run()
+
+if __name__ == '__main__':
+ print("Running test...")
+ test_bench()
diff --git a/ip/third_party/verilog-wishbone/tb/test_wb_reg.v b/ip/third_party/verilog-wishbone/tb/test_wb_reg.v
new file mode 100644
index 0000000..3a20813
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/test_wb_reg.v
@@ -0,0 +1,132 @@
+/*
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for wb_reg
+ */
+module test_wb_reg;
+
+// Parameters
+parameter DATA_WIDTH = 32;
+parameter ADDR_WIDTH = 32;
+parameter SELECT_WIDTH = 4;
+
+// Inputs
+reg clk = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
+reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
+reg wbm_we_i = 0;
+reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
+reg wbm_stb_i = 0;
+reg wbm_cyc_i = 0;
+reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
+reg wbs_ack_i = 0;
+reg wbs_err_i = 0;
+reg wbs_rty_i = 0;
+
+// Outputs
+wire [DATA_WIDTH-1:0] wbm_dat_o;
+wire wbm_ack_o;
+wire wbm_err_o;
+wire wbm_rty_o;
+wire [ADDR_WIDTH-1:0] wbs_adr_o;
+wire [DATA_WIDTH-1:0] wbs_dat_o;
+wire wbs_we_o;
+wire [SELECT_WIDTH-1:0] wbs_sel_o;
+wire wbs_stb_o;
+wire wbs_cyc_o;
+
+initial begin
+ // myhdl integration
+ $from_myhdl(
+ clk,
+ rst,
+ current_test,
+ wbm_adr_i,
+ wbm_dat_i,
+ wbm_we_i,
+ wbm_sel_i,
+ wbm_stb_i,
+ wbm_cyc_i,
+ wbs_dat_i,
+ wbs_ack_i,
+ wbs_err_i,
+ wbs_rty_i
+ );
+ $to_myhdl(
+ wbm_dat_o,
+ wbm_ack_o,
+ wbm_err_o,
+ wbm_rty_o,
+ wbs_adr_o,
+ wbs_dat_o,
+ wbs_we_o,
+ wbs_sel_o,
+ wbs_stb_o,
+ wbs_cyc_o
+ );
+
+ // dump file
+ $dumpfile("test_wb_reg.lxt");
+ $dumpvars(0, test_wb_reg);
+end
+
+wb_reg #(
+ .DATA_WIDTH(DATA_WIDTH),
+ .ADDR_WIDTH(ADDR_WIDTH),
+ .SELECT_WIDTH(SELECT_WIDTH)
+)
+UUT (
+ .clk(clk),
+ .rst(rst),
+ .wbm_adr_i(wbm_adr_i),
+ .wbm_dat_i(wbm_dat_i),
+ .wbm_dat_o(wbm_dat_o),
+ .wbm_we_i(wbm_we_i),
+ .wbm_sel_i(wbm_sel_i),
+ .wbm_stb_i(wbm_stb_i),
+ .wbm_ack_o(wbm_ack_o),
+ .wbm_err_o(wbm_err_o),
+ .wbm_rty_o(wbm_rty_o),
+ .wbm_cyc_i(wbm_cyc_i),
+ .wbs_adr_o(wbs_adr_o),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_dat_o(wbs_dat_o),
+ .wbs_we_o(wbs_we_o),
+ .wbs_sel_o(wbs_sel_o),
+ .wbs_stb_o(wbs_stb_o),
+ .wbs_ack_i(wbs_ack_i),
+ .wbs_err_i(wbs_err_i),
+ .wbs_rty_i(wbs_rty_i),
+ .wbs_cyc_o(wbs_cyc_o)
+);
+
+endmodule
diff --git a/ip/third_party/verilog-wishbone/tb/wb.py b/ip/third_party/verilog-wishbone/tb/wb.py
new file mode 100644
index 0000000..b618ef8
--- /dev/null
+++ b/ip/third_party/verilog-wishbone/tb/wb.py
@@ -0,0 +1,441 @@
+"""
+
+Copyright (c) 2015-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import mmap
+
+class WBMaster(object):
+ def __init__(self):
+ self.command_queue = []
+ self.read_data_queue = []
+ self.has_logic = False
+ self.clk = None
+ self.cyc_o = None
+
+ def init_read(self, address, length):
+ self.command_queue.append(('r', address, length))
+
+ def init_read_words(self, address, length, ws=2):
+ assert ws in (1, 2, 4, 8)
+ self.init_read(int(address*ws), int(length*ws))
+
+ def init_read_dwords(self, address, length):
+ self.init_read_words(address, length, 4)
+
+ def init_read_qwords(self, address, length):
+ self.init_read_words(address, length, 8)
+
+ def init_write(self, address, data):
+ self.command_queue.append(('w', address, data))
+
+ def init_write_words(self, address, data, ws=2):
+ assert ws in (1, 2, 4, 8)
+ data2 = []
+ for w in data:
+ d = []
+ for j in range(ws):
+ d.append(w&0xff)
+ w >>= 8
+ data2.extend(bytearray(d))
+ self.init_write(int(address*ws), data2)
+
+ def init_write_dwords(self, address, data):
+ self.init_write_words(address, data, 4)
+
+ def init_write_qwords(self, address, data):
+ self.init_write_words(address, data, 8)
+
+ def idle(self):
+ return len(self.command_queue) == 0 and not self.cyc_o.next
+
+ def wait(self):
+ while not self.idle():
+ yield self.clk.posedge
+
+ def read_data_ready(self):
+ return not self.read_data_queue
+
+ def get_read_data(self):
+ return self.read_data_queue.pop(0)
+
+ def get_read_data_words(self, ws=2):
+ assert ws in (1, 2, 4, 8)
+ v = self.get_read_data()
+ if v is None:
+ return None
+ address, data = v
+ d = []
+ for i in range(int(len(data)/ws)):
+ w = 0
+ for j in range(ws-1,-1,-1):
+ w <<= 8
+ w += data[i*ws+j]
+ d.append(w)
+ return (int(address/ws), d)
+
+ def get_read_data_dwords(self):
+ return self.get_read_data_words(4)
+
+ def get_read_data_qwords(self):
+ return self.get_read_data_words(8)
+
+ def create_logic(self,
+ clk,
+ adr_o=Signal(intbv(0)[8:]),
+ dat_i=None,
+ dat_o=None,
+ we_o=Signal(bool(0)),
+ sel_o=Signal(intbv(1)[1:]),
+ stb_o=Signal(bool(0)),
+ ack_i=Signal(bool(0)),
+ cyc_o=Signal(bool(0)),
+ name=None
+ ):
+
+ if self.has_logic:
+ raise Exception("Logic already instantiated!")
+
+ if dat_i is not None:
+ assert len(dat_i) % 8 == 0
+ w = len(dat_i)
+ if dat_o is not None:
+ assert len(dat_o) % 8 == 0
+ w = len(dat_o)
+ if dat_i is not None and dat_o is not None:
+ assert len(dat_i) == len(dat_o)
+
+ bw = int(w/8) # width of bus in bytes
+ ww = len(sel_o) # width of bus in words
+ ws = int(bw/ww) # word size in bytes
+
+ assert ww in (1, 2, 4, 8)
+ assert ws in (1, 2, 4, 8)
+
+ self.has_logic = True
+ self.clk = clk
+ self.cyc_o = cyc_o
+
+ @instance
+ def logic():
+ while True:
+ yield clk.posedge
+
+ # check for commands
+ if len(self.command_queue) > 0:
+ cmd = self.command_queue.pop(0)
+
+ # address
+ addr = cmd[1]
+ # address in words
+ adw = int(addr/ws)
+ # select for first access
+ sel_start = ((2**(ww)-1) << int(adw % ww)) & (2**(ww)-1)
+
+ if cmd[0] == 'w':
+ data = cmd[2]
+ # select for last access
+ sel_end = (2**(ww)-1) >> int(ww - (((int((addr+len(data)-1)/ws)) % ww) + 1))
+ # number of cycles
+ cycles = int((len(data) + bw-1 + (addr % bw)) / bw)
+ i = 0
+
+ if name is not None:
+ print("[%s] Write data a:0x%08x d:%s" % (name, addr, " ".join(("{:02x}".format(c) for c in bytearray(data)))))
+
+ cyc_o.next = 1
+
+ # first cycle
+ stb_o.next = 1
+ we_o.next = 1
+ adr_o.next = int(adw/ww)*ww
+ val = 0
+ for j in range(bw):
+ if j >= addr % bw and (cycles > 1 or j < (((addr + len(data) - 1) % bw) + 1)):
+ val |= bytearray(data)[i] << j*8
+ i += 1
+ dat_o.next = val
+
+ if cycles == 1:
+ sel_o.next = sel_start & sel_end
+ else:
+ sel_o.next = sel_start
+
+ yield clk.posedge
+ while not int(ack_i):
+ yield clk.posedge
+
+ stb_o.next = 0
+ we_o.next = 0
+
+ for k in range(1, cycles-1):
+ # middle cycles
+ yield clk.posedge
+ stb_o.next = 1
+ we_o.next = 1
+ adr_o.next = int(adw/ww)*ww + k * ww
+ val = 0
+ for j in range(bw):
+ val |= bytearray(data)[i] << j*8
+ i += 1
+ dat_o.next = val
+ sel_o.next = 2**(ww)-1
+
+ yield clk.posedge
+ while not int(ack_i):
+ yield clk.posedge
+
+ stb_o.next = 0
+ we_o.next = 0
+
+ if cycles > 1:
+ # last cycle
+ yield clk.posedge
+ stb_o.next = 1
+ we_o.next = 1
+ adr_o.next = int(adw/ww)*ww + (cycles-1) * ww
+ val = 0
+ for j in range(bw):
+ if j < (((addr + len(data) - 1) % bw) + 1):
+ val |= bytearray(data)[i] << j*8
+ i += 1
+ dat_o.next = val
+ sel_o.next = sel_end
+
+ yield clk.posedge
+ while not int(ack_i):
+ yield clk.posedge
+
+ stb_o.next = 0
+ we_o.next = 0
+
+ we_o.next = 0
+ stb_o.next = 0
+
+ cyc_o.next = 0
+
+ elif cmd[0] == 'r':
+ length = cmd[2]
+ data = b''
+ # select for last access
+ sel_end = (2**(ww)-1) >> int(ww - (((int((addr+length-1)/ws)) % ww) + 1))
+ # number of cycles
+ cycles = int((length + bw-1 + (addr % bw)) / bw)
+
+ cyc_o.next = 1
+
+ # first cycle
+ stb_o.next = 1
+ adr_o.next = int(adw/ww)*ww
+ if cycles == 1:
+ sel_o.next = sel_start & sel_end
+ else:
+ sel_o.next = sel_start
+
+ yield clk.posedge
+ while not int(ack_i):
+ yield clk.posedge
+
+ stb_o.next = 0
+
+ val = int(dat_i)
+
+ for j in range(bw):
+ if j >= addr % bw and (cycles > 1 or j < (((addr + length - 1) % bw) + 1)):
+ data += bytes(bytearray([(val >> j*8) & 255]))
+
+ for k in range(1, cycles-1):
+ # middle cycles
+ yield clk.posedge
+ stb_o.next = 1
+ adr_o.next = int(adw/ww)*ww + k * ww
+ sel_o.next = 2**(ww)-1
+
+ yield clk.posedge
+ while not int(ack_i):
+ yield clk.posedge
+
+ stb_o.next = 0
+
+ val = int(dat_i)
+
+ for j in range(bw):
+ data += bytes(bytearray([(val >> j*8) & 255]))
+
+ if cycles > 1:
+ # last cycle
+ yield clk.posedge
+ stb_o.next = 1
+ adr_o.next = int(adw/ww)*ww + (cycles-1) * ww
+ sel_o.next = sel_end
+
+ yield clk.posedge
+ while not int(ack_i):
+ yield clk.posedge
+
+ stb_o.next = 0
+
+ val = int(dat_i)
+
+ for j in range(bw):
+ if j < (((addr + length - 1) % bw) + 1):
+ data += bytes(bytearray([(val >> j*8) & 255]))
+
+ stb_o.next = 0
+ cyc_o.next = 0
+
+ if name is not None:
+ print("[%s] Read data a:0x%08x d:%s" % (name, addr, " ".join(("{:02x}".format(c) for c in bytearray(data)))))
+
+ self.read_data_queue.append((addr, data))
+
+ return instances()
+
+
+class WBRam(object):
+ def __init__(self, size = 1024):
+ self.size = size
+ self.mem = mmap.mmap(-1, size)
+
+ def read_mem(self, address, length):
+ self.mem.seek(address)
+ return self.mem.read(length)
+
+ def write_mem(self, address, data):
+ self.mem.seek(address)
+ self.mem.write(data)
+
+ def read_words(self, address, length, ws=2):
+ assert ws in (1, 2, 4, 8)
+ self.mem.seek(int(address*ws))
+ d = []
+ for i in range(length):
+ w = 0
+ data = bytearray(self.mem.read(ws))
+ for j in range(ws-1,-1,-1):
+ w <<= 8
+ w += data[j]
+ d.append(w)
+ return d
+
+ def read_dwords(self, address, length):
+ return self.read_words(address, length, 4)
+
+ def read_qwords(self, address, length):
+ return self.read_words(address, length, 8)
+
+ def write_words(self, address, data, ws=2):
+ assert ws in (1, 2, 4, 8)
+ self.mem.seek(int(address*ws))
+ for w in data:
+ d = []
+ for j in range(ws):
+ d.append(w&0xff)
+ w >>= 8
+ self.mem.write(bytearray(d))
+
+ def write_dwords(self, address, length):
+ return self.write_words(address, length, 4)
+
+ def write_qwords(self, address, length):
+ return self.write_words(address, length, 8)
+
+ def create_port(self,
+ clk,
+ adr_i=Signal(intbv(0)[8:]),
+ dat_i=None,
+ dat_o=None,
+ we_i=Signal(bool(0)),
+ sel_i=Signal(intbv(1)[1:]),
+ stb_i=Signal(bool(0)),
+ ack_o=Signal(bool(0)),
+ cyc_i=Signal(bool(0)),
+ latency=1,
+ asynchronous=False,
+ name=None
+ ):
+
+ if dat_i is not None:
+ assert len(dat_i) % 8 == 0
+ w = len(dat_i)
+ if dat_o is not None:
+ assert len(dat_o) % 8 == 0
+ w = len(dat_o)
+ if dat_i is not None and dat_o is not None:
+ assert len(dat_i) == len(dat_o)
+
+ bw = int(w/8) # width of bus in bytes
+ ww = len(sel_i) # width of bus in words
+ ws = int(bw/ww) # word size in bytes
+
+ assert ww in (1, 2, 4, 8)
+ assert ws in (1, 2, 4, 8)
+
+ @instance
+ def logic():
+ while True:
+ if asynchronous:
+ yield adr_i, cyc_i, stb_i
+ else:
+ yield clk.posedge
+
+ ack_o.next = False
+
+ # address in increments of bus word width
+ addr = int(int(adr_i)/ww)*ww
+
+ if cyc_i & stb_i & ~ack_o:
+ if asynchronous:
+ yield delay(latency)
+ else:
+ for i in range(latency):
+ yield clk.posedge
+ ack_o.next = True
+ self.mem.seek(addr*ws % self.size)
+ if we_i:
+ # write
+ data = []
+ val = int(dat_i)
+ for i in range(bw):
+ data += [val & 0xff]
+ val >>= 8
+ data = bytearray(data)
+ for i in range(ww):
+ if sel_i & (1 << i):
+ self.mem.write(data[i*ws:(i+1)*ws])
+ else:
+ self.mem.seek(ws, 1)
+ if name is not None:
+ print("[%s] Write word a:0x%08x sel:0x%02x d:%s" % (name, addr, sel_i, " ".join(("{:02x}".format(c) for c in bytearray(data)))))
+ else:
+ data = bytearray(self.mem.read(bw))
+ val = 0
+ for i in range(bw-1,-1,-1):
+ val <<= 8
+ val += data[i]
+ dat_o.next = val
+ if name is not None:
+ print("[%s] Read word a:0x%08x d:%s" % (name, addr, " ".join(("{:02x}".format(c) for c in bytearray(data)))))
+
+ return instances()
+
