last version not working
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json index c0ac816..1e5b206 100644 --- a/openlane/user_proj_example/config.json +++ b/openlane/user_proj_example/config.json
@@ -2,7 +2,7 @@ "PDK" : "sky130A", "STD_CELL_LIBRARY" : "sky130_fd_sc_hd", "CARAVEL_ROOT" : "../../caravel", - "CLOCK_NET" : "main_module.clk", + "CLOCK_NET" : "main_module_ins.wb_clk_i", "CLOCK_PERIOD" : "10", "CLOCK_PORT" : "wb_clk_i", "DESIGN_IS_CORE" : "0",
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl index b835ad6..30f4576 100755 --- a/openlane/user_proj_example/config.tcl +++ b/openlane/user_proj_example/config.tcl
@@ -36,7 +36,7 @@ set ::env(DESIGN_IS_CORE) 0 set ::env(CLOCK_PORT) "wb_clk_i" -set ::env(CLOCK_NET) "main_module.clk" +set ::env(CLOCK_NET) "wb_clk_i" set ::env(CLOCK_PERIOD) "10" set ::env(FP_SIZING) absolute
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 5006ced..7f5724e 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -38,8 +38,8 @@ $script_dir/../../verilog/rtl/user_project_wrapper.v" ## Clock configurations -set ::env(CLOCK_PORT) "user_clock2" -set ::env(CLOCK_NET) "mprj.clk" +set ::env(CLOCK_PORT) "wb_clk_i" +set ::env(CLOCK_NET) "mprj.wbs_cyc_i" set ::env(CLOCK_PERIOD) "10"
diff --git a/verilog/rtl/controller/control_module.v b/verilog/rtl/controller/control_module.v index 67ded59..798d42d 100644 --- a/verilog/rtl/controller/control_module.v +++ b/verilog/rtl/controller/control_module.v
@@ -33,7 +33,7 @@ parameter OUTPUTS = 32, parameter INPUTS = 32, parameter INSTRUCTION_SIZE = 3, - parameter SIZE_WORD_REGISTER = 5 + parameter SIZE_WORD_REGISTER = 3 ) (
diff --git a/verilog/rtl/controller/logic_control.v b/verilog/rtl/controller/logic_control.v index fe6a5a9..eccd0e9 100644 --- a/verilog/rtl/controller/logic_control.v +++ b/verilog/rtl/controller/logic_control.v
@@ -30,7 +30,7 @@ parameter STATUS_SIGNALS = 6, parameter DATA_WIDTH = 8, parameter INSTRUCTION_SIZE = 3, - parameter SIZE_WORD_REGISTER = 5, + parameter SIZE_WORD_REGISTER = 3, parameter INSTRUCCION_INPUT_START = INPUT_DATA_SIZE - 1 , //51 parameter INSTRUCCION_INPUT_END = INSTRUCCION_INPUT_START - (INSTRUCTION_SIZE - 1), // 49 parameter REGISTER_INPUT_START = INSTRUCCION_INPUT_END -1, // 48
diff --git a/verilog/rtl/controller/pmu.v b/verilog/rtl/controller/pmu.v index 47060b1..8d9eba7 100644 --- a/verilog/rtl/controller/pmu.v +++ b/verilog/rtl/controller/pmu.v
@@ -20,31 +20,76 @@ input wire [WHISBONE_ADR - 1 : 0] wbs_adr_i, input wire valid_i, input wire wbs_we_i, + input wire [2:0] trx_error, + input wire [2:0] output_io_error, output reg ready_o, output reg [WORD_SIZE - 1 : 0] rdata_o ); -reg [COUNTERSIZE-1:0] total_clk_pass; +reg [COUNTERSIZE-1:0] total_errors_trx [0:2]; +reg [COUNTERSIZE-1:0] total_errors_io [0:2]; +reg [COUNTERSIZE-1:0] total_unrecobable_errors_trx; +reg [COUNTERSIZE-1:0] total_unrecobable_errors_io; always @(posedge clk) begin if(rst) begin - total_clk_pass <= {WORD_SIZE {1'b0}}; + total_errors_trx[0] <= {WORD_SIZE {1'b0}}; + total_errors_trx[1] <= {WORD_SIZE {1'b0}}; + total_errors_trx[2] <= {WORD_SIZE {1'b0}}; + total_errors_io[0] <= {WORD_SIZE {1'b0}}; + total_errors_io[1] <= {WORD_SIZE {1'b0}}; + total_errors_io[2] <= {WORD_SIZE {1'b0}}; + end else begin - total_clk_pass <= total_clk_pass + 1; + // couting errors + if (trx_error != 3'b000) begin + case (trx_error) + 3'b001: total_errors_trx[0] <= total_errors_trx[0] + 1; + 3'b010: total_errors_trx[1] <= total_errors_trx[1] + 1; + 3'b100: total_errors_trx[2] <= total_errors_trx[2] + 1; + default: total_unrecobable_errors_trx = total_unrecobable_errors_trx + 1; + endcase + end + if (output_io_error != 3'b000) begin + case (trx_error) + 3'b001: total_errors_io[0] <= total_errors_io[0] + 1; + 3'b010: total_errors_io[1] <= total_errors_io[1] + 1; + 3'b100: total_errors_io[2] <= total_errors_io[2] + 1; + default: total_unrecobable_errors_io = total_unrecobable_errors_io + 1; + endcase + end + if (valid_i && wbs_adr_i[31:12] == ADDRBASE) begin - ready_o <= 1'b1; - if (wbs_we_i) begin - if (wstrb_i[0]) total_clk_pass[7:0] <= wdata_i[7:0]; - if (wstrb_i[1]) total_clk_pass[15:8] <= wdata_i[15:8]; - if (wstrb_i[2]) total_clk_pass[23:16] <= wdata_i[23:16]; - if (wstrb_i[3]) total_clk_pass[31:24] <= wdata_i[31:24]; - end - else begin - rdata_o <= {total_clk_pass}; - end + case (wbs_adr_i[3:0]) + 4'h0: begin + ready_o <= 1'b1; + if (wbs_we_i) begin + if (wstrb_i[0]) total_errors_trx[wbs_adr_i[5:4]][7:0] <= wdata_i[7:0]; + if (wstrb_i[1]) total_errors_trx[wbs_adr_i[5:4]][15:8] <= wdata_i[15:8]; + if (wstrb_i[2]) total_errors_trx[wbs_adr_i[5:4]][23:16] <= wdata_i[23:16]; + if (wstrb_i[3]) total_errors_trx[wbs_adr_i[5:4]][31:24] <= wdata_i[31:24]; + end + else begin + rdata_o <= {total_errors_trx[wbs_adr_i[5:4]]}; + end + + end + 4'h4: begin + ready_o <= 1'b1; + if (wbs_we_i) begin + if (wstrb_i[0]) total_errors_io[wbs_adr_i[5:4]][7:0] <= wdata_i[7:0]; + if (wstrb_i[1]) total_errors_io[wbs_adr_i[5:4]][15:8] <= wdata_i[15:8]; + if (wstrb_i[2]) total_errors_io[wbs_adr_i[5:4]][23:16] <= wdata_i[23:16]; + if (wstrb_i[3]) total_errors_io[wbs_adr_i[5:4]][31:24] <= wdata_i[31:24]; + end + else begin + rdata_o <= {total_errors_io[wbs_adr_i[5:4]]}; + end + end + endcase end else begin ready_o <= 1'b0;
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 1065d78..30cb808 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -25,7 +25,7 @@ `else `include "user_project_wrapper.v" `include "user_proj_example.v" - `include "controller/top_module.v" + `include "controller/main_module.v" `include "controller/status_sender_data.v" `include "controller/logic_control.v" `include "controller/control_module.v"
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 671ff2b..02a52cf 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -62,6 +62,8 @@ input [31:0] wbs_adr_i, output wbs_ack_o, output [31:0] wbs_dat_o, + // seconday clk + input user_clock2, // Logic Analyzer Signals input [127:0] la_data_in, @@ -72,13 +74,25 @@ input [`MPRJ_IO_PADS-1:0] io_in, output [`MPRJ_IO_PADS-1:0] io_out, output [`MPRJ_IO_PADS-1:0] io_oeb, + /* + *--------------------------------------------------------------------- + * If the chip is configured for output with the oeb control + * register = 1, then the oeb line is controlled by the additional + * signal from the management SoC. If the oeb control register = 0, + * then the output is disabled completely. The "io" line is input + * only in this module. + * + *--------------------------------------------------------------------- + */ // IRQ output [2:0] irq ); wire clk; wire rst; - wire [15:0] io_port; + wire [15:0] io_port_out; + wire [15:0] io_port_in; + wire [15:0] la_out_value; wire rtx; wire trx; wire [`MPRJ_IO_PADS-1:0] io_in; @@ -99,16 +113,18 @@ assign wdata = wbs_dat_i; // IO - assign io_out = {io_port,rtx,trx,20'b0}; - assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; + // IO MODE IO port connected to the 16 last + assign io_out = {io_port_out,1'bx,trx,20'b0}; + assign io_in = {io_port_in,rtx,1'bx,20'b0}; + assign io_oeb = {(`MPRJ_IO_PADS-1){1'b0}}; // IRQ //assign irq = 3'b000; // Unused // LA - //assign la_data_out = {{(127-BITS){1'b0}}, count}; + assign la_data_out = {{(127-15){1'b0}}, la_out_value}; // Assuming LA probes [63:32] are for controlling the count register - //assign la_write = ~la_oenb[63:32] & ~{BITS{valid}}; + //assign la_write = ~la_oenb[63:32] & ~{WORD_SIZE{valid}}; // Assuming LA probes [65:64] are for controlling the count clk & reset assign clk = wb_clk_i; assign rst = wb_rst_i; @@ -130,8 +146,8 @@ .clk(clk), .rtx(rtx), .rst(rst), - .input_io_ports({la_data_in[15:0],io_port}), - .output_io_ports({la_data_out[15:0],io_port}), + .input_io_ports({la_data_in[15:0],io_port_in}), + .output_io_ports({la_out_value,io_port_out}), .trx(trx), .wstrb_i(wstrb), .wdata_i(wdata), @@ -143,4 +159,5 @@ ); endmodule + `default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 5ee1cee..82a5eff 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -115,7 +115,10 @@ .io_oeb(io_oeb), // IRQ - .irq(user_irq) + .irq(user_irq), + + // independent clk + .user_clock2(user_clock2) ); endmodule // user_project_wrapper