added new instruccion set to the readme
1 file changed
tree: becfa84e516f078727f5e8a5a81fe919eaa50ce9
  1. docs/
  2. openlane/
  3. signoff/
  4. verilog/
  5. .gitignore
  6. .gitmodules
  7. clean_run.sh
  8. LICENSE
  9. make_complete.sh
  10. make_sythesys.sh
  11. Makefile
  12. README.md
  13. run_test.sh
README.md

Space Controller

License Caravel Build

Authors

  • Ivan Rodriguez-Ferrandez (UPC¹-BSC²)
  • Alvaro Jover-Alvarez (UPC¹-BSC²)
  • Leonidas Kosmidis (BSC²-UPC¹)
  • David Steenari (ESA³)
    ¹ Universitat Politècnica de Catalunya (UPC)
    ² Barcelona Supercomputing Center (BSC)
    ³ European Space Agency (ESA)

Main Version of the chip: 1.0V

Change Log

  • Version 1.0V:
    • TODO

Chip Layout

Description

How To Use The Chip

This chip uses the UART port for main communication. This communication port is use to send instructions and receive the requested output. The input is a 52 bit word for communication. In order to fill up the word the values are send one by one via the UART port. The 52 bit are divided in this well defined sections:

  • [51:48] 4 bit operation code.
  • [47:43] 5 bit primary register operation.
  • [42:0] 43 bit auxiliary values.

As commented the communication is throw the UART port, and each 4 bits are codification in hex. Because UART uses the ASCII table for the characters, the following list is the translation between the ASCII characters and the hex value interpreted by the chip:

  • 1 ➜ 1
  • 2 ➜ 2
  • 3 ➜ 3
  • 4 ➜ 4
  • 5 ➜ 5
  • 6 ➜ 6
  • 7 ➜ 7
  • 8 ➜ 8
  • 9 ➜ 9
  • : ➜ A
  • ; ➜ B
  • < ➜ C
  • = ➜ D
  • > ➜ E
  • ? ➜ F

The sended data is stored in a shift register, so in order to confirm that the command is fully sended, the ASCII character 0D (New line) needs to be send. If you want to clear the instruction sended you can send the ASCII character 20 (Space) in order to clear the shift registers.

Instruction Set

IWrite instructions

TypeDescriptionOP Code [51:49]Primary Register [48:44]Auxillary [43:0]
IWriteWrite a logic 1 in the selected register
and is maintained auxillary number of cycles
000registercycles
IWriteWaits 1 Second and writes a logic 1 in
the selected selected register and is
maintained auxillary number of cycles
001registercycles



IRead instructions

TypeDescriptionOP Code [51:49]Primary Register [48:44]Auxillary [43:0]
IReadReads the logic value in the selected register
and the read is delayed by auxiliary number of cycles
100registercycles



BWrite instructions

TypeDescriptionOP Code [51:49]Primary Register [48:44]Auxillary [43:0]
BWriteWrites 8 bit value during one clock cycle
The register and value are in the auxiliary part
011sel register 7[43:39] sel register 6
[38:34] sel register 5
[33:29] sel register 4
[28:24] sel register 3
[23:19] sel register 2
[18:13] sel register 1
[13:9] sel register 0
[8] not use
[7:0] value for the registers
BWriteWaits 1 second and writes 8 bit value during one second
The register and value are in the auxiliary part
111sel register 7[43:39] sel register 6
[38:34] sel register 5
[33:29] sel register 4
[28:24] sel register 3
[23:19] sel register 2
[18:13] sel register 1
[13:9] sel register 0
[8] not use
[7:0] value for the registers



BRead instructions

TypeDescriptionOP Code [51:49]Primary Register [48:44]Auxillary [43:0]
BRriteReads 8 bit value during one clock cycle
The register and value are in the auxiliary part
011sel register 7[43:39] sel register 6
[38:34] sel register 5
[33:29] sel register 4
[28:24] sel register 3
[23:19] sel register 2
[18:13] sel register 1
[13:9] sel register 0
[8:0] not use

Triple Redundancy Implementation

Block Description

Module Ports:

  • Input Ports
  • Output Ports

Caravel Connections

GPIO Connections

Logic Analyzer Probes

  • Input probes:

  • Output probes:

Wishbone Connection

User Maskable Interrupt Signals

Description of the Modules

Module List

Wishbone Description

Memory Map

Software Example

Available Tests