| commit | 00662c7af404e01adedcec81100546ba5e3fdf73 | [log] [tgz] |
|---|---|---|
| author | jaquerinte <ivanrodriguezferrandez@gmail.com> | Mon Dec 13 23:03:03 2021 +0100 |
| committer | jaquerinte <ivanrodriguezferrandez@gmail.com> | Mon Dec 13 23:03:03 2021 +0100 |
| tree | becfa84e516f078727f5e8a5a81fe919eaa50ce9 | |
| parent | 97b2049342064288ddc31631884383605ddccc0b [diff] |
added new instruccion set to the readme
This chip uses the UART port for main communication. This communication port is use to send instructions and receive the requested output. The input is a 52 bit word for communication. In order to fill up the word the values are send one by one via the UART port. The 52 bit are divided in this well defined sections:
As commented the communication is throw the UART port, and each 4 bits are codification in hex. Because UART uses the ASCII table for the characters, the following list is the translation between the ASCII characters and the hex value interpreted by the chip:
The sended data is stored in a shift register, so in order to confirm that the command is fully sended, the ASCII character 0D (New line) needs to be send. If you want to clear the instruction sended you can send the ASCII character 20 (Space) in order to clear the shift registers.
| Type | Description | OP Code [51:49] | Primary Register [48:44] | Auxillary [43:0] |
|---|---|---|---|---|
| IWrite | Write a logic 1 in the selected register and is maintained auxillary number of cycles | 000 | register | cycles |
| IWrite | Waits 1 Second and writes a logic 1 in the selected selected register and is maintained auxillary number of cycles | 001 | register | cycles |
| Type | Description | OP Code [51:49] | Primary Register [48:44] | Auxillary [43:0] |
|---|---|---|---|---|
| IRead | Reads the logic value in the selected register and the read is delayed by auxiliary number of cycles | 100 | register | cycles |
| Type | Description | OP Code [51:49] | Primary Register [48:44] | Auxillary [43:0] |
|---|---|---|---|---|
| BWrite | Writes 8 bit value during one clock cycle The register and value are in the auxiliary part | 011 | sel register 7 | [43:39] sel register 6 [38:34] sel register 5 [33:29] sel register 4 [28:24] sel register 3 [23:19] sel register 2 [18:13] sel register 1 [13:9] sel register 0 [8] not use [7:0] value for the registers |
| BWrite | Waits 1 second and writes 8 bit value during one second The register and value are in the auxiliary part | 111 | sel register 7 | [43:39] sel register 6 [38:34] sel register 5 [33:29] sel register 4 [28:24] sel register 3 [23:19] sel register 2 [18:13] sel register 1 [13:9] sel register 0 [8] not use [7:0] value for the registers |
| Type | Description | OP Code [51:49] | Primary Register [48:44] | Auxillary [43:0] |
|---|---|---|---|---|
| BRrite | Reads 8 bit value during one clock cycle The register and value are in the auxiliary part | 011 | sel register 7 | [43:39] sel register 6 [38:34] sel register 5 [33:29] sel register 4 [28:24] sel register 3 [23:19] sel register 2 [18:13] sel register 1 [13:9] sel register 0 [8:0] not use |
Input probes:
Output probes: