verilog/rtl/soc.v

module soc (
	sys_clk,
	sys_rst,
	io0_i,
	io0_o,
	io0_oe,
	io1_i,
	io1_o,
	io1_oe,
	io2_i,
	io2_o,
	io2_oe,
	io3_i,
	io3_o,
	io3_oe,
	io4_i,
	io4_o,
	io4_oe,
	io5_i,
	io5_o,
	io5_oe,
	io6_i,
	io6_o,
	io6_oe,
	io7_i,
	io7_o,
	io7_oe,
	io8_i,
	io8_o,
	io8_oe,
	io9_i,
	io9_o,
	io9_oe,
	io10_i,
	io10_o,
	io10_oe,
	io11_i,
	io11_o,
	io11_oe,
	io12_i,
	io12_o,
	io12_oe,
	io13_i,
	io13_o,
	io13_oe,
	io14_i,
	io14_o,
	io14_oe,
	io15_i,
	io15_o,
	io15_oe,
	io16_i,
	io16_o,
	io16_oe,
	io17_i,
	io17_o,
	io17_oe,
	io18_i,
	io18_o,
	io18_oe,
	io19_i,
	io19_o,
	io19_oe,
	uart_main_dbg_tx,
	uart_main_dbg_rx
);
	input sys_clk;
	input sys_rst;
	input io0_i;
	output reg io0_o;
	output reg io0_oe;
	input io1_i;
	output reg io1_o;
	output reg io1_oe;
	input io2_i;
	output reg io2_o;
	output reg io2_oe;
	input io3_i;
	output reg io3_o;
	output reg io3_oe;
	input io4_i;
	output reg io4_o;
	output reg io4_oe;
	input io5_i;
	output reg io5_o;
	output reg io5_oe;
	input io6_i;
	output reg io6_o;
	output reg io6_oe;
	input io7_i;
	output reg io7_o;
	output reg io7_oe;
	input io8_i;
	output reg io8_o;
	output reg io8_oe;
	input io9_i;
	output reg io9_o;
	output reg io9_oe;
	input io10_i;
	output reg io10_o;
	output reg io10_oe;
	input io11_i;
	output reg io11_o;
	output reg io11_oe;
	input io12_i;
	output reg io12_o;
	output reg io12_oe;
	input io13_i;
	output reg io13_o;
	output reg io13_oe;
	input io14_i;
	output reg io14_o;
	output reg io14_oe;
	input io15_i;
	output reg io15_o;
	output reg io15_oe;
	input io16_i;
	output reg io16_o;
	output reg io16_oe;
	input io17_i;
	output reg io17_o;
	output reg io17_oe;
	input io18_i;
	output reg io18_o;
	output reg io18_oe;
	input io19_i;
	output reg io19_o;
	output reg io19_oe;
	output uart_main_dbg_tx;
	input uart_main_dbg_rx;
	wire [31:0] pifive_debug_bus_debug_bus_adr = 32'd0;
	wire [31:0] pifive_debug_bus_debug_bus_dat_w = 32'd0;
	wire [31:0] pifive_debug_bus_debug_bus_dat_r;
	wire [3:0] pifive_debug_bus_debug_bus_sel = 4'd0;
	wire pifive_debug_bus_debug_bus_cyc = 1'd0;
	wire pifive_debug_bus_debug_bus_stb = 1'd0;
	wire pifive_debug_bus_debug_bus_ack;
	wire pifive_debug_bus_debug_bus_we = 1'd0;
	wire pifive_debug_bus_debug_bus_err;
	wire sys_clk_1;
	wire sys_rst_1;
	wire pifive0;
	wire pifive1;
	wire pifive2;
	wire pifive3;
	wire pifive4;
	wire pifive5;
	wire pifive6;
	wire pifive7;
	wire pifive8;
	wire pifive9;
	wire pifive10;
	wire pifive11;
	wire pifive12;
	wire pifive13;
	wire pifive14;
	wire pifive15;
	wire pifive_pwm0_pad;
	wire pifive_pwm1_pad;
	wire pifive_pwm2_pad;
	wire pifive_pwm3_pad;
	wire pifive_pwm4_pad;
	wire pifive_pwm5_pad;
	wire pifive16 = 1'd0;
	wire pifive17;
	wire pifive18 = 1'd0;
	wire pifive19;
	wire pifive20;
	wire pifive21;
	wire pifive22;
	wire pifive23;
	wire pifive24;
	wire pifive25;
	wire pifive26;
	wire pifive27 = 1'd0;
	wire pifive28;
	wire pifive29;
	wire pifive30 = 1'd0;
	wire pifive31;
	wire [31:0] pifive_iocontrol_bus_adr;
	wire [31:0] pifive_iocontrol_bus_dat_w;
	reg [31:0] pifive_iocontrol_bus_dat_r = 32'd0;
	wire [3:0] pifive_iocontrol_bus_sel;
	wire pifive_iocontrol_bus_cyc;
	wire pifive_iocontrol_bus_stb;
	reg pifive_iocontrol_bus_ack = 1'd0;
	wire pifive_iocontrol_bus_we;
	reg pifive_iocontrol_bus_err = 1'd0;
	wire [31:0] pifive_iocontrol_debug_bus_adr;
	wire [31:0] pifive_iocontrol_debug_bus_dat_w;
	reg [31:0] pifive_iocontrol_debug_bus_dat_r = 32'd0;
	wire [3:0] pifive_iocontrol_debug_bus_sel;
	wire pifive_iocontrol_debug_bus_cyc;
	wire pifive_iocontrol_debug_bus_stb;
	reg pifive_iocontrol_debug_bus_ack = 1'd0;
	wire pifive_iocontrol_debug_bus_we;
	reg pifive_iocontrol_debug_bus_err = 1'd0;
	reg pifive_iocontrol_irq = 1'd0;
	reg pifive_iocontrol_ff10 = 1'd0;
	reg pifive_iocontrol_ff20 = 1'd0;
	reg pifive_iocontrol_pad_i0 = 1'd0;
	reg pifive_iocontrol_last0 = 1'd0;
	wire pifive_iocontrol_gpio_in0;
	reg pifive_iocontrol_gpio_out0 = 1'd0;
	reg pifive_iocontrol_gpio_oe0 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode0 = 2'd0;
	reg [3:0] pifive_iocontrol_select0 = 4'd0;
	reg pifive_iocontrol_enable0 = 1'd0;
	reg pifive_iocontrol_ff11 = 1'd0;
	reg pifive_iocontrol_ff21 = 1'd0;
	reg pifive_iocontrol_pad_i1 = 1'd0;
	reg pifive_iocontrol_last1 = 1'd0;
	wire pifive_iocontrol_gpio_in1;
	reg pifive_iocontrol_gpio_out1 = 1'd0;
	reg pifive_iocontrol_gpio_oe1 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode1 = 2'd0;
	reg [3:0] pifive_iocontrol_select1 = 4'd0;
	reg pifive_iocontrol_enable1 = 1'd0;
	reg pifive_iocontrol_ff12 = 1'd0;
	reg pifive_iocontrol_ff22 = 1'd0;
	reg pifive_iocontrol_pad_i2 = 1'd0;
	reg pifive_iocontrol_last2 = 1'd0;
	wire pifive_iocontrol_gpio_in2;
	reg pifive_iocontrol_gpio_out2 = 1'd0;
	reg pifive_iocontrol_gpio_oe2 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode2 = 2'd0;
	reg [3:0] pifive_iocontrol_select2 = 4'd0;
	reg pifive_iocontrol_enable2 = 1'd0;
	reg pifive_iocontrol_ff13 = 1'd0;
	reg pifive_iocontrol_ff23 = 1'd0;
	reg pifive_iocontrol_pad_i3 = 1'd0;
	reg pifive_iocontrol_last3 = 1'd0;
	wire pifive_iocontrol_gpio_in3;
	reg pifive_iocontrol_gpio_out3 = 1'd0;
	reg pifive_iocontrol_gpio_oe3 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode3 = 2'd0;
	reg [3:0] pifive_iocontrol_select3 = 4'd0;
	reg pifive_iocontrol_enable3 = 1'd0;
	reg pifive_iocontrol_ff14 = 1'd0;
	reg pifive_iocontrol_ff24 = 1'd0;
	reg pifive_iocontrol_pad_i4 = 1'd0;
	reg pifive_iocontrol_last4 = 1'd0;
	wire pifive_iocontrol_gpio_in4;
	reg pifive_iocontrol_gpio_out4 = 1'd0;
	reg pifive_iocontrol_gpio_oe4 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode4 = 2'd0;
	reg [3:0] pifive_iocontrol_select4 = 4'd0;
	reg pifive_iocontrol_enable4 = 1'd0;
	reg pifive_iocontrol_ff15 = 1'd0;
	reg pifive_iocontrol_ff25 = 1'd0;
	reg pifive_iocontrol_pad_i5 = 1'd0;
	reg pifive_iocontrol_last5 = 1'd0;
	wire pifive_iocontrol_gpio_in5;
	reg pifive_iocontrol_gpio_out5 = 1'd0;
	reg pifive_iocontrol_gpio_oe5 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode5 = 2'd0;
	reg [3:0] pifive_iocontrol_select5 = 4'd0;
	reg pifive_iocontrol_enable5 = 1'd0;
	reg pifive_iocontrol_ff16 = 1'd0;
	reg pifive_iocontrol_ff26 = 1'd0;
	reg pifive_iocontrol_pad_i6 = 1'd0;
	reg pifive_iocontrol_last6 = 1'd0;
	wire pifive_iocontrol_gpio_in6;
	reg pifive_iocontrol_gpio_out6 = 1'd0;
	reg pifive_iocontrol_gpio_oe6 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode6 = 2'd0;
	reg [3:0] pifive_iocontrol_select6 = 4'd0;
	reg pifive_iocontrol_enable6 = 1'd0;
	reg pifive_iocontrol_ff17 = 1'd0;
	reg pifive_iocontrol_ff27 = 1'd0;
	reg pifive_iocontrol_pad_i7 = 1'd0;
	reg pifive_iocontrol_last7 = 1'd0;
	wire pifive_iocontrol_gpio_in7;
	reg pifive_iocontrol_gpio_out7 = 1'd0;
	reg pifive_iocontrol_gpio_oe7 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode7 = 2'd0;
	reg [3:0] pifive_iocontrol_select7 = 4'd0;
	reg pifive_iocontrol_enable7 = 1'd0;
	reg pifive_iocontrol_ff18 = 1'd0;
	reg pifive_iocontrol_ff28 = 1'd0;
	reg pifive_iocontrol_pad_i8 = 1'd0;
	reg pifive_iocontrol_last8 = 1'd0;
	wire pifive_iocontrol_gpio_in8;
	reg pifive_iocontrol_gpio_out8 = 1'd0;
	reg pifive_iocontrol_gpio_oe8 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode8 = 2'd0;
	reg [3:0] pifive_iocontrol_select8 = 4'd0;
	reg pifive_iocontrol_enable8 = 1'd0;
	reg pifive_iocontrol_ff19 = 1'd0;
	reg pifive_iocontrol_ff29 = 1'd0;
	reg pifive_iocontrol_pad_i9 = 1'd0;
	reg pifive_iocontrol_last9 = 1'd0;
	wire pifive_iocontrol_gpio_in9;
	reg pifive_iocontrol_gpio_out9 = 1'd0;
	reg pifive_iocontrol_gpio_oe9 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode9 = 2'd0;
	reg [3:0] pifive_iocontrol_select9 = 4'd0;
	reg pifive_iocontrol_enable9 = 1'd0;
	reg pifive_iocontrol_ff110 = 1'd0;
	reg pifive_iocontrol_ff210 = 1'd0;
	reg pifive_iocontrol_pad_i10 = 1'd0;
	reg pifive_iocontrol_last10 = 1'd0;
	wire pifive_iocontrol_gpio_in10;
	reg pifive_iocontrol_gpio_out10 = 1'd0;
	reg pifive_iocontrol_gpio_oe10 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode10 = 2'd0;
	reg [3:0] pifive_iocontrol_select10 = 4'd0;
	reg pifive_iocontrol_enable10 = 1'd0;
	reg pifive_iocontrol_ff111 = 1'd0;
	reg pifive_iocontrol_ff211 = 1'd0;
	reg pifive_iocontrol_pad_i11 = 1'd0;
	reg pifive_iocontrol_last11 = 1'd0;
	wire pifive_iocontrol_gpio_in11;
	reg pifive_iocontrol_gpio_out11 = 1'd0;
	reg pifive_iocontrol_gpio_oe11 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode11 = 2'd0;
	reg [3:0] pifive_iocontrol_select11 = 4'd0;
	reg pifive_iocontrol_enable11 = 1'd0;
	reg pifive_iocontrol_ff112 = 1'd0;
	reg pifive_iocontrol_ff212 = 1'd0;
	reg pifive_iocontrol_pad_i12 = 1'd0;
	reg pifive_iocontrol_last12 = 1'd0;
	wire pifive_iocontrol_gpio_in12;
	reg pifive_iocontrol_gpio_out12 = 1'd0;
	reg pifive_iocontrol_gpio_oe12 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode12 = 2'd0;
	reg [3:0] pifive_iocontrol_select12 = 4'd0;
	reg pifive_iocontrol_enable12 = 1'd0;
	reg pifive_iocontrol_ff113 = 1'd0;
	reg pifive_iocontrol_ff213 = 1'd0;
	reg pifive_iocontrol_pad_i13 = 1'd0;
	reg pifive_iocontrol_last13 = 1'd0;
	wire pifive_iocontrol_gpio_in13;
	reg pifive_iocontrol_gpio_out13 = 1'd0;
	reg pifive_iocontrol_gpio_oe13 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode13 = 2'd0;
	reg [3:0] pifive_iocontrol_select13 = 4'd0;
	reg pifive_iocontrol_enable13 = 1'd0;
	reg pifive_iocontrol_ff114 = 1'd0;
	reg pifive_iocontrol_ff214 = 1'd0;
	reg pifive_iocontrol_pad_i14 = 1'd0;
	reg pifive_iocontrol_last14 = 1'd0;
	wire pifive_iocontrol_gpio_in14;
	reg pifive_iocontrol_gpio_out14 = 1'd0;
	reg pifive_iocontrol_gpio_oe14 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode14 = 2'd0;
	reg [3:0] pifive_iocontrol_select14 = 4'd0;
	reg pifive_iocontrol_enable14 = 1'd0;
	reg pifive_iocontrol_ff115 = 1'd0;
	reg pifive_iocontrol_ff215 = 1'd0;
	reg pifive_iocontrol_pad_i15 = 1'd0;
	reg pifive_iocontrol_last15 = 1'd0;
	wire pifive_iocontrol_gpio_in15;
	reg pifive_iocontrol_gpio_out15 = 1'd0;
	reg pifive_iocontrol_gpio_oe15 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode15 = 2'd0;
	reg [3:0] pifive_iocontrol_select15 = 4'd0;
	reg pifive_iocontrol_enable15 = 1'd0;
	reg pifive_iocontrol_ff116 = 1'd0;
	reg pifive_iocontrol_ff216 = 1'd0;
	reg pifive_iocontrol_pad_i16 = 1'd0;
	reg pifive_iocontrol_last16 = 1'd0;
	wire pifive_iocontrol_gpio_in16;
	reg pifive_iocontrol_gpio_out16 = 1'd0;
	reg pifive_iocontrol_gpio_oe16 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode16 = 2'd0;
	reg [3:0] pifive_iocontrol_select16 = 4'd0;
	reg pifive_iocontrol_enable16 = 1'd0;
	reg pifive_iocontrol_ff117 = 1'd0;
	reg pifive_iocontrol_ff217 = 1'd0;
	reg pifive_iocontrol_pad_i17 = 1'd0;
	reg pifive_iocontrol_last17 = 1'd0;
	wire pifive_iocontrol_gpio_in17;
	reg pifive_iocontrol_gpio_out17 = 1'd0;
	reg pifive_iocontrol_gpio_oe17 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode17 = 2'd0;
	reg [3:0] pifive_iocontrol_select17 = 4'd0;
	reg pifive_iocontrol_enable17 = 1'd0;
	reg pifive_iocontrol_ff118 = 1'd0;
	reg pifive_iocontrol_ff218 = 1'd0;
	reg pifive_iocontrol_pad_i18 = 1'd0;
	reg pifive_iocontrol_last18 = 1'd0;
	wire pifive_iocontrol_gpio_in18;
	reg pifive_iocontrol_gpio_out18 = 1'd0;
	reg pifive_iocontrol_gpio_oe18 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode18 = 2'd0;
	reg [3:0] pifive_iocontrol_select18 = 4'd0;
	reg pifive_iocontrol_enable18 = 1'd0;
	reg pifive_iocontrol_ff119 = 1'd0;
	reg pifive_iocontrol_ff219 = 1'd0;
	reg pifive_iocontrol_pad_i19 = 1'd0;
	reg pifive_iocontrol_last19 = 1'd0;
	wire pifive_iocontrol_gpio_in19;
	reg pifive_iocontrol_gpio_out19 = 1'd0;
	reg pifive_iocontrol_gpio_oe19 = 1'd0;
	reg [1:0] pifive_iocontrol_irqmode19 = 2'd0;
	reg [3:0] pifive_iocontrol_select19 = 4'd0;
	reg pifive_iocontrol_enable19 = 1'd0;
	wire [31:0] pifive_spi0_bus_adr;
	wire [31:0] pifive_spi0_bus_dat_w;
	reg [31:0] pifive_spi0_bus_dat_r = 32'd0;
	wire [3:0] pifive_spi0_bus_sel;
	wire pifive_spi0_bus_cyc;
	wire pifive_spi0_bus_stb;
	reg pifive_spi0_bus_ack = 1'd0;
	wire pifive_spi0_bus_we;
	reg pifive_spi0_bus_err = 1'd0;
	reg pifive_spi0_irq = 1'd0;
	reg [7:0] pifive_spi0_data_out_reg = 8'd0;
	wire [7:0] pifive_spi0_data_out;
	wire pifive_spi0_data_out_valid;
	reg [7:0] pifive_spi0_data_write = 8'd0;
	reg pifive_spi0_start_write = 1'd0;
	wire pifive_spi0_ready;
	reg [1:0] pifive_spi0_mode = 2'd0;
	reg [15:0] pifive_spi0_divider = 16'd25;
	reg pifive_spi0_last_out_valid = 1'd0;
	wire [31:0] pifive_spi1_bus_adr;
	wire [31:0] pifive_spi1_bus_dat_w;
	reg [31:0] pifive_spi1_bus_dat_r = 32'd0;
	wire [3:0] pifive_spi1_bus_sel;
	wire pifive_spi1_bus_cyc;
	wire pifive_spi1_bus_stb;
	reg pifive_spi1_bus_ack = 1'd0;
	wire pifive_spi1_bus_we;
	reg pifive_spi1_bus_err = 1'd0;
	reg pifive_spi1_irq = 1'd0;
	reg [7:0] pifive_spi1_data_out_reg = 8'd0;
	wire [7:0] pifive_spi1_data_out;
	wire pifive_spi1_data_out_valid;
	reg [7:0] pifive_spi1_data_write = 8'd0;
	reg pifive_spi1_start_write = 1'd0;
	wire pifive_spi1_ready;
	reg [1:0] pifive_spi1_mode = 2'd0;
	reg [15:0] pifive_spi1_divider = 16'd25;
	reg pifive_spi1_last_out_valid = 1'd0;
	wire [31:0] pifive_uart0_bus_adr;
	wire [31:0] pifive_uart0_bus_dat_w;
	wire [31:0] pifive_uart0_bus_dat_r;
	wire [3:0] pifive_uart0_bus_sel;
	wire pifive_uart0_bus_cyc;
	wire pifive_uart0_bus_stb;
	wire pifive_uart0_bus_ack;
	wire pifive_uart0_bus_we;
	wire pifive_uart0_bus_err;
	wire [31:0] pifive_uart1_bus_adr;
	wire [31:0] pifive_uart1_bus_dat_w;
	wire [31:0] pifive_uart1_bus_dat_r;
	wire [3:0] pifive_uart1_bus_sel;
	wire pifive_uart1_bus_cyc;
	wire pifive_uart1_bus_stb;
	wire pifive_uart1_bus_ack;
	wire pifive_uart1_bus_we;
	wire pifive_uart1_bus_err;
	wire [31:0] pifive_i2c_bus_adr;
	wire [31:0] pifive_i2c_bus_dat_w;
	wire [31:0] pifive_i2c_bus_dat_r;
	wire [3:0] pifive_i2c_bus_sel;
	wire pifive_i2c_bus_cyc;
	wire pifive_i2c_bus_stb;
	wire pifive_i2c_bus_ack;
	wire pifive_i2c_bus_we;
	wire pifive_i2c_bus_err = 1'd0;
	reg pifive_i2c_last_stb = 1'd0;
	reg pifive_i2c_last_ack = 1'd0;
	wire [31:0] pifive_pwm0_bus_adr;
	wire [31:0] pifive_pwm0_bus_dat_w;
	reg [31:0] pifive_pwm0_bus_dat_r = 32'd0;
	wire [3:0] pifive_pwm0_bus_sel;
	wire pifive_pwm0_bus_cyc;
	wire pifive_pwm0_bus_stb;
	reg pifive_pwm0_bus_ack = 1'd0;
	wire pifive_pwm0_bus_we;
	reg pifive_pwm0_bus_err = 1'd0;
	reg [31:0] pifive_pwm0_ctr = 32'd0;
	reg [31:0] pifive_pwm0_width = 32'd0;
	reg [31:0] pifive_pwm0_period = 32'd0;
	wire [31:0] pifive_pwm1_bus_adr;
	wire [31:0] pifive_pwm1_bus_dat_w;
	reg [31:0] pifive_pwm1_bus_dat_r = 32'd0;
	wire [3:0] pifive_pwm1_bus_sel;
	wire pifive_pwm1_bus_cyc;
	wire pifive_pwm1_bus_stb;
	reg pifive_pwm1_bus_ack = 1'd0;
	wire pifive_pwm1_bus_we;
	reg pifive_pwm1_bus_err = 1'd0;
	reg [31:0] pifive_pwm1_ctr = 32'd0;
	reg [31:0] pifive_pwm1_width = 32'd0;
	reg [31:0] pifive_pwm1_period = 32'd0;
	wire [31:0] pifive_pwm2_bus_adr;
	wire [31:0] pifive_pwm2_bus_dat_w;
	reg [31:0] pifive_pwm2_bus_dat_r = 32'd0;
	wire [3:0] pifive_pwm2_bus_sel;
	wire pifive_pwm2_bus_cyc;
	wire pifive_pwm2_bus_stb;
	reg pifive_pwm2_bus_ack = 1'd0;
	wire pifive_pwm2_bus_we;
	reg pifive_pwm2_bus_err = 1'd0;
	reg [31:0] pifive_pwm2_ctr = 32'd0;
	reg [31:0] pifive_pwm2_width = 32'd0;
	reg [31:0] pifive_pwm2_period = 32'd0;
	wire [31:0] pifive_pwm3_bus_adr;
	wire [31:0] pifive_pwm3_bus_dat_w;
	reg [31:0] pifive_pwm3_bus_dat_r = 32'd0;
	wire [3:0] pifive_pwm3_bus_sel;
	wire pifive_pwm3_bus_cyc;
	wire pifive_pwm3_bus_stb;
	reg pifive_pwm3_bus_ack = 1'd0;
	wire pifive_pwm3_bus_we;
	reg pifive_pwm3_bus_err = 1'd0;
	reg [31:0] pifive_pwm3_ctr = 32'd0;
	reg [31:0] pifive_pwm3_width = 32'd0;
	reg [31:0] pifive_pwm3_period = 32'd0;
	wire [31:0] pifive_pwm4_bus_adr;
	wire [31:0] pifive_pwm4_bus_dat_w;
	reg [31:0] pifive_pwm4_bus_dat_r = 32'd0;
	wire [3:0] pifive_pwm4_bus_sel;
	wire pifive_pwm4_bus_cyc;
	wire pifive_pwm4_bus_stb;
	reg pifive_pwm4_bus_ack = 1'd0;
	wire pifive_pwm4_bus_we;
	reg pifive_pwm4_bus_err = 1'd0;
	reg [31:0] pifive_pwm4_ctr = 32'd0;
	reg [31:0] pifive_pwm4_width = 32'd0;
	reg [31:0] pifive_pwm4_period = 32'd0;
	wire [31:0] pifive_pwm5_bus_adr;
	wire [31:0] pifive_pwm5_bus_dat_w;
	reg [31:0] pifive_pwm5_bus_dat_r = 32'd0;
	wire [3:0] pifive_pwm5_bus_sel;
	wire pifive_pwm5_bus_cyc;
	wire pifive_pwm5_bus_stb;
	reg pifive_pwm5_bus_ack = 1'd0;
	wire pifive_pwm5_bus_we;
	reg pifive_pwm5_bus_err = 1'd0;
	reg [31:0] pifive_pwm5_ctr = 32'd0;
	reg [31:0] pifive_pwm5_width = 32'd0;
	reg [31:0] pifive_pwm5_period = 32'd0;
	wire [31:0] pifive_rom0_bus_adr;
	wire [31:0] pifive_rom0_bus_dat_w;
	reg [31:0] pifive_rom0_bus_dat_r = 32'd0;
	wire [3:0] pifive_rom0_bus_sel;
	wire pifive_rom0_bus_cyc;
	wire pifive_rom0_bus_stb;
	reg pifive_rom0_bus_ack = 1'd0;
	wire pifive_rom0_bus_we;
	wire pifive_rom0_bus_err = 1'd0;
	wire [31:0] pifive_interface0_adr0;
	wire [31:0] pifive_interface0_dat_w0;
	wire [31:0] pifive_interface0_dat_r0;
	wire [3:0] pifive_interface0_sel0;
	wire pifive_interface0_cyc0;
	wire pifive_interface0_stb0;
	reg pifive_interface0_ack0 = 1'd0;
	wire pifive_interface0_we0;
	wire pifive_interface0_err0 = 1'd0;
	wire [1:0] pifive_sram0_adr;
	wire [31:0] pifive_sram0_dat_r;
	reg [3:0] pifive_sram0_we;
	wire [31:0] pifive_sram0_dat_w;
	wire [31:0] pifive_interface1_adr0;
	wire [31:0] pifive_interface1_dat_w0;
	wire [31:0] pifive_interface1_dat_r0;
	wire [3:0] pifive_interface1_sel0;
	wire pifive_interface1_cyc0;
	wire pifive_interface1_stb0;
	reg pifive_interface1_ack0 = 1'd0;
	wire pifive_interface1_we0;
	wire pifive_interface1_err0 = 1'd0;
	wire [1:0] pifive_sram1_adr;
	wire [31:0] pifive_sram1_dat_r;
	reg [3:0] pifive_sram1_we;
	wire [31:0] pifive_sram1_dat_w;
	wire [31:0] pifive_rom1_bus_adr;
	wire [31:0] pifive_rom1_bus_dat_w;
	reg [31:0] pifive_rom1_bus_dat_r = 32'd0;
	wire [3:0] pifive_rom1_bus_sel;
	wire pifive_rom1_bus_cyc;
	wire pifive_rom1_bus_stb;
	reg pifive_rom1_bus_ack = 1'd0;
	wire pifive_rom1_bus_we;
	wire pifive_rom1_bus_err = 1'd0;
	wire [31:0] pifive_uptimetimer_bus_adr;
	wire [31:0] pifive_uptimetimer_bus_dat_w;
	reg [31:0] pifive_uptimetimer_bus_dat_r = 32'd0;
	wire [3:0] pifive_uptimetimer_bus_sel;
	wire pifive_uptimetimer_bus_cyc;
	wire pifive_uptimetimer_bus_stb;
	reg pifive_uptimetimer_bus_ack = 1'd0;
	wire pifive_uptimetimer_bus_we;
	reg pifive_uptimetimer_bus_err = 1'd0;
	reg [63:0] pifive_uptimetimer_ctr = 64'd0;
	reg pifive_timer0_irq = 1'd0;
	wire [31:0] pifive_timer0_bus_adr;
	wire [31:0] pifive_timer0_bus_dat_w;
	reg [31:0] pifive_timer0_bus_dat_r = 32'd0;
	wire [3:0] pifive_timer0_bus_sel;
	wire pifive_timer0_bus_cyc;
	wire pifive_timer0_bus_stb;
	reg pifive_timer0_bus_ack = 1'd0;
	wire pifive_timer0_bus_we;
	reg pifive_timer0_bus_err = 1'd0;
	reg [31:0] pifive_timer0_ctr = 32'd0;
	reg pifive_timer0_running = 1'd0;
	reg pifive_timer0_triggered = 1'd0;
	reg [31:0] pifive_timer0_reload = 32'd0;
	reg [31:0] pifive_timer0_load = 32'd0;
	reg pifive_timer1_irq = 1'd0;
	wire [31:0] pifive_timer1_bus_adr;
	wire [31:0] pifive_timer1_bus_dat_w;
	reg [31:0] pifive_timer1_bus_dat_r = 32'd0;
	wire [3:0] pifive_timer1_bus_sel;
	wire pifive_timer1_bus_cyc;
	wire pifive_timer1_bus_stb;
	reg pifive_timer1_bus_ack = 1'd0;
	wire pifive_timer1_bus_we;
	reg pifive_timer1_bus_err = 1'd0;
	reg [31:0] pifive_timer1_ctr = 32'd0;
	reg pifive_timer1_running = 1'd0;
	reg pifive_timer1_triggered = 1'd0;
	reg [31:0] pifive_timer1_reload = 32'd0;
	reg [31:0] pifive_timer1_load = 32'd0;
	wire [31:0] pifive_wishbonedebugbus_bus_adr;
	wire [31:0] pifive_wishbonedebugbus_bus_dat_w;
	wire [31:0] pifive_wishbonedebugbus_bus_dat_r;
	reg [3:0] pifive_wishbonedebugbus_bus_sel = 4'd0;
	wire pifive_wishbonedebugbus_bus_cyc;
	wire pifive_wishbonedebugbus_bus_stb;
	wire pifive_wishbonedebugbus_bus_ack;
	wire pifive_wishbonedebugbus_bus_we;
	wire pifive_wishbonedebugbus_bus_err;
	reg [15:0] pifive_wishbonedebugbus_ctr = 16'd0;
	reg pifive_wishbonedebugbus_last_stb = 1'd0;
	wire [31:0] pifive_instr_bus_adr;
	wire [31:0] pifive_instr_bus_dat_w;
	wire [31:0] pifive_instr_bus_dat_r;
	wire [3:0] pifive_instr_bus_sel;
	wire pifive_instr_bus_cyc;
	wire pifive_instr_bus_stb;
	wire pifive_instr_bus_ack;
	wire pifive_instr_bus_we;
	wire pifive_instr_bus_err;
	wire [31:0] pifive_data_bus_adr;
	wire [31:0] pifive_data_bus_dat_w;
	wire [31:0] pifive_data_bus_dat_r;
	wire [3:0] pifive_data_bus_sel;
	wire pifive_data_bus_cyc;
	wire pifive_data_bus_stb;
	wire pifive_data_bus_ack;
	wire pifive_data_bus_we;
	wire pifive_data_bus_err;
	wire pifive_stall_in = 1'd0;
	wire pifive_stall_out;
	wire [31:0] pifive_init_pc;
	wire [31:0] pifive_pc_out;
	wire pifive_cpu_reset;
	wire [31:0] pifive_interface0_controller_bus_adr;
	wire [31:0] pifive_interface0_controller_bus_dat_w;
	wire [31:0] pifive_interface0_controller_bus_dat_r;
	wire [3:0] pifive_interface0_controller_bus_sel;
	wire pifive_interface0_controller_bus_cyc;
	wire pifive_interface0_controller_bus_stb;
	wire pifive_interface0_controller_bus_ack;
	wire pifive_interface0_controller_bus_we;
	wire pifive_interface0_controller_bus_err;
	wire [31:0] pifive_interface1_controller_bus_adr;
	wire [31:0] pifive_interface1_controller_bus_dat_w;
	wire [31:0] pifive_interface1_controller_bus_dat_r;
	wire [3:0] pifive_interface1_controller_bus_sel;
	wire pifive_interface1_controller_bus_cyc;
	wire pifive_interface1_controller_bus_stb;
	wire pifive_interface1_controller_bus_ack;
	wire pifive_interface1_controller_bus_we;
	wire pifive_interface1_controller_bus_err;
	wire [31:0] pifive_interface2_controller_bus_adr;
	wire [31:0] pifive_interface2_controller_bus_dat_w;
	wire [31:0] pifive_interface2_controller_bus_dat_r;
	wire [3:0] pifive_interface2_controller_bus_sel;
	wire pifive_interface2_controller_bus_cyc;
	wire pifive_interface2_controller_bus_stb;
	wire pifive_interface2_controller_bus_ack;
	wire pifive_interface2_controller_bus_we;
	wire pifive_interface2_controller_bus_err;
	wire [31:0] pifive_interface3_controller_bus_adr;
	wire [31:0] pifive_interface3_controller_bus_dat_w;
	wire [31:0] pifive_interface3_controller_bus_dat_r;
	wire [3:0] pifive_interface3_controller_bus_sel;
	wire pifive_interface3_controller_bus_cyc;
	wire pifive_interface3_controller_bus_stb;
	wire pifive_interface3_controller_bus_ack;
	wire pifive_interface3_controller_bus_we;
	wire pifive_interface3_controller_bus_err;
	wire [31:0] pifive_interface4_controller_bus_adr;
	wire [31:0] pifive_interface4_controller_bus_dat_w;
	wire [31:0] pifive_interface4_controller_bus_dat_r;
	wire [3:0] pifive_interface4_controller_bus_sel;
	wire pifive_interface4_controller_bus_cyc;
	wire pifive_interface4_controller_bus_stb;
	wire pifive_interface4_controller_bus_ack;
	wire pifive_interface4_controller_bus_we;
	wire pifive_interface4_controller_bus_err;
	wire [31:0] pifive_interface5_controller_bus_adr;
	wire [31:0] pifive_interface5_controller_bus_dat_w;
	wire [31:0] pifive_interface5_controller_bus_dat_r;
	wire [3:0] pifive_interface5_controller_bus_sel;
	wire pifive_interface5_controller_bus_cyc;
	wire pifive_interface5_controller_bus_stb;
	wire pifive_interface5_controller_bus_ack;
	wire pifive_interface5_controller_bus_we;
	wire pifive_interface5_controller_bus_err;
	wire [31:0] pifive_interface6_controller_bus_adr;
	wire [31:0] pifive_interface6_controller_bus_dat_w;
	wire [31:0] pifive_interface6_controller_bus_dat_r;
	wire [3:0] pifive_interface6_controller_bus_sel;
	wire pifive_interface6_controller_bus_cyc;
	wire pifive_interface6_controller_bus_stb;
	wire pifive_interface6_controller_bus_ack;
	wire pifive_interface6_controller_bus_we;
	wire pifive_interface6_controller_bus_err;
	wire [31:0] pifive_interface7_controller_bus_adr;
	wire [31:0] pifive_interface7_controller_bus_dat_w;
	wire [31:0] pifive_interface7_controller_bus_dat_r;
	wire [3:0] pifive_interface7_controller_bus_sel;
	wire pifive_interface7_controller_bus_cyc;
	wire pifive_interface7_controller_bus_stb;
	wire pifive_interface7_controller_bus_ack;
	wire pifive_interface7_controller_bus_we;
	wire pifive_interface7_controller_bus_err;
	wire [31:0] pifive_interface8_controller_bus_adr;
	wire [31:0] pifive_interface8_controller_bus_dat_w;
	wire [31:0] pifive_interface8_controller_bus_dat_r;
	wire [3:0] pifive_interface8_controller_bus_sel;
	wire pifive_interface8_controller_bus_cyc;
	wire pifive_interface8_controller_bus_stb;
	wire pifive_interface8_controller_bus_ack;
	wire pifive_interface8_controller_bus_we;
	wire pifive_interface8_controller_bus_err;
	wire [31:0] pifive_interface9_controller_bus_adr;
	wire [31:0] pifive_interface9_controller_bus_dat_w;
	wire [31:0] pifive_interface9_controller_bus_dat_r;
	wire [3:0] pifive_interface9_controller_bus_sel;
	wire pifive_interface9_controller_bus_cyc;
	wire pifive_interface9_controller_bus_stb;
	wire pifive_interface9_controller_bus_ack;
	wire pifive_interface9_controller_bus_we;
	wire pifive_interface9_controller_bus_err;
	wire [31:0] pifive_interface10_controller_bus_adr;
	wire [31:0] pifive_interface10_controller_bus_dat_w;
	wire [31:0] pifive_interface10_controller_bus_dat_r;
	wire [3:0] pifive_interface10_controller_bus_sel;
	wire pifive_interface10_controller_bus_cyc;
	wire pifive_interface10_controller_bus_stb;
	wire pifive_interface10_controller_bus_ack;
	wire pifive_interface10_controller_bus_we;
	wire pifive_interface10_controller_bus_err;
	wire [31:0] pifive_interface11_controller_bus_adr;
	wire [31:0] pifive_interface11_controller_bus_dat_w;
	wire [31:0] pifive_interface11_controller_bus_dat_r;
	wire [3:0] pifive_interface11_controller_bus_sel;
	wire pifive_interface11_controller_bus_cyc;
	wire pifive_interface11_controller_bus_stb;
	wire pifive_interface11_controller_bus_ack;
	wire pifive_interface11_controller_bus_we;
	wire pifive_interface11_controller_bus_err;
	wire [31:0] pifive_interface12_controller_bus_adr;
	wire [31:0] pifive_interface12_controller_bus_dat_w;
	wire [31:0] pifive_interface12_controller_bus_dat_r;
	wire [3:0] pifive_interface12_controller_bus_sel;
	wire pifive_interface12_controller_bus_cyc;
	wire pifive_interface12_controller_bus_stb;
	wire pifive_interface12_controller_bus_ack;
	wire pifive_interface12_controller_bus_we;
	wire pifive_interface12_controller_bus_err;
	wire [31:0] pifive_interface13_controller_bus_adr;
	wire [31:0] pifive_interface13_controller_bus_dat_w;
	wire [31:0] pifive_interface13_controller_bus_dat_r;
	wire [3:0] pifive_interface13_controller_bus_sel;
	wire pifive_interface13_controller_bus_cyc;
	wire pifive_interface13_controller_bus_stb;
	wire pifive_interface13_controller_bus_ack;
	wire pifive_interface13_controller_bus_we;
	wire pifive_interface13_controller_bus_err;
	wire [31:0] pifive_interface14_controller_bus_adr;
	wire [31:0] pifive_interface14_controller_bus_dat_w;
	wire [31:0] pifive_interface14_controller_bus_dat_r;
	wire [3:0] pifive_interface14_controller_bus_sel;
	wire pifive_interface14_controller_bus_cyc;
	wire pifive_interface14_controller_bus_stb;
	wire pifive_interface14_controller_bus_ack;
	wire pifive_interface14_controller_bus_we;
	wire pifive_interface14_controller_bus_err;
	wire [31:0] pifive_interface15_controller_bus_adr;
	wire [31:0] pifive_interface15_controller_bus_dat_w;
	wire [31:0] pifive_interface15_controller_bus_dat_r;
	wire [3:0] pifive_interface15_controller_bus_sel;
	wire pifive_interface15_controller_bus_cyc;
	wire pifive_interface15_controller_bus_stb;
	wire pifive_interface15_controller_bus_ack;
	wire pifive_interface15_controller_bus_we;
	wire pifive_interface15_controller_bus_err;
	wire [31:0] pifive_interface16_controller_bus_adr;
	wire [31:0] pifive_interface16_controller_bus_dat_w;
	wire [31:0] pifive_interface16_controller_bus_dat_r;
	wire [3:0] pifive_interface16_controller_bus_sel;
	wire pifive_interface16_controller_bus_cyc;
	wire pifive_interface16_controller_bus_stb;
	wire pifive_interface16_controller_bus_ack;
	wire pifive_interface16_controller_bus_we;
	wire pifive_interface16_controller_bus_err;
	wire [31:0] pifive_shared_adr;
	wire [31:0] pifive_shared_dat_w;
	wire [31:0] pifive_shared_dat_r;
	wire [3:0] pifive_shared_sel;
	wire pifive_shared_cyc;
	wire pifive_shared_stb;
	wire pifive_shared_ack;
	wire pifive_shared_we;
	wire pifive_shared_err;
	reg [16:0] pifive_periph_bridge_slave_sel;
	reg [16:0] pifive_periph_bridge_slave_sel_r = 17'd0;
	wire [31:0] pifive_interface17_controller_bus_adr;
	wire [31:0] pifive_interface17_controller_bus_dat_w;
	wire [31:0] pifive_interface17_controller_bus_dat_r;
	wire [3:0] pifive_interface17_controller_bus_sel;
	wire pifive_interface17_controller_bus_cyc;
	wire pifive_interface17_controller_bus_stb;
	wire pifive_interface17_controller_bus_ack;
	wire pifive_interface17_controller_bus_we;
	wire pifive_interface17_controller_bus_err;
	wire [31:0] pifive_interface18_controller_bus_adr;
	wire [31:0] pifive_interface18_controller_bus_dat_w;
	wire [31:0] pifive_interface18_controller_bus_dat_r;
	wire [3:0] pifive_interface18_controller_bus_sel;
	wire pifive_interface18_controller_bus_cyc;
	wire pifive_interface18_controller_bus_stb;
	wire pifive_interface18_controller_bus_ack;
	wire pifive_interface18_controller_bus_we;
	wire pifive_interface18_controller_bus_err;
	wire [31:0] pifive_interface19_controller_bus_adr;
	wire [31:0] pifive_interface19_controller_bus_dat_w;
	wire [31:0] pifive_interface19_controller_bus_dat_r;
	wire [3:0] pifive_interface19_controller_bus_sel;
	wire pifive_interface19_controller_bus_cyc;
	wire pifive_interface19_controller_bus_stb;
	wire pifive_interface19_controller_bus_ack;
	wire pifive_interface19_controller_bus_we;
	wire pifive_interface19_controller_bus_err;
	wire [31:0] pifive_interface0_adr1;
	wire [31:0] pifive_interface0_dat_w1;
	wire [31:0] pifive_interface0_dat_r1;
	wire [3:0] pifive_interface0_sel1;
	wire pifive_interface0_cyc1;
	wire pifive_interface0_stb1;
	wire pifive_interface0_ack1;
	wire pifive_interface0_we1;
	wire pifive_interface0_err1;
	wire [31:0] pifive_interface1_adr1;
	wire [31:0] pifive_interface1_dat_w1;
	wire [31:0] pifive_interface1_dat_r1;
	wire [3:0] pifive_interface1_sel1;
	wire pifive_interface1_cyc1;
	wire pifive_interface1_stb1;
	wire pifive_interface1_ack1;
	wire pifive_interface1_we1;
	wire pifive_interface1_err1;
	wire [31:0] pifive_interface2_adr;
	wire [31:0] pifive_interface2_dat_w;
	wire [31:0] pifive_interface2_dat_r;
	wire [3:0] pifive_interface2_sel;
	wire pifive_interface2_cyc;
	wire pifive_interface2_stb;
	wire pifive_interface2_ack;
	wire pifive_interface2_we;
	wire pifive_interface2_err;
	wire [31:0] pifive_interface3_adr;
	wire [31:0] pifive_interface3_dat_w;
	wire [31:0] pifive_interface3_dat_r;
	wire [3:0] pifive_interface3_sel;
	wire pifive_interface3_cyc;
	wire pifive_interface3_stb;
	wire pifive_interface3_ack;
	wire pifive_interface3_we;
	wire pifive_interface3_err;
	wire [31:0] pifive_interface4_adr;
	wire [31:0] pifive_interface4_dat_w;
	wire [31:0] pifive_interface4_dat_r;
	wire [3:0] pifive_interface4_sel;
	wire pifive_interface4_cyc;
	wire pifive_interface4_stb;
	wire pifive_interface4_ack;
	wire pifive_interface4_we;
	wire pifive_interface4_err;
	wire [31:0] pifive_interface5_adr;
	wire [31:0] pifive_interface5_dat_w;
	wire [31:0] pifive_interface5_dat_r;
	wire [3:0] pifive_interface5_sel;
	wire pifive_interface5_cyc;
	wire pifive_interface5_stb;
	wire pifive_interface5_ack;
	wire pifive_interface5_we;
	wire pifive_interface5_err;
	wire [31:0] pifive_interface6_adr;
	wire [31:0] pifive_interface6_dat_w;
	wire [31:0] pifive_interface6_dat_r;
	wire [3:0] pifive_interface6_sel;
	wire pifive_interface6_cyc;
	wire pifive_interface6_stb;
	wire pifive_interface6_ack;
	wire pifive_interface6_we;
	wire pifive_interface6_err;
	wire [31:0] pifive_interface7_adr;
	wire [31:0] pifive_interface7_dat_w;
	wire [31:0] pifive_interface7_dat_r;
	wire [3:0] pifive_interface7_sel;
	wire pifive_interface7_cyc;
	wire pifive_interface7_stb;
	wire pifive_interface7_ack;
	wire pifive_interface7_we;
	wire pifive_interface7_err;
	wire [31:0] pifive_interface8_adr;
	wire [31:0] pifive_interface8_dat_w;
	wire [31:0] pifive_interface8_dat_r;
	wire [3:0] pifive_interface8_sel;
	wire pifive_interface8_cyc;
	wire pifive_interface8_stb;
	wire pifive_interface8_ack;
	wire pifive_interface8_we;
	wire pifive_interface8_err;
	reg [2:0] pifive_decoder0_slave_sel;
	wire [2:0] pifive_decoder0_slave_sel_r;
	reg [2:0] pifive_decoder1_slave_sel;
	wire [2:0] pifive_decoder1_slave_sel_r;
	reg [2:0] pifive_decoder2_slave_sel;
	wire [2:0] pifive_decoder2_slave_sel_r;
	wire [2:0] pifive_arbiter0_request;
	reg [1:0] pifive_arbiter0_grant = 2'd0;
	wire [2:0] pifive_arbiter1_request;
	reg [1:0] pifive_arbiter1_grant = 2'd0;
	wire [2:0] pifive_arbiter2_request;
	reg [1:0] pifive_arbiter2_grant = 2'd0;
	wire [31:0] pifive_interface20_controller_bus_adr;
	wire [31:0] pifive_interface20_controller_bus_dat_w;
	wire [31:0] pifive_interface20_controller_bus_dat_r;
	wire [3:0] pifive_interface20_controller_bus_sel;
	wire pifive_interface20_controller_bus_cyc;
	wire pifive_interface20_controller_bus_stb;
	wire pifive_interface20_controller_bus_ack;
	wire pifive_interface20_controller_bus_we;
	wire pifive_interface20_controller_bus_err;
	wire pifive_debug_interconnect_slave_sel;
	reg pifive_debug_interconnect_slave_sel_r = 1'd0;
	wire [32:0] slice_proxy0;
	wire [32:0] slice_proxy1;
	wire [32:0] slice_proxy2;
	wire [32:0] slice_proxy3;
	wire [32:0] slice_proxy4;
	wire [32:0] slice_proxy5;
	wire [32:0] slice_proxy6;
	wire [32:0] slice_proxy7;
	wire [32:0] slice_proxy8;
	wire [32:0] slice_proxy9;
	wire [32:0] slice_proxy10;
	wire [32:0] slice_proxy11;
	wire [32:0] slice_proxy12;
	wire [32:0] slice_proxy13;
	wire [32:0] slice_proxy14;
	wire [32:0] slice_proxy15;
	wire [32:0] slice_proxy16;
	wire [32:0] slice_proxy17;
	wire [32:0] slice_proxy18;
	wire [32:0] slice_proxy19;
	reg [31:0] comb_array_muxed0;
	reg [31:0] comb_array_muxed1;
	reg [3:0] comb_array_muxed2;
	reg comb_array_muxed3;
	reg comb_array_muxed4;
	reg comb_array_muxed5;
	reg [31:0] comb_array_muxed6;
	reg [31:0] comb_array_muxed7;
	reg [3:0] comb_array_muxed8;
	reg comb_array_muxed9;
	reg comb_array_muxed10;
	reg comb_array_muxed11;
	reg [31:0] comb_array_muxed12;
	reg [31:0] comb_array_muxed13;
	reg [3:0] comb_array_muxed14;
	reg comb_array_muxed15;
	reg comb_array_muxed16;
	reg comb_array_muxed17;
	reg [31:0] sync_array_muxed0;
	reg [30:0] sync_array_muxed1;
	reg dummy_s;
	initial dummy_s <= 1'd0;
	assign pifive_init_pc = 1'd0;
	assign pifive_cpu_reset = 1'd0;
	assign sys_clk_1 = sys_clk;
	assign sys_rst_1 = sys_rst;
	assign pifive_iocontrol_gpio_in0 = pifive_iocontrol_pad_i0;
	assign pifive6 = pifive_iocontrol_pad_i0;
	reg dummy_d;
	always @(*) begin
		io0_o <= 1'd0;
		io0_oe <= 1'd0;
		if (~pifive_iocontrol_enable0) begin
			io0_oe <= 1'd0;
			io0_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select0)
				1'd1: begin
					io0_o <= pifive16;
					io0_oe <= 1'd0;
				end
				default: begin
					io0_o <= pifive_iocontrol_gpio_out0;
					io0_oe <= pifive_iocontrol_gpio_oe0;
				end
			endcase
		dummy_d <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in1 = pifive_iocontrol_pad_i1;
	assign pifive17 = pifive_iocontrol_pad_i1;
	reg dummy_d_1;
	always @(*) begin
		io1_o <= 1'd0;
		io1_oe <= 1'd0;
		if (~pifive_iocontrol_enable1) begin
			io1_oe <= 1'd0;
			io1_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select1)
				1'd1: begin
					io1_o <= pifive7;
					io1_oe <= 1'd1;
				end
				default: begin
					io1_o <= pifive_iocontrol_gpio_out1;
					io1_oe <= pifive_iocontrol_gpio_oe1;
				end
			endcase
		dummy_d_1 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in2 = pifive_iocontrol_pad_i2;
	assign pifive8 = pifive_iocontrol_pad_i2;
	reg dummy_d_2;
	always @(*) begin
		io2_o <= 1'd0;
		io2_oe <= 1'd0;
		if (~pifive_iocontrol_enable2) begin
			io2_oe <= 1'd0;
			io2_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select2)
				1'd1: begin
					io2_o <= pifive18;
					io2_oe <= 1'd0;
				end
				default: begin
					io2_o <= pifive_iocontrol_gpio_out2;
					io2_oe <= pifive_iocontrol_gpio_oe2;
				end
			endcase
		dummy_d_2 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in3 = pifive_iocontrol_pad_i3;
	assign pifive19 = pifive_iocontrol_pad_i3;
	reg dummy_d_3;
	always @(*) begin
		io3_o <= 1'd0;
		io3_oe <= 1'd0;
		if (~pifive_iocontrol_enable3) begin
			io3_oe <= 1'd0;
			io3_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select3)
				1'd1: begin
					io3_o <= pifive9;
					io3_oe <= 1'd1;
				end
				default: begin
					io3_o <= pifive_iocontrol_gpio_out3;
					io3_oe <= pifive_iocontrol_gpio_oe3;
				end
			endcase
		dummy_d_3 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in4 = pifive_iocontrol_pad_i4;
	assign pifive20 = pifive_iocontrol_pad_i4;
	reg dummy_d_4;
	always @(*) begin
		io4_o <= 1'd0;
		io4_oe <= 1'd0;
		if (~pifive_iocontrol_enable4) begin
			io4_oe <= 1'd0;
			io4_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select4)
				1'd1: begin
					io4_o <= pifive_pwm0_pad;
					io4_oe <= 1'd1;
				end
				default: begin
					io4_o <= pifive_iocontrol_gpio_out4;
					io4_oe <= pifive_iocontrol_gpio_oe4;
				end
			endcase
		dummy_d_4 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in5 = pifive_iocontrol_pad_i5;
	assign pifive21 = pifive_iocontrol_pad_i5;
	reg dummy_d_5;
	always @(*) begin
		io5_o <= 1'd0;
		io5_oe <= 1'd0;
		if (~pifive_iocontrol_enable5) begin
			io5_oe <= 1'd0;
			io5_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select5)
				1'd1: begin
					io5_o <= pifive_pwm1_pad;
					io5_oe <= 1'd1;
				end
				default: begin
					io5_o <= pifive_iocontrol_gpio_out5;
					io5_oe <= pifive_iocontrol_gpio_oe5;
				end
			endcase
		dummy_d_5 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in6 = pifive_iocontrol_pad_i6;
	assign pifive22 = pifive_iocontrol_pad_i6;
	reg dummy_d_6;
	always @(*) begin
		io6_o <= 1'd0;
		io6_oe <= 1'd0;
		if (~pifive_iocontrol_enable6) begin
			io6_oe <= 1'd0;
			io6_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select6)
				1'd1: begin
					io6_o <= pifive_pwm2_pad;
					io6_oe <= 1'd1;
				end
				default: begin
					io6_o <= pifive_iocontrol_gpio_out6;
					io6_oe <= pifive_iocontrol_gpio_oe6;
				end
			endcase
		dummy_d_6 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in7 = pifive_iocontrol_pad_i7;
	assign pifive23 = pifive_iocontrol_pad_i7;
	reg dummy_d_7;
	always @(*) begin
		io7_o <= 1'd0;
		io7_oe <= 1'd0;
		if (~pifive_iocontrol_enable7) begin
			io7_oe <= 1'd0;
			io7_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select7)
				1'd1: begin
					io7_o <= pifive_pwm3_pad;
					io7_oe <= 1'd1;
				end
				default: begin
					io7_o <= pifive_iocontrol_gpio_out7;
					io7_oe <= pifive_iocontrol_gpio_oe7;
				end
			endcase
		dummy_d_7 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in8 = pifive_iocontrol_pad_i8;
	assign pifive24 = pifive_iocontrol_pad_i8;
	reg dummy_d_8;
	always @(*) begin
		io8_o <= 1'd0;
		io8_oe <= 1'd0;
		if (~pifive_iocontrol_enable8) begin
			io8_oe <= 1'd0;
			io8_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select8)
				1'd1: begin
					io8_o <= pifive_pwm4_pad;
					io8_oe <= 1'd1;
				end
				default: begin
					io8_o <= pifive_iocontrol_gpio_out8;
					io8_oe <= pifive_iocontrol_gpio_oe8;
				end
			endcase
		dummy_d_8 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in9 = pifive_iocontrol_pad_i9;
	assign pifive25 = pifive_iocontrol_pad_i9;
	reg dummy_d_9;
	always @(*) begin
		io9_o <= 1'd0;
		io9_oe <= 1'd0;
		if (~pifive_iocontrol_enable9) begin
			io9_oe <= 1'd0;
			io9_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select9)
				1'd1: begin
					io9_o <= pifive_pwm5_pad;
					io9_oe <= 1'd1;
				end
				default: begin
					io9_o <= pifive_iocontrol_gpio_out9;
					io9_oe <= pifive_iocontrol_gpio_oe9;
				end
			endcase
		dummy_d_9 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in10 = pifive_iocontrol_pad_i10;
	reg dummy_d_10;
	always @(*) begin
		io10_o <= 1'd0;
		io10_oe <= 1'd0;
		if (~pifive_iocontrol_enable10) begin
			io10_oe <= 1'd0;
			io10_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select10)
				default: begin
					io10_o <= pifive_iocontrol_gpio_out10;
					io10_oe <= pifive_iocontrol_gpio_oe10;
				end
			endcase
		dummy_d_10 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in11 = pifive_iocontrol_pad_i11;
	assign pifive26 = pifive_iocontrol_pad_i11;
	reg dummy_d_11;
	always @(*) begin
		io11_o <= 1'd0;
		io11_oe <= 1'd0;
		if (~pifive_iocontrol_enable11) begin
			io11_oe <= 1'd0;
			io11_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select11)
				1'd1: begin
					io11_o <= pifive0;
					io11_oe <= 1'd1;
				end
				default: begin
					io11_o <= pifive_iocontrol_gpio_out11;
					io11_oe <= pifive_iocontrol_gpio_oe11;
				end
			endcase
		dummy_d_11 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in12 = pifive_iocontrol_pad_i12;
	assign pifive1 = pifive_iocontrol_pad_i12;
	reg dummy_d_12;
	always @(*) begin
		io12_o <= 1'd0;
		io12_oe <= 1'd0;
		if (~pifive_iocontrol_enable12) begin
			io12_oe <= 1'd0;
			io12_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select12)
				1'd1: begin
					io12_o <= pifive27;
					io12_oe <= 1'd0;
				end
				default: begin
					io12_o <= pifive_iocontrol_gpio_out12;
					io12_oe <= pifive_iocontrol_gpio_oe12;
				end
			endcase
		dummy_d_12 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in13 = pifive_iocontrol_pad_i13;
	assign pifive28 = pifive_iocontrol_pad_i13;
	reg dummy_d_13;
	always @(*) begin
		io13_o <= 1'd0;
		io13_oe <= 1'd0;
		if (~pifive_iocontrol_enable13) begin
			io13_oe <= 1'd0;
			io13_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select13)
				1'd1: begin
					io13_o <= pifive2;
					io13_oe <= 1'd1;
				end
				default: begin
					io13_o <= pifive_iocontrol_gpio_out13;
					io13_oe <= pifive_iocontrol_gpio_oe13;
				end
			endcase
		dummy_d_13 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in14 = pifive_iocontrol_pad_i14;
	assign pifive29 = pifive_iocontrol_pad_i14;
	reg dummy_d_14;
	always @(*) begin
		io14_o <= 1'd0;
		io14_oe <= 1'd0;
		if (~pifive_iocontrol_enable14) begin
			io14_oe <= 1'd0;
			io14_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select14)
				1'd1: begin
					io14_o <= pifive3;
					io14_oe <= 1'd1;
				end
				default: begin
					io14_o <= pifive_iocontrol_gpio_out14;
					io14_oe <= pifive_iocontrol_gpio_oe14;
				end
			endcase
		dummy_d_14 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in15 = pifive_iocontrol_pad_i15;
	assign pifive4 = pifive_iocontrol_pad_i15;
	reg dummy_d_15;
	always @(*) begin
		io15_o <= 1'd0;
		io15_oe <= 1'd0;
		if (~pifive_iocontrol_enable15) begin
			io15_oe <= 1'd0;
			io15_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select15)
				1'd1: begin
					io15_o <= pifive30;
					io15_oe <= 1'd0;
				end
				default: begin
					io15_o <= pifive_iocontrol_gpio_out15;
					io15_oe <= pifive_iocontrol_gpio_oe15;
				end
			endcase
		dummy_d_15 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in16 = pifive_iocontrol_pad_i16;
	assign pifive31 = pifive_iocontrol_pad_i16;
	reg dummy_d_16;
	always @(*) begin
		io16_o <= 1'd0;
		io16_oe <= 1'd0;
		if (~pifive_iocontrol_enable16) begin
			io16_oe <= 1'd0;
			io16_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select16)
				1'd1: begin
					io16_o <= pifive5;
					io16_oe <= 1'd1;
				end
				default: begin
					io16_o <= pifive_iocontrol_gpio_out16;
					io16_oe <= pifive_iocontrol_gpio_oe16;
				end
			endcase
		dummy_d_16 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in17 = pifive_iocontrol_pad_i17;
	reg dummy_d_17;
	always @(*) begin
		io17_o <= 1'd0;
		io17_oe <= 1'd0;
		if (~pifive_iocontrol_enable17) begin
			io17_oe <= 1'd0;
			io17_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select17)
				default: begin
					io17_o <= pifive_iocontrol_gpio_out17;
					io17_oe <= pifive_iocontrol_gpio_oe17;
				end
			endcase
		dummy_d_17 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in18 = pifive_iocontrol_pad_i18;
	assign pifive10 = pifive_iocontrol_pad_i18;
	reg dummy_d_18;
	always @(*) begin
		io18_o <= 1'd0;
		io18_oe <= 1'd0;
		if (~pifive_iocontrol_enable18) begin
			io18_oe <= 1'd0;
			io18_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select18)
				1'd1: begin
					io18_o <= 1'd0;
					io18_oe <= pifive11 == 1'd0;
				end
				default: begin
					io18_o <= pifive_iocontrol_gpio_out18;
					io18_oe <= pifive_iocontrol_gpio_oe18;
				end
			endcase
		dummy_d_18 <= dummy_s;
	end
	assign pifive_iocontrol_gpio_in19 = pifive_iocontrol_pad_i19;
	assign pifive13 = pifive_iocontrol_pad_i19;
	reg dummy_d_19;
	always @(*) begin
		io19_o <= 1'd0;
		io19_oe <= 1'd0;
		if (~pifive_iocontrol_enable19) begin
			io19_oe <= 1'd0;
			io19_o <= 1'd0;
		end
		else
			case (pifive_iocontrol_select19)
				1'd1: begin
					io19_o <= 1'd0;
					io19_oe <= pifive14 == 1'd0;
				end
				default: begin
					io19_o <= pifive_iocontrol_gpio_out19;
					io19_oe <= pifive_iocontrol_gpio_oe19;
				end
			endcase
		dummy_d_19 <= dummy_s;
	end
	assign pifive_pwm0_pad = pifive_pwm0_ctr < pifive_pwm0_width;
	assign pifive_pwm1_pad = pifive_pwm1_ctr < pifive_pwm1_width;
	assign pifive_pwm2_pad = pifive_pwm2_ctr < pifive_pwm2_width;
	assign pifive_pwm3_pad = pifive_pwm3_ctr < pifive_pwm3_width;
	assign pifive_pwm4_pad = pifive_pwm4_ctr < pifive_pwm4_width;
	assign pifive_pwm5_pad = pifive_pwm5_ctr < pifive_pwm5_width;
	reg dummy_d_20;
	always @(*) begin
		pifive_sram0_we <= 4'd0;
		pifive_sram0_we[0] <= ((pifive_interface0_cyc0 & pifive_interface0_stb0) & pifive_interface0_we0) & pifive_interface0_sel0[0];
		pifive_sram0_we[1] <= ((pifive_interface0_cyc0 & pifive_interface0_stb0) & pifive_interface0_we0) & pifive_interface0_sel0[1];
		pifive_sram0_we[2] <= ((pifive_interface0_cyc0 & pifive_interface0_stb0) & pifive_interface0_we0) & pifive_interface0_sel0[2];
		pifive_sram0_we[3] <= ((pifive_interface0_cyc0 & pifive_interface0_stb0) & pifive_interface0_we0) & pifive_interface0_sel0[3];
		dummy_d_20 <= dummy_s;
	end
	assign pifive_sram0_adr = pifive_interface0_adr0[1:0];
	assign pifive_interface0_dat_r0 = pifive_sram0_dat_r;
	assign pifive_sram0_dat_w = pifive_interface0_dat_w0;
	reg dummy_d_21;
	always @(*) begin
		pifive_sram1_we <= 4'd0;
		pifive_sram1_we[0] <= ((pifive_interface1_cyc0 & pifive_interface1_stb0) & pifive_interface1_we0) & pifive_interface1_sel0[0];
		pifive_sram1_we[1] <= ((pifive_interface1_cyc0 & pifive_interface1_stb0) & pifive_interface1_we0) & pifive_interface1_sel0[1];
		pifive_sram1_we[2] <= ((pifive_interface1_cyc0 & pifive_interface1_stb0) & pifive_interface1_we0) & pifive_interface1_sel0[2];
		pifive_sram1_we[3] <= ((pifive_interface1_cyc0 & pifive_interface1_stb0) & pifive_interface1_we0) & pifive_interface1_sel0[3];
		dummy_d_21 <= dummy_s;
	end
	assign pifive_sram1_adr = pifive_interface1_adr0[1:0];
	assign pifive_interface1_dat_r0 = pifive_sram1_dat_r;
	assign pifive_sram1_dat_w = pifive_interface1_dat_w0;
	assign pifive_iocontrol_bus_dat_w = pifive_interface0_controller_bus_dat_w;
	assign pifive_interface0_controller_bus_dat_r = pifive_iocontrol_bus_dat_r;
	assign pifive_iocontrol_bus_sel = pifive_interface0_controller_bus_sel;
	assign pifive_iocontrol_bus_cyc = pifive_interface0_controller_bus_cyc;
	assign pifive_iocontrol_bus_stb = pifive_interface0_controller_bus_stb;
	assign pifive_interface0_controller_bus_ack = pifive_iocontrol_bus_ack;
	assign pifive_iocontrol_bus_we = pifive_interface0_controller_bus_we;
	assign pifive_interface0_controller_bus_err = pifive_iocontrol_bus_err;
	assign pifive_iocontrol_bus_adr = slice_proxy0[32:0];
	assign pifive_spi0_bus_dat_w = pifive_interface1_controller_bus_dat_w;
	assign pifive_interface1_controller_bus_dat_r = pifive_spi0_bus_dat_r;
	assign pifive_spi0_bus_sel = pifive_interface1_controller_bus_sel;
	assign pifive_spi0_bus_cyc = pifive_interface1_controller_bus_cyc;
	assign pifive_spi0_bus_stb = pifive_interface1_controller_bus_stb;
	assign pifive_interface1_controller_bus_ack = pifive_spi0_bus_ack;
	assign pifive_spi0_bus_we = pifive_interface1_controller_bus_we;
	assign pifive_interface1_controller_bus_err = pifive_spi0_bus_err;
	assign pifive_spi0_bus_adr = slice_proxy1[32:0];
	assign pifive_spi1_bus_dat_w = pifive_interface2_controller_bus_dat_w;
	assign pifive_interface2_controller_bus_dat_r = pifive_spi1_bus_dat_r;
	assign pifive_spi1_bus_sel = pifive_interface2_controller_bus_sel;
	assign pifive_spi1_bus_cyc = pifive_interface2_controller_bus_cyc;
	assign pifive_spi1_bus_stb = pifive_interface2_controller_bus_stb;
	assign pifive_interface2_controller_bus_ack = pifive_spi1_bus_ack;
	assign pifive_spi1_bus_we = pifive_interface2_controller_bus_we;
	assign pifive_interface2_controller_bus_err = pifive_spi1_bus_err;
	assign pifive_spi1_bus_adr = slice_proxy2[32:0];
	assign pifive_uart0_bus_dat_w = pifive_interface3_controller_bus_dat_w;
	assign pifive_interface3_controller_bus_dat_r = pifive_uart0_bus_dat_r;
	assign pifive_uart0_bus_sel = pifive_interface3_controller_bus_sel;
	assign pifive_uart0_bus_cyc = pifive_interface3_controller_bus_cyc;
	assign pifive_uart0_bus_stb = pifive_interface3_controller_bus_stb;
	assign pifive_interface3_controller_bus_ack = pifive_uart0_bus_ack;
	assign pifive_uart0_bus_we = pifive_interface3_controller_bus_we;
	assign pifive_interface3_controller_bus_err = pifive_uart0_bus_err;
	assign pifive_uart0_bus_adr = slice_proxy3[32:0];
	assign pifive_uart1_bus_dat_w = pifive_interface4_controller_bus_dat_w;
	assign pifive_interface4_controller_bus_dat_r = pifive_uart1_bus_dat_r;
	assign pifive_uart1_bus_sel = pifive_interface4_controller_bus_sel;
	assign pifive_uart1_bus_cyc = pifive_interface4_controller_bus_cyc;
	assign pifive_uart1_bus_stb = pifive_interface4_controller_bus_stb;
	assign pifive_interface4_controller_bus_ack = pifive_uart1_bus_ack;
	assign pifive_uart1_bus_we = pifive_interface4_controller_bus_we;
	assign pifive_interface4_controller_bus_err = pifive_uart1_bus_err;
	assign pifive_uart1_bus_adr = slice_proxy4[32:0];
	assign pifive_i2c_bus_dat_w = pifive_interface5_controller_bus_dat_w;
	assign pifive_interface5_controller_bus_dat_r = pifive_i2c_bus_dat_r;
	assign pifive_i2c_bus_sel = pifive_interface5_controller_bus_sel;
	assign pifive_i2c_bus_cyc = pifive_interface5_controller_bus_cyc;
	assign pifive_i2c_bus_stb = pifive_interface5_controller_bus_stb;
	assign pifive_interface5_controller_bus_ack = pifive_i2c_bus_ack;
	assign pifive_i2c_bus_we = pifive_interface5_controller_bus_we;
	assign pifive_interface5_controller_bus_err = pifive_i2c_bus_err;
	assign pifive_i2c_bus_adr = slice_proxy5[32:0];
	assign pifive_pwm0_bus_dat_w = pifive_interface6_controller_bus_dat_w;
	assign pifive_interface6_controller_bus_dat_r = pifive_pwm0_bus_dat_r;
	assign pifive_pwm0_bus_sel = pifive_interface6_controller_bus_sel;
	assign pifive_pwm0_bus_cyc = pifive_interface6_controller_bus_cyc;
	assign pifive_pwm0_bus_stb = pifive_interface6_controller_bus_stb;
	assign pifive_interface6_controller_bus_ack = pifive_pwm0_bus_ack;
	assign pifive_pwm0_bus_we = pifive_interface6_controller_bus_we;
	assign pifive_interface6_controller_bus_err = pifive_pwm0_bus_err;
	assign pifive_pwm0_bus_adr = slice_proxy6[32:0];
	assign pifive_pwm1_bus_dat_w = pifive_interface7_controller_bus_dat_w;
	assign pifive_interface7_controller_bus_dat_r = pifive_pwm1_bus_dat_r;
	assign pifive_pwm1_bus_sel = pifive_interface7_controller_bus_sel;
	assign pifive_pwm1_bus_cyc = pifive_interface7_controller_bus_cyc;
	assign pifive_pwm1_bus_stb = pifive_interface7_controller_bus_stb;
	assign pifive_interface7_controller_bus_ack = pifive_pwm1_bus_ack;
	assign pifive_pwm1_bus_we = pifive_interface7_controller_bus_we;
	assign pifive_interface7_controller_bus_err = pifive_pwm1_bus_err;
	assign pifive_pwm1_bus_adr = slice_proxy7[32:0];
	assign pifive_pwm2_bus_dat_w = pifive_interface8_controller_bus_dat_w;
	assign pifive_interface8_controller_bus_dat_r = pifive_pwm2_bus_dat_r;
	assign pifive_pwm2_bus_sel = pifive_interface8_controller_bus_sel;
	assign pifive_pwm2_bus_cyc = pifive_interface8_controller_bus_cyc;
	assign pifive_pwm2_bus_stb = pifive_interface8_controller_bus_stb;
	assign pifive_interface8_controller_bus_ack = pifive_pwm2_bus_ack;
	assign pifive_pwm2_bus_we = pifive_interface8_controller_bus_we;
	assign pifive_interface8_controller_bus_err = pifive_pwm2_bus_err;
	assign pifive_pwm2_bus_adr = slice_proxy8[32:0];
	assign pifive_pwm3_bus_dat_w = pifive_interface9_controller_bus_dat_w;
	assign pifive_interface9_controller_bus_dat_r = pifive_pwm3_bus_dat_r;
	assign pifive_pwm3_bus_sel = pifive_interface9_controller_bus_sel;
	assign pifive_pwm3_bus_cyc = pifive_interface9_controller_bus_cyc;
	assign pifive_pwm3_bus_stb = pifive_interface9_controller_bus_stb;
	assign pifive_interface9_controller_bus_ack = pifive_pwm3_bus_ack;
	assign pifive_pwm3_bus_we = pifive_interface9_controller_bus_we;
	assign pifive_interface9_controller_bus_err = pifive_pwm3_bus_err;
	assign pifive_pwm3_bus_adr = slice_proxy9[32:0];
	assign pifive_pwm4_bus_dat_w = pifive_interface10_controller_bus_dat_w;
	assign pifive_interface10_controller_bus_dat_r = pifive_pwm4_bus_dat_r;
	assign pifive_pwm4_bus_sel = pifive_interface10_controller_bus_sel;
	assign pifive_pwm4_bus_cyc = pifive_interface10_controller_bus_cyc;
	assign pifive_pwm4_bus_stb = pifive_interface10_controller_bus_stb;
	assign pifive_interface10_controller_bus_ack = pifive_pwm4_bus_ack;
	assign pifive_pwm4_bus_we = pifive_interface10_controller_bus_we;
	assign pifive_interface10_controller_bus_err = pifive_pwm4_bus_err;
	assign pifive_pwm4_bus_adr = slice_proxy10[32:0];
	assign pifive_pwm5_bus_dat_w = pifive_interface11_controller_bus_dat_w;
	assign pifive_interface11_controller_bus_dat_r = pifive_pwm5_bus_dat_r;
	assign pifive_pwm5_bus_sel = pifive_interface11_controller_bus_sel;
	assign pifive_pwm5_bus_cyc = pifive_interface11_controller_bus_cyc;
	assign pifive_pwm5_bus_stb = pifive_interface11_controller_bus_stb;
	assign pifive_interface11_controller_bus_ack = pifive_pwm5_bus_ack;
	assign pifive_pwm5_bus_we = pifive_interface11_controller_bus_we;
	assign pifive_interface11_controller_bus_err = pifive_pwm5_bus_err;
	assign pifive_pwm5_bus_adr = slice_proxy11[32:0];
	assign pifive_rom0_bus_dat_w = pifive_interface12_controller_bus_dat_w;
	assign pifive_interface12_controller_bus_dat_r = pifive_rom0_bus_dat_r;
	assign pifive_rom0_bus_sel = pifive_interface12_controller_bus_sel;
	assign pifive_rom0_bus_cyc = pifive_interface12_controller_bus_cyc;
	assign pifive_rom0_bus_stb = pifive_interface12_controller_bus_stb;
	assign pifive_interface12_controller_bus_ack = pifive_rom0_bus_ack;
	assign pifive_rom0_bus_we = pifive_interface12_controller_bus_we;
	assign pifive_interface12_controller_bus_err = pifive_rom0_bus_err;
	assign pifive_rom0_bus_adr = slice_proxy12[32:0];
	assign pifive_rom1_bus_dat_w = pifive_interface13_controller_bus_dat_w;
	assign pifive_interface13_controller_bus_dat_r = pifive_rom1_bus_dat_r;
	assign pifive_rom1_bus_sel = pifive_interface13_controller_bus_sel;
	assign pifive_rom1_bus_cyc = pifive_interface13_controller_bus_cyc;
	assign pifive_rom1_bus_stb = pifive_interface13_controller_bus_stb;
	assign pifive_interface13_controller_bus_ack = pifive_rom1_bus_ack;
	assign pifive_rom1_bus_we = pifive_interface13_controller_bus_we;
	assign pifive_interface13_controller_bus_err = pifive_rom1_bus_err;
	assign pifive_rom1_bus_adr = slice_proxy13[32:0];
	assign pifive_uptimetimer_bus_dat_w = pifive_interface14_controller_bus_dat_w;
	assign pifive_interface14_controller_bus_dat_r = pifive_uptimetimer_bus_dat_r;
	assign pifive_uptimetimer_bus_sel = pifive_interface14_controller_bus_sel;
	assign pifive_uptimetimer_bus_cyc = pifive_interface14_controller_bus_cyc;
	assign pifive_uptimetimer_bus_stb = pifive_interface14_controller_bus_stb;
	assign pifive_interface14_controller_bus_ack = pifive_uptimetimer_bus_ack;
	assign pifive_uptimetimer_bus_we = pifive_interface14_controller_bus_we;
	assign pifive_interface14_controller_bus_err = pifive_uptimetimer_bus_err;
	assign pifive_uptimetimer_bus_adr = slice_proxy14[32:0];
	assign pifive_timer0_bus_dat_w = pifive_interface15_controller_bus_dat_w;
	assign pifive_interface15_controller_bus_dat_r = pifive_timer0_bus_dat_r;
	assign pifive_timer0_bus_sel = pifive_interface15_controller_bus_sel;
	assign pifive_timer0_bus_cyc = pifive_interface15_controller_bus_cyc;
	assign pifive_timer0_bus_stb = pifive_interface15_controller_bus_stb;
	assign pifive_interface15_controller_bus_ack = pifive_timer0_bus_ack;
	assign pifive_timer0_bus_we = pifive_interface15_controller_bus_we;
	assign pifive_interface15_controller_bus_err = pifive_timer0_bus_err;
	assign pifive_timer0_bus_adr = slice_proxy15[32:0];
	assign pifive_timer1_bus_dat_w = pifive_interface16_controller_bus_dat_w;
	assign pifive_interface16_controller_bus_dat_r = pifive_timer1_bus_dat_r;
	assign pifive_timer1_bus_sel = pifive_interface16_controller_bus_sel;
	assign pifive_timer1_bus_cyc = pifive_interface16_controller_bus_cyc;
	assign pifive_timer1_bus_stb = pifive_interface16_controller_bus_stb;
	assign pifive_interface16_controller_bus_ack = pifive_timer1_bus_ack;
	assign pifive_timer1_bus_we = pifive_interface16_controller_bus_we;
	assign pifive_interface16_controller_bus_err = pifive_timer1_bus_err;
	assign pifive_timer1_bus_adr = slice_proxy16[32:0];
	reg dummy_d_22;
	always @(*) begin
		pifive_periph_bridge_slave_sel <= 17'd0;
		pifive_periph_bridge_slave_sel[0] <= (pifive_shared_adr >= 31'd1610612736) & (pifive_shared_adr < 31'd1610616832);
		pifive_periph_bridge_slave_sel[1] <= (pifive_shared_adr >= 31'd1879048192) & (pifive_shared_adr < 31'd1879048448);
		pifive_periph_bridge_slave_sel[2] <= (pifive_shared_adr >= 31'd1879048448) & (pifive_shared_adr < 31'd1879048704);
		pifive_periph_bridge_slave_sel[3] <= (pifive_shared_adr >= 31'd1879052288) & (pifive_shared_adr < 31'd1879052544);
		pifive_periph_bridge_slave_sel[4] <= (pifive_shared_adr >= 31'd1879052544) & (pifive_shared_adr < 31'd1879052800);
		pifive_periph_bridge_slave_sel[5] <= (pifive_shared_adr >= 31'd1879056384) & (pifive_shared_adr < 31'd1879056640);
		pifive_periph_bridge_slave_sel[6] <= (pifive_shared_adr >= 31'd1879060480) & (pifive_shared_adr < 31'd1879060736);
		pifive_periph_bridge_slave_sel[7] <= (pifive_shared_adr >= 31'd1879060736) & (pifive_shared_adr < 31'd1879060992);
		pifive_periph_bridge_slave_sel[8] <= (pifive_shared_adr >= 31'd1879060992) & (pifive_shared_adr < 31'd1879061248);
		pifive_periph_bridge_slave_sel[9] <= (pifive_shared_adr >= 31'd1879061248) & (pifive_shared_adr < 31'd1879061504);
		pifive_periph_bridge_slave_sel[10] <= (pifive_shared_adr >= 31'd1879061504) & (pifive_shared_adr < 31'd1879061760);
		pifive_periph_bridge_slave_sel[11] <= (pifive_shared_adr >= 31'd1879061760) & (pifive_shared_adr < 31'd1879062016);
		pifive_periph_bridge_slave_sel[12] <= (pifive_shared_adr >= 1'd0) & (pifive_shared_adr < 25'd16777216);
		pifive_periph_bridge_slave_sel[13] <= (pifive_shared_adr >= 31'd1073741824) & (pifive_shared_adr < 31'd1073745920);
		pifive_periph_bridge_slave_sel[14] <= (pifive_shared_adr >= 31'd1073745920) & (pifive_shared_adr < 31'd1073746176);
		pifive_periph_bridge_slave_sel[15] <= (pifive_shared_adr >= 31'd1073746176) & (pifive_shared_adr < 31'd1073746432);
		pifive_periph_bridge_slave_sel[16] <= (pifive_shared_adr >= 31'd1073746432) & (pifive_shared_adr < 31'd1073746688);
		dummy_d_22 <= dummy_s;
	end
	assign pifive_interface0_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface0_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface0_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface0_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface0_controller_bus_we = pifive_shared_we;
	assign pifive_interface1_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface1_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface1_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface1_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface1_controller_bus_we = pifive_shared_we;
	assign pifive_interface2_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface2_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface2_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface2_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface2_controller_bus_we = pifive_shared_we;
	assign pifive_interface3_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface3_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface3_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface3_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface3_controller_bus_we = pifive_shared_we;
	assign pifive_interface4_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface4_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface4_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface4_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface4_controller_bus_we = pifive_shared_we;
	assign pifive_interface5_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface5_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface5_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface5_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface5_controller_bus_we = pifive_shared_we;
	assign pifive_interface6_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface6_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface6_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface6_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface6_controller_bus_we = pifive_shared_we;
	assign pifive_interface7_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface7_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface7_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface7_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface7_controller_bus_we = pifive_shared_we;
	assign pifive_interface8_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface8_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface8_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface8_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface8_controller_bus_we = pifive_shared_we;
	assign pifive_interface9_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface9_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface9_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface9_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface9_controller_bus_we = pifive_shared_we;
	assign pifive_interface10_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface10_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface10_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface10_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface10_controller_bus_we = pifive_shared_we;
	assign pifive_interface11_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface11_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface11_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface11_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface11_controller_bus_we = pifive_shared_we;
	assign pifive_interface12_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface12_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface12_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface12_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface12_controller_bus_we = pifive_shared_we;
	assign pifive_interface13_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface13_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface13_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface13_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface13_controller_bus_we = pifive_shared_we;
	assign pifive_interface14_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface14_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface14_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface14_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface14_controller_bus_we = pifive_shared_we;
	assign pifive_interface15_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface15_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface15_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface15_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface15_controller_bus_we = pifive_shared_we;
	assign pifive_interface16_controller_bus_adr = pifive_shared_adr;
	assign pifive_interface16_controller_bus_dat_w = pifive_shared_dat_w;
	assign pifive_interface16_controller_bus_sel = pifive_shared_sel;
	assign pifive_interface16_controller_bus_stb = pifive_shared_stb;
	assign pifive_interface16_controller_bus_we = pifive_shared_we;
	assign pifive_interface0_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[0];
	assign pifive_interface1_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[1];
	assign pifive_interface2_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[2];
	assign pifive_interface3_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[3];
	assign pifive_interface4_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[4];
	assign pifive_interface5_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[5];
	assign pifive_interface6_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[6];
	assign pifive_interface7_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[7];
	assign pifive_interface8_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[8];
	assign pifive_interface9_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[9];
	assign pifive_interface10_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[10];
	assign pifive_interface11_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[11];
	assign pifive_interface12_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[12];
	assign pifive_interface13_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[13];
	assign pifive_interface14_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[14];
	assign pifive_interface15_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[15];
	assign pifive_interface16_controller_bus_cyc = pifive_shared_cyc & pifive_periph_bridge_slave_sel[16];
	assign pifive_shared_ack = (((((((((((((((pifive_interface0_controller_bus_ack | pifive_interface1_controller_bus_ack) | pifive_interface2_controller_bus_ack) | pifive_interface3_controller_bus_ack) | pifive_interface4_controller_bus_ack) | pifive_interface5_controller_bus_ack) | pifive_interface6_controller_bus_ack) | pifive_interface7_controller_bus_ack) | pifive_interface8_controller_bus_ack) | pifive_interface9_controller_bus_ack) | pifive_interface10_controller_bus_ack) | pifive_interface11_controller_bus_ack) | pifive_interface12_controller_bus_ack) | pifive_interface13_controller_bus_ack) | pifive_interface14_controller_bus_ack) | pifive_interface15_controller_bus_ack) | pifive_interface16_controller_bus_ack;
	assign pifive_shared_err = (((((((((((((((pifive_interface0_controller_bus_err | pifive_interface1_controller_bus_err) | pifive_interface2_controller_bus_err) | pifive_interface3_controller_bus_err) | pifive_interface4_controller_bus_err) | pifive_interface5_controller_bus_err) | pifive_interface6_controller_bus_err) | pifive_interface7_controller_bus_err) | pifive_interface8_controller_bus_err) | pifive_interface9_controller_bus_err) | pifive_interface10_controller_bus_err) | pifive_interface11_controller_bus_err) | pifive_interface12_controller_bus_err) | pifive_interface13_controller_bus_err) | pifive_interface14_controller_bus_err) | pifive_interface15_controller_bus_err) | pifive_interface16_controller_bus_err;
	assign pifive_shared_dat_r = (((((((((((((((({32 {pifive_periph_bridge_slave_sel_r[0]}} & pifive_interface0_controller_bus_dat_r) | ({32 {pifive_periph_bridge_slave_sel_r[1]}} & pifive_interface1_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[2]}} & pifive_interface2_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[3]}} & pifive_interface3_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[4]}} & pifive_interface4_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[5]}} & pifive_interface5_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[6]}} & pifive_interface6_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[7]}} & pifive_interface7_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[8]}} & pifive_interface8_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[9]}} & pifive_interface9_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[10]}} & pifive_interface10_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[11]}} & pifive_interface11_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[12]}} & pifive_interface12_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[13]}} & pifive_interface13_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[14]}} & pifive_interface14_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[15]}} & pifive_interface15_controller_bus_dat_r)) | ({32 {pifive_periph_bridge_slave_sel_r[16]}} & pifive_interface16_controller_bus_dat_r);
	assign pifive_interface0_dat_w0 = pifive_interface17_controller_bus_dat_w;
	assign pifive_interface17_controller_bus_dat_r = pifive_interface0_dat_r0;
	assign pifive_interface0_sel0 = pifive_interface17_controller_bus_sel;
	assign pifive_interface0_cyc0 = pifive_interface17_controller_bus_cyc;
	assign pifive_interface0_stb0 = pifive_interface17_controller_bus_stb;
	assign pifive_interface17_controller_bus_ack = pifive_interface0_ack0;
	assign pifive_interface0_we0 = pifive_interface17_controller_bus_we;
	assign pifive_interface17_controller_bus_err = pifive_interface0_err0;
	assign pifive_interface0_adr0 = slice_proxy17[32:2];
	assign pifive_interface1_dat_w0 = pifive_interface18_controller_bus_dat_w;
	assign pifive_interface18_controller_bus_dat_r = pifive_interface1_dat_r0;
	assign pifive_interface1_sel0 = pifive_interface18_controller_bus_sel;
	assign pifive_interface1_cyc0 = pifive_interface18_controller_bus_cyc;
	assign pifive_interface1_stb0 = pifive_interface18_controller_bus_stb;
	assign pifive_interface18_controller_bus_ack = pifive_interface1_ack0;
	assign pifive_interface1_we0 = pifive_interface18_controller_bus_we;
	assign pifive_interface18_controller_bus_err = pifive_interface1_err0;
	assign pifive_interface1_adr0 = slice_proxy18[32:2];
	assign pifive_shared_dat_w = pifive_interface19_controller_bus_dat_w;
	assign pifive_interface19_controller_bus_dat_r = pifive_shared_dat_r;
	assign pifive_shared_sel = pifive_interface19_controller_bus_sel;
	assign pifive_shared_cyc = pifive_interface19_controller_bus_cyc;
	assign pifive_shared_stb = pifive_interface19_controller_bus_stb;
	assign pifive_interface19_controller_bus_ack = pifive_shared_ack;
	assign pifive_shared_we = pifive_interface19_controller_bus_we;
	assign pifive_interface19_controller_bus_err = pifive_shared_err;
	assign pifive_shared_adr = pifive_interface19_controller_bus_adr;
	reg dummy_d_23;
	always @(*) begin
		pifive_decoder0_slave_sel <= 3'd0;
		pifive_decoder0_slave_sel[0] <= (pifive_wishbonedebugbus_bus_adr >= 32'd3221225472) & (pifive_wishbonedebugbus_bus_adr < 32'd3221225488);
		pifive_decoder0_slave_sel[1] <= (pifive_wishbonedebugbus_bus_adr >= 32'd3489660928) & (pifive_wishbonedebugbus_bus_adr < 32'd3489660944);
		pifive_decoder0_slave_sel[2] <= (pifive_wishbonedebugbus_bus_adr >= 1'd0) & (pifive_wishbonedebugbus_bus_adr < 32'd2147483648);
		dummy_d_23 <= dummy_s;
	end
	assign pifive_decoder0_slave_sel_r = pifive_decoder0_slave_sel;
	assign pifive_interface0_adr1 = pifive_wishbonedebugbus_bus_adr;
	assign pifive_interface0_dat_w1 = pifive_wishbonedebugbus_bus_dat_w;
	assign pifive_interface0_sel1 = pifive_wishbonedebugbus_bus_sel;
	assign pifive_interface0_stb1 = pifive_wishbonedebugbus_bus_stb;
	assign pifive_interface0_we1 = pifive_wishbonedebugbus_bus_we;
	assign pifive_interface1_adr1 = pifive_wishbonedebugbus_bus_adr;
	assign pifive_interface1_dat_w1 = pifive_wishbonedebugbus_bus_dat_w;
	assign pifive_interface1_sel1 = pifive_wishbonedebugbus_bus_sel;
	assign pifive_interface1_stb1 = pifive_wishbonedebugbus_bus_stb;
	assign pifive_interface1_we1 = pifive_wishbonedebugbus_bus_we;
	assign pifive_interface2_adr = pifive_wishbonedebugbus_bus_adr;
	assign pifive_interface2_dat_w = pifive_wishbonedebugbus_bus_dat_w;
	assign pifive_interface2_sel = pifive_wishbonedebugbus_bus_sel;
	assign pifive_interface2_stb = pifive_wishbonedebugbus_bus_stb;
	assign pifive_interface2_we = pifive_wishbonedebugbus_bus_we;
	assign pifive_interface0_cyc1 = pifive_wishbonedebugbus_bus_cyc & pifive_decoder0_slave_sel[0];
	assign pifive_interface1_cyc1 = pifive_wishbonedebugbus_bus_cyc & pifive_decoder0_slave_sel[1];
	assign pifive_interface2_cyc = pifive_wishbonedebugbus_bus_cyc & pifive_decoder0_slave_sel[2];
	assign pifive_wishbonedebugbus_bus_ack = (pifive_interface0_ack1 | pifive_interface1_ack1) | pifive_interface2_ack;
	assign pifive_wishbonedebugbus_bus_err = (pifive_interface0_err1 | pifive_interface1_err1) | pifive_interface2_err;
	assign pifive_wishbonedebugbus_bus_dat_r = (({32 {pifive_decoder0_slave_sel_r[0]}} & pifive_interface0_dat_r1) | ({32 {pifive_decoder0_slave_sel_r[1]}} & pifive_interface1_dat_r1)) | ({32 {pifive_decoder0_slave_sel_r[2]}} & pifive_interface2_dat_r);
	reg dummy_d_24;
	always @(*) begin
		pifive_decoder1_slave_sel <= 3'd0;
		pifive_decoder1_slave_sel[0] <= (pifive_instr_bus_adr >= 32'd3221225472) & (pifive_instr_bus_adr < 32'd3221225488);
		pifive_decoder1_slave_sel[1] <= (pifive_instr_bus_adr >= 32'd3489660928) & (pifive_instr_bus_adr < 32'd3489660944);
		pifive_decoder1_slave_sel[2] <= (pifive_instr_bus_adr >= 1'd0) & (pifive_instr_bus_adr < 32'd2147483648);
		dummy_d_24 <= dummy_s;
	end
	assign pifive_decoder1_slave_sel_r = pifive_decoder1_slave_sel;
	assign pifive_interface3_adr = pifive_instr_bus_adr;
	assign pifive_interface3_dat_w = pifive_instr_bus_dat_w;
	assign pifive_interface3_sel = pifive_instr_bus_sel;
	assign pifive_interface3_stb = pifive_instr_bus_stb;
	assign pifive_interface3_we = pifive_instr_bus_we;
	assign pifive_interface4_adr = pifive_instr_bus_adr;
	assign pifive_interface4_dat_w = pifive_instr_bus_dat_w;
	assign pifive_interface4_sel = pifive_instr_bus_sel;
	assign pifive_interface4_stb = pifive_instr_bus_stb;
	assign pifive_interface4_we = pifive_instr_bus_we;
	assign pifive_interface5_adr = pifive_instr_bus_adr;
	assign pifive_interface5_dat_w = pifive_instr_bus_dat_w;
	assign pifive_interface5_sel = pifive_instr_bus_sel;
	assign pifive_interface5_stb = pifive_instr_bus_stb;
	assign pifive_interface5_we = pifive_instr_bus_we;
	assign pifive_interface3_cyc = pifive_instr_bus_cyc & pifive_decoder1_slave_sel[0];
	assign pifive_interface4_cyc = pifive_instr_bus_cyc & pifive_decoder1_slave_sel[1];
	assign pifive_interface5_cyc = pifive_instr_bus_cyc & pifive_decoder1_slave_sel[2];
	assign pifive_instr_bus_ack = (pifive_interface3_ack | pifive_interface4_ack) | pifive_interface5_ack;
	assign pifive_instr_bus_err = (pifive_interface3_err | pifive_interface4_err) | pifive_interface5_err;
	assign pifive_instr_bus_dat_r = (({32 {pifive_decoder1_slave_sel_r[0]}} & pifive_interface3_dat_r) | ({32 {pifive_decoder1_slave_sel_r[1]}} & pifive_interface4_dat_r)) | ({32 {pifive_decoder1_slave_sel_r[2]}} & pifive_interface5_dat_r);
	reg dummy_d_25;
	always @(*) begin
		pifive_decoder2_slave_sel <= 3'd0;
		pifive_decoder2_slave_sel[0] <= (pifive_data_bus_adr >= 32'd3221225472) & (pifive_data_bus_adr < 32'd3221225488);
		pifive_decoder2_slave_sel[1] <= (pifive_data_bus_adr >= 32'd3489660928) & (pifive_data_bus_adr < 32'd3489660944);
		pifive_decoder2_slave_sel[2] <= (pifive_data_bus_adr >= 1'd0) & (pifive_data_bus_adr < 32'd2147483648);
		dummy_d_25 <= dummy_s;
	end
	assign pifive_decoder2_slave_sel_r = pifive_decoder2_slave_sel;
	assign pifive_interface6_adr = pifive_data_bus_adr;
	assign pifive_interface6_dat_w = pifive_data_bus_dat_w;
	assign pifive_interface6_sel = pifive_data_bus_sel;
	assign pifive_interface6_stb = pifive_data_bus_stb;
	assign pifive_interface6_we = pifive_data_bus_we;
	assign pifive_interface7_adr = pifive_data_bus_adr;
	assign pifive_interface7_dat_w = pifive_data_bus_dat_w;
	assign pifive_interface7_sel = pifive_data_bus_sel;
	assign pifive_interface7_stb = pifive_data_bus_stb;
	assign pifive_interface7_we = pifive_data_bus_we;
	assign pifive_interface8_adr = pifive_data_bus_adr;
	assign pifive_interface8_dat_w = pifive_data_bus_dat_w;
	assign pifive_interface8_sel = pifive_data_bus_sel;
	assign pifive_interface8_stb = pifive_data_bus_stb;
	assign pifive_interface8_we = pifive_data_bus_we;
	assign pifive_interface6_cyc = pifive_data_bus_cyc & pifive_decoder2_slave_sel[0];
	assign pifive_interface7_cyc = pifive_data_bus_cyc & pifive_decoder2_slave_sel[1];
	assign pifive_interface8_cyc = pifive_data_bus_cyc & pifive_decoder2_slave_sel[2];
	assign pifive_data_bus_ack = (pifive_interface6_ack | pifive_interface7_ack) | pifive_interface8_ack;
	assign pifive_data_bus_err = (pifive_interface6_err | pifive_interface7_err) | pifive_interface8_err;
	assign pifive_data_bus_dat_r = (({32 {pifive_decoder2_slave_sel_r[0]}} & pifive_interface6_dat_r) | ({32 {pifive_decoder2_slave_sel_r[1]}} & pifive_interface7_dat_r)) | ({32 {pifive_decoder2_slave_sel_r[2]}} & pifive_interface8_dat_r);
	assign pifive_interface17_controller_bus_adr = comb_array_muxed0;
	assign pifive_interface17_controller_bus_dat_w = comb_array_muxed1;
	assign pifive_interface17_controller_bus_sel = comb_array_muxed2;
	assign pifive_interface17_controller_bus_cyc = comb_array_muxed3;
	assign pifive_interface17_controller_bus_stb = comb_array_muxed4;
	assign pifive_interface17_controller_bus_we = comb_array_muxed5;
	assign pifive_interface0_dat_r1 = pifive_interface17_controller_bus_dat_r;
	assign pifive_interface3_dat_r = pifive_interface17_controller_bus_dat_r;
	assign pifive_interface6_dat_r = pifive_interface17_controller_bus_dat_r;
	assign pifive_interface0_ack1 = pifive_interface17_controller_bus_ack & (pifive_arbiter0_grant == 1'd0);
	assign pifive_interface3_ack = pifive_interface17_controller_bus_ack & (pifive_arbiter0_grant == 1'd1);
	assign pifive_interface6_ack = pifive_interface17_controller_bus_ack & (pifive_arbiter0_grant == 2'd2);
	assign pifive_interface0_err1 = pifive_interface17_controller_bus_err & (pifive_arbiter0_grant == 1'd0);
	assign pifive_interface3_err = pifive_interface17_controller_bus_err & (pifive_arbiter0_grant == 1'd1);
	assign pifive_interface6_err = pifive_interface17_controller_bus_err & (pifive_arbiter0_grant == 2'd2);
	assign pifive_arbiter0_request = {pifive_interface6_cyc, pifive_interface3_cyc, pifive_interface0_cyc1};
	assign pifive_interface18_controller_bus_adr = comb_array_muxed6;
	assign pifive_interface18_controller_bus_dat_w = comb_array_muxed7;
	assign pifive_interface18_controller_bus_sel = comb_array_muxed8;
	assign pifive_interface18_controller_bus_cyc = comb_array_muxed9;
	assign pifive_interface18_controller_bus_stb = comb_array_muxed10;
	assign pifive_interface18_controller_bus_we = comb_array_muxed11;
	assign pifive_interface1_dat_r1 = pifive_interface18_controller_bus_dat_r;
	assign pifive_interface4_dat_r = pifive_interface18_controller_bus_dat_r;
	assign pifive_interface7_dat_r = pifive_interface18_controller_bus_dat_r;
	assign pifive_interface1_ack1 = pifive_interface18_controller_bus_ack & (pifive_arbiter1_grant == 1'd0);
	assign pifive_interface4_ack = pifive_interface18_controller_bus_ack & (pifive_arbiter1_grant == 1'd1);
	assign pifive_interface7_ack = pifive_interface18_controller_bus_ack & (pifive_arbiter1_grant == 2'd2);
	assign pifive_interface1_err1 = pifive_interface18_controller_bus_err & (pifive_arbiter1_grant == 1'd0);
	assign pifive_interface4_err = pifive_interface18_controller_bus_err & (pifive_arbiter1_grant == 1'd1);
	assign pifive_interface7_err = pifive_interface18_controller_bus_err & (pifive_arbiter1_grant == 2'd2);
	assign pifive_arbiter1_request = {pifive_interface7_cyc, pifive_interface4_cyc, pifive_interface1_cyc1};
	assign pifive_interface19_controller_bus_adr = comb_array_muxed12;
	assign pifive_interface19_controller_bus_dat_w = comb_array_muxed13;
	assign pifive_interface19_controller_bus_sel = comb_array_muxed14;
	assign pifive_interface19_controller_bus_cyc = comb_array_muxed15;
	assign pifive_interface19_controller_bus_stb = comb_array_muxed16;
	assign pifive_interface19_controller_bus_we = comb_array_muxed17;
	assign pifive_interface2_dat_r = pifive_interface19_controller_bus_dat_r;
	assign pifive_interface5_dat_r = pifive_interface19_controller_bus_dat_r;
	assign pifive_interface8_dat_r = pifive_interface19_controller_bus_dat_r;
	assign pifive_interface2_ack = pifive_interface19_controller_bus_ack & (pifive_arbiter2_grant == 1'd0);
	assign pifive_interface5_ack = pifive_interface19_controller_bus_ack & (pifive_arbiter2_grant == 1'd1);
	assign pifive_interface8_ack = pifive_interface19_controller_bus_ack & (pifive_arbiter2_grant == 2'd2);
	assign pifive_interface2_err = pifive_interface19_controller_bus_err & (pifive_arbiter2_grant == 1'd0);
	assign pifive_interface5_err = pifive_interface19_controller_bus_err & (pifive_arbiter2_grant == 1'd1);
	assign pifive_interface8_err = pifive_interface19_controller_bus_err & (pifive_arbiter2_grant == 2'd2);
	assign pifive_arbiter2_request = {pifive_interface8_cyc, pifive_interface5_cyc, pifive_interface2_cyc};
	assign pifive_iocontrol_debug_bus_dat_w = pifive_interface20_controller_bus_dat_w;
	assign pifive_interface20_controller_bus_dat_r = pifive_iocontrol_debug_bus_dat_r;
	assign pifive_iocontrol_debug_bus_sel = pifive_interface20_controller_bus_sel;
	assign pifive_iocontrol_debug_bus_cyc = pifive_interface20_controller_bus_cyc;
	assign pifive_iocontrol_debug_bus_stb = pifive_interface20_controller_bus_stb;
	assign pifive_interface20_controller_bus_ack = pifive_iocontrol_debug_bus_ack;
	assign pifive_iocontrol_debug_bus_we = pifive_interface20_controller_bus_we;
	assign pifive_interface20_controller_bus_err = pifive_iocontrol_debug_bus_err;
	assign pifive_iocontrol_debug_bus_adr = slice_proxy19[32:0];
	assign pifive_debug_interconnect_slave_sel = (pifive_debug_bus_debug_bus_adr >= 30'd810549248) & (pifive_debug_bus_debug_bus_adr < 30'd811597824);
	assign pifive_interface20_controller_bus_adr = pifive_debug_bus_debug_bus_adr;
	assign pifive_interface20_controller_bus_dat_w = pifive_debug_bus_debug_bus_dat_w;
	assign pifive_interface20_controller_bus_sel = pifive_debug_bus_debug_bus_sel;
	assign pifive_interface20_controller_bus_stb = pifive_debug_bus_debug_bus_stb;
	assign pifive_interface20_controller_bus_we = pifive_debug_bus_debug_bus_we;
	assign pifive_interface20_controller_bus_cyc = pifive_debug_bus_debug_bus_cyc & pifive_debug_interconnect_slave_sel;
	assign pifive_debug_bus_debug_bus_ack = pifive_interface20_controller_bus_ack;
	assign pifive_debug_bus_debug_bus_err = pifive_interface20_controller_bus_err;
	assign pifive_debug_bus_debug_bus_dat_r = {32 {pifive_debug_interconnect_slave_sel_r}} & pifive_interface20_controller_bus_dat_r;
	assign slice_proxy0 = pifive_interface0_controller_bus_adr - 31'd1610612736;
	assign slice_proxy1 = pifive_interface1_controller_bus_adr - 31'd1879048192;
	assign slice_proxy2 = pifive_interface2_controller_bus_adr - 31'd1879048448;
	assign slice_proxy3 = pifive_interface3_controller_bus_adr - 31'd1879052288;
	assign slice_proxy4 = pifive_interface4_controller_bus_adr - 31'd1879052544;
	assign slice_proxy5 = pifive_interface5_controller_bus_adr - 31'd1879056384;
	assign slice_proxy6 = pifive_interface6_controller_bus_adr - 31'd1879060480;
	assign slice_proxy7 = pifive_interface7_controller_bus_adr - 31'd1879060736;
	assign slice_proxy8 = pifive_interface8_controller_bus_adr - 31'd1879060992;
	assign slice_proxy9 = pifive_interface9_controller_bus_adr - 31'd1879061248;
	assign slice_proxy10 = pifive_interface10_controller_bus_adr - 31'd1879061504;
	assign slice_proxy11 = pifive_interface11_controller_bus_adr - 31'd1879061760;
	assign slice_proxy12 = pifive_interface12_controller_bus_adr - 1'd0;
	assign slice_proxy13 = pifive_interface13_controller_bus_adr - 31'd1073741824;
	assign slice_proxy14 = pifive_interface14_controller_bus_adr - 31'd1073745920;
	assign slice_proxy15 = pifive_interface15_controller_bus_adr - 31'd1073746176;
	assign slice_proxy16 = pifive_interface16_controller_bus_adr - 31'd1073746432;
	assign slice_proxy17 = pifive_interface17_controller_bus_adr - 32'd3221225472;
	assign slice_proxy18 = pifive_interface18_controller_bus_adr - 32'd3489660928;
	assign slice_proxy19 = pifive_interface20_controller_bus_adr - 30'd810549248;
	reg dummy_d_26;
	always @(*) begin
		comb_array_muxed0 <= 32'd0;
		case (pifive_arbiter0_grant)
			1'd0: comb_array_muxed0 <= pifive_interface0_adr1;
			1'd1: comb_array_muxed0 <= pifive_interface3_adr;
			default: comb_array_muxed0 <= pifive_interface6_adr;
		endcase
		dummy_d_26 <= dummy_s;
	end
	reg dummy_d_27;
	always @(*) begin
		comb_array_muxed1 <= 32'd0;
		case (pifive_arbiter0_grant)
			1'd0: comb_array_muxed1 <= pifive_interface0_dat_w1;
			1'd1: comb_array_muxed1 <= pifive_interface3_dat_w;
			default: comb_array_muxed1 <= pifive_interface6_dat_w;
		endcase
		dummy_d_27 <= dummy_s;
	end
	reg dummy_d_28;
	always @(*) begin
		comb_array_muxed2 <= 4'd0;
		case (pifive_arbiter0_grant)
			1'd0: comb_array_muxed2 <= pifive_interface0_sel1;
			1'd1: comb_array_muxed2 <= pifive_interface3_sel;
			default: comb_array_muxed2 <= pifive_interface6_sel;
		endcase
		dummy_d_28 <= dummy_s;
	end
	reg dummy_d_29;
	always @(*) begin
		comb_array_muxed3 <= 1'd0;
		case (pifive_arbiter0_grant)
			1'd0: comb_array_muxed3 <= pifive_interface0_cyc1;
			1'd1: comb_array_muxed3 <= pifive_interface3_cyc;
			default: comb_array_muxed3 <= pifive_interface6_cyc;
		endcase
		dummy_d_29 <= dummy_s;
	end
	reg dummy_d_30;
	always @(*) begin
		comb_array_muxed4 <= 1'd0;
		case (pifive_arbiter0_grant)
			1'd0: comb_array_muxed4 <= pifive_interface0_stb1;
			1'd1: comb_array_muxed4 <= pifive_interface3_stb;
			default: comb_array_muxed4 <= pifive_interface6_stb;
		endcase
		dummy_d_30 <= dummy_s;
	end
	reg dummy_d_31;
	always @(*) begin
		comb_array_muxed5 <= 1'd0;
		case (pifive_arbiter0_grant)
			1'd0: comb_array_muxed5 <= pifive_interface0_we1;
			1'd1: comb_array_muxed5 <= pifive_interface3_we;
			default: comb_array_muxed5 <= pifive_interface6_we;
		endcase
		dummy_d_31 <= dummy_s;
	end
	reg dummy_d_32;
	always @(*) begin
		comb_array_muxed6 <= 32'd0;
		case (pifive_arbiter1_grant)
			1'd0: comb_array_muxed6 <= pifive_interface1_adr1;
			1'd1: comb_array_muxed6 <= pifive_interface4_adr;
			default: comb_array_muxed6 <= pifive_interface7_adr;
		endcase
		dummy_d_32 <= dummy_s;
	end
	reg dummy_d_33;
	always @(*) begin
		comb_array_muxed7 <= 32'd0;
		case (pifive_arbiter1_grant)
			1'd0: comb_array_muxed7 <= pifive_interface1_dat_w1;
			1'd1: comb_array_muxed7 <= pifive_interface4_dat_w;
			default: comb_array_muxed7 <= pifive_interface7_dat_w;
		endcase
		dummy_d_33 <= dummy_s;
	end
	reg dummy_d_34;
	always @(*) begin
		comb_array_muxed8 <= 4'd0;
		case (pifive_arbiter1_grant)
			1'd0: comb_array_muxed8 <= pifive_interface1_sel1;
			1'd1: comb_array_muxed8 <= pifive_interface4_sel;
			default: comb_array_muxed8 <= pifive_interface7_sel;
		endcase
		dummy_d_34 <= dummy_s;
	end
	reg dummy_d_35;
	always @(*) begin
		comb_array_muxed9 <= 1'd0;
		case (pifive_arbiter1_grant)
			1'd0: comb_array_muxed9 <= pifive_interface1_cyc1;
			1'd1: comb_array_muxed9 <= pifive_interface4_cyc;
			default: comb_array_muxed9 <= pifive_interface7_cyc;
		endcase
		dummy_d_35 <= dummy_s;
	end
	reg dummy_d_36;
	always @(*) begin
		comb_array_muxed10 <= 1'd0;
		case (pifive_arbiter1_grant)
			1'd0: comb_array_muxed10 <= pifive_interface1_stb1;
			1'd1: comb_array_muxed10 <= pifive_interface4_stb;
			default: comb_array_muxed10 <= pifive_interface7_stb;
		endcase
		dummy_d_36 <= dummy_s;
	end
	reg dummy_d_37;
	always @(*) begin
		comb_array_muxed11 <= 1'd0;
		case (pifive_arbiter1_grant)
			1'd0: comb_array_muxed11 <= pifive_interface1_we1;
			1'd1: comb_array_muxed11 <= pifive_interface4_we;
			default: comb_array_muxed11 <= pifive_interface7_we;
		endcase
		dummy_d_37 <= dummy_s;
	end
	reg dummy_d_38;
	always @(*) begin
		comb_array_muxed12 <= 32'd0;
		case (pifive_arbiter2_grant)
			1'd0: comb_array_muxed12 <= pifive_interface2_adr;
			1'd1: comb_array_muxed12 <= pifive_interface5_adr;
			default: comb_array_muxed12 <= pifive_interface8_adr;
		endcase
		dummy_d_38 <= dummy_s;
	end
	reg dummy_d_39;
	always @(*) begin
		comb_array_muxed13 <= 32'd0;
		case (pifive_arbiter2_grant)
			1'd0: comb_array_muxed13 <= pifive_interface2_dat_w;
			1'd1: comb_array_muxed13 <= pifive_interface5_dat_w;
			default: comb_array_muxed13 <= pifive_interface8_dat_w;
		endcase
		dummy_d_39 <= dummy_s;
	end
	reg dummy_d_40;
	always @(*) begin
		comb_array_muxed14 <= 4'd0;
		case (pifive_arbiter2_grant)
			1'd0: comb_array_muxed14 <= pifive_interface2_sel;
			1'd1: comb_array_muxed14 <= pifive_interface5_sel;
			default: comb_array_muxed14 <= pifive_interface8_sel;
		endcase
		dummy_d_40 <= dummy_s;
	end
	reg dummy_d_41;
	always @(*) begin
		comb_array_muxed15 <= 1'd0;
		case (pifive_arbiter2_grant)
			1'd0: comb_array_muxed15 <= pifive_interface2_cyc;
			1'd1: comb_array_muxed15 <= pifive_interface5_cyc;
			default: comb_array_muxed15 <= pifive_interface8_cyc;
		endcase
		dummy_d_41 <= dummy_s;
	end
	reg dummy_d_42;
	always @(*) begin
		comb_array_muxed16 <= 1'd0;
		case (pifive_arbiter2_grant)
			1'd0: comb_array_muxed16 <= pifive_interface2_stb;
			1'd1: comb_array_muxed16 <= pifive_interface5_stb;
			default: comb_array_muxed16 <= pifive_interface8_stb;
		endcase
		dummy_d_42 <= dummy_s;
	end
	reg dummy_d_43;
	always @(*) begin
		comb_array_muxed17 <= 1'd0;
		case (pifive_arbiter2_grant)
			1'd0: comb_array_muxed17 <= pifive_interface2_we;
			1'd1: comb_array_muxed17 <= pifive_interface5_we;
			default: comb_array_muxed17 <= pifive_interface8_we;
		endcase
		dummy_d_43 <= dummy_s;
	end
	reg dummy_d_44;
	always @(*) begin
		sync_array_muxed0 <= 32'd0;
		case (pifive_rom0_bus_adr >>> 2'd2)
			1'd0: sync_array_muxed0 <= 31'd1610613815;
			1'd1: sync_array_muxed0 <= 19'd263187;
			2'd2: sync_array_muxed0 <= 31'd1073747127;
			2'd3: sync_array_muxed0 <= 19'd296083;
			3'd4: sync_array_muxed0 <= 19'd303747;
			3'd5: sync_array_muxed0 <= 24'd12501815;
			3'd6: sync_array_muxed0 <= 32'd3254977299;
			3'd7: sync_array_muxed0 <= 23'd6455987;
			4'd8: sync_array_muxed0 <= 15'd17335;
			4'd9: sync_array_muxed0 <= 23'd6521747;
			4'd10: sync_array_muxed0 <= 26'd41167395;
			4'd11: sync_array_muxed0 <= 19'd303875;
			4'd12: sync_array_muxed0 <= 32'd4266880739;
			4'd13: sync_array_muxed0 <= 10'd951;
			4'd14: sync_array_muxed0 <= 18'd230291;
			4'd15: sync_array_muxed0 <= 26'd41167395;
			5'd16: sync_array_muxed0 <= 15'd17335;
			5'd17: sync_array_muxed0 <= 31'd1073972115;
			5'd18: sync_array_muxed0 <= 23'd7610403;
			5'd19: sync_array_muxed0 <= 23'd7610915;
			5'd20: sync_array_muxed0 <= 31'd1879053367;
			5'd21: sync_array_muxed0 <= 19'd263187;
			5'd22: sync_array_muxed0 <= 10'd951;
			5'd23: sync_array_muxed0 <= 27'd113476499;
			5'd24: sync_array_muxed0 <= 23'd7610915;
			5'd25: sync_array_muxed0 <= 10'd695;
			5'd26: sync_array_muxed0 <= 23'd5407379;
			5'd27: sync_array_muxed0 <= 23'd5514275;
			5'd28: sync_array_muxed0 <= 11'd1939;
			5'd29: sync_array_muxed0 <= 19'd270979;
			5'd30: sync_array_muxed0 <= 21'd1241747;
			5'd31: sync_array_muxed0 <= 32'd4261584099;
			6'd32: sync_array_muxed0 <= 24'd12853891;
			6'd33: sync_array_muxed0 <= 28'd267580051;
			6'd34: sync_array_muxed0 <= 18'd168595;
			6'd35: sync_array_muxed0 <= 23'd5760947;
			6'd36: sync_array_muxed0 <= 19'd270979;
			6'd37: sync_array_muxed0 <= 21'd1241747;
			6'd38: sync_array_muxed0 <= 32'd4261584099;
			6'd39: sync_array_muxed0 <= 24'd12853891;
			6'd40: sync_array_muxed0 <= 28'd267580051;
			6'd41: sync_array_muxed0 <= 24'd8557203;
			6'd42: sync_array_muxed0 <= 23'd5760947;
			6'd43: sync_array_muxed0 <= 19'd270979;
			6'd44: sync_array_muxed0 <= 21'd1241747;
			6'd45: sync_array_muxed0 <= 32'd4261584099;
			6'd46: sync_array_muxed0 <= 24'd12853891;
			6'd47: sync_array_muxed0 <= 28'd267580051;
			6'd48: sync_array_muxed0 <= 25'd16945811;
			6'd49: sync_array_muxed0 <= 23'd5760947;
			6'd50: sync_array_muxed0 <= 19'd270979;
			6'd51: sync_array_muxed0 <= 21'd1241747;
			6'd52: sync_array_muxed0 <= 32'd4261584099;
			6'd53: sync_array_muxed0 <= 24'd12853891;
			6'd54: sync_array_muxed0 <= 28'd267580051;
			6'd55: sync_array_muxed0 <= 25'd25334419;
			6'd56: sync_array_muxed0 <= 23'd5760947;
			6'd57: sync_array_muxed0 <= 11'd1427;
			6'd58: sync_array_muxed0 <= 19'd270979;
			6'd59: sync_array_muxed0 <= 21'd1241747;
			6'd60: sync_array_muxed0 <= 32'd4261584099;
			6'd61: sync_array_muxed0 <= 24'd12853891;
			6'd62: sync_array_muxed0 <= 28'd267580051;
			6'd63: sync_array_muxed0 <= 18'd168595;
			7'd64: sync_array_muxed0 <= 23'd5629363;
			7'd65: sync_array_muxed0 <= 19'd270979;
			7'd66: sync_array_muxed0 <= 21'd1241747;
			7'd67: sync_array_muxed0 <= 32'd4261584099;
			7'd68: sync_array_muxed0 <= 24'd12853891;
			7'd69: sync_array_muxed0 <= 28'd267580051;
			7'd70: sync_array_muxed0 <= 24'd8557203;
			7'd71: sync_array_muxed0 <= 23'd5629363;
			7'd72: sync_array_muxed0 <= 19'd270979;
			7'd73: sync_array_muxed0 <= 21'd1241747;
			7'd74: sync_array_muxed0 <= 32'd4261584099;
			7'd75: sync_array_muxed0 <= 24'd12853891;
			7'd76: sync_array_muxed0 <= 28'd267580051;
			7'd77: sync_array_muxed0 <= 25'd16945811;
			7'd78: sync_array_muxed0 <= 23'd5629363;
			7'd79: sync_array_muxed0 <= 19'd270979;
			7'd80: sync_array_muxed0 <= 21'd1241747;
			7'd81: sync_array_muxed0 <= 32'd4261584099;
			7'd82: sync_array_muxed0 <= 24'd12853891;
			7'd83: sync_array_muxed0 <= 28'd267580051;
			7'd84: sync_array_muxed0 <= 25'd25334419;
			7'd85: sync_array_muxed0 <= 23'd5629363;
			7'd86: sync_array_muxed0 <= 12'd2067;
			7'd87: sync_array_muxed0 <= 19'd270979;
			7'd88: sync_array_muxed0 <= 21'd1241747;
			7'd89: sync_array_muxed0 <= 32'd4261584099;
			7'd90: sync_array_muxed0 <= 24'd12853891;
			7'd91: sync_array_muxed0 <= 28'd267580051;
			7'd92: sync_array_muxed0 <= 18'd168595;
			7'd93: sync_array_muxed0 <= 23'd5793843;
			7'd94: sync_array_muxed0 <= 19'd270979;
			7'd95: sync_array_muxed0 <= 21'd1241747;
			7'd96: sync_array_muxed0 <= 32'd4261584099;
			7'd97: sync_array_muxed0 <= 24'd12853891;
			7'd98: sync_array_muxed0 <= 28'd267580051;
			7'd99: sync_array_muxed0 <= 24'd8557203;
			7'd100: sync_array_muxed0 <= 23'd5793843;
			7'd101: sync_array_muxed0 <= 19'd270979;
			7'd102: sync_array_muxed0 <= 21'd1241747;
			7'd103: sync_array_muxed0 <= 32'd4261584099;
			7'd104: sync_array_muxed0 <= 24'd12853891;
			7'd105: sync_array_muxed0 <= 28'd267580051;
			7'd106: sync_array_muxed0 <= 25'd16945811;
			7'd107: sync_array_muxed0 <= 23'd5793843;
			7'd108: sync_array_muxed0 <= 19'd270979;
			7'd109: sync_array_muxed0 <= 21'd1241747;
			7'd110: sync_array_muxed0 <= 32'd4261584099;
			7'd111: sync_array_muxed0 <= 24'd12853891;
			7'd112: sync_array_muxed0 <= 28'd267580051;
			7'd113: sync_array_muxed0 <= 25'd25334419;
			7'd114: sync_array_muxed0 <= 23'd5793843;
			7'd115: sync_array_muxed0 <= 11'd1555;
			7'd116: sync_array_muxed0 <= 19'd270979;
			7'd117: sync_array_muxed0 <= 21'd1241747;
			7'd118: sync_array_muxed0 <= 32'd4261584099;
			7'd119: sync_array_muxed0 <= 24'd12853891;
			7'd120: sync_array_muxed0 <= 28'd267580051;
			7'd121: sync_array_muxed0 <= 18'd168595;
			7'd122: sync_array_muxed0 <= 23'd5662259;
			7'd123: sync_array_muxed0 <= 19'd270979;
			7'd124: sync_array_muxed0 <= 21'd1241747;
			7'd125: sync_array_muxed0 <= 32'd4261584099;
			7'd126: sync_array_muxed0 <= 24'd12853891;
			7'd127: sync_array_muxed0 <= 28'd267580051;
			8'd128: sync_array_muxed0 <= 24'd8557203;
			8'd129: sync_array_muxed0 <= 23'd5662259;
			8'd130: sync_array_muxed0 <= 19'd270979;
			8'd131: sync_array_muxed0 <= 21'd1241747;
			8'd132: sync_array_muxed0 <= 32'd4261584099;
			8'd133: sync_array_muxed0 <= 24'd12853891;
			8'd134: sync_array_muxed0 <= 28'd267580051;
			8'd135: sync_array_muxed0 <= 25'd16945811;
			8'd136: sync_array_muxed0 <= 23'd5662259;
			8'd137: sync_array_muxed0 <= 19'd270979;
			8'd138: sync_array_muxed0 <= 21'd1241747;
			8'd139: sync_array_muxed0 <= 32'd4261584099;
			8'd140: sync_array_muxed0 <= 24'd12853891;
			8'd141: sync_array_muxed0 <= 28'd267580051;
			8'd142: sync_array_muxed0 <= 25'd25334419;
			8'd143: sync_array_muxed0 <= 23'd5662259;
			8'd144: sync_array_muxed0 <= 24'd16090547;
			8'd145: sync_array_muxed0 <= 25'd17172019;
			8'd146: sync_array_muxed0 <= 19'd492819;
			8'd147: sync_array_muxed0 <= 11'd1719;
			8'd148: sync_array_muxed0 <= 19'd427667;
			8'd149: sync_array_muxed0 <= 26'd45440611;
			8'd150: sync_array_muxed0 <= 19'd270979;
			8'd151: sync_array_muxed0 <= 21'd1241747;
			8'd152: sync_array_muxed0 <= 32'd4261584099;
			8'd153: sync_array_muxed0 <= 24'd12853891;
			8'd154: sync_array_muxed0 <= 28'd267580051;
			8'd155: sync_array_muxed0 <= 23'd5670579;
			8'd156: sync_array_muxed0 <= 23'd5570595;
			8'd157: sync_array_muxed0 <= 24'd16085779;
			8'd158: sync_array_muxed0 <= 18'd202851;
			8'd159: sync_array_muxed0 <= 10'd695;
			8'd160: sync_array_muxed0 <= 23'd6455955;
			8'd161: sync_array_muxed0 <= 23'd5514275;
			8'd162: sync_array_muxed0 <= 21'd1377555;
			8'd163: sync_array_muxed0 <= 32'd4238340207;
			8'd164: sync_array_muxed0 <= 20'd525587;
			8'd165: sync_array_muxed0 <= 11'd1847;
			8'd166: sync_array_muxed0 <= 19'd460563;
			8'd167: sync_array_muxed0 <= 26'd46489187;
			8'd168: sync_array_muxed0 <= 19'd270979;
			8'd169: sync_array_muxed0 <= 21'd1241747;
			8'd170: sync_array_muxed0 <= 32'd4261584099;
			8'd171: sync_array_muxed0 <= 24'd12853891;
			8'd172: sync_array_muxed0 <= 28'd267580051;
			8'd173: sync_array_muxed0 <= 23'd5703475;
			8'd174: sync_array_muxed0 <= 23'd5570595;
			8'd175: sync_array_muxed0 <= 24'd16085779;
			8'd176: sync_array_muxed0 <= 18'd202851;
			8'd177: sync_array_muxed0 <= 10'd695;
			8'd178: sync_array_muxed0 <= 23'd6455955;
			8'd179: sync_array_muxed0 <= 23'd5514275;
			8'd180: sync_array_muxed0 <= 21'd1377555;
			8'd181: sync_array_muxed0 <= 32'd4238340207;
			8'd182: sync_array_muxed0 <= 19'd272259;
			8'd183: sync_array_muxed0 <= 21'd1570707;
			8'd184: sync_array_muxed0 <= 32'd4261911779;
			8'd185: sync_array_muxed0 <= 24'd12855171;
			8'd186: sync_array_muxed0 <= 28'd267909011;
			8'd187: sync_array_muxed0 <= 19'd272387;
			8'd188: sync_array_muxed0 <= 21'd1603603;
			8'd189: sync_array_muxed0 <= 32'd4261944547;
			8'd190: sync_array_muxed0 <= 24'd12855299;
			8'd191: sync_array_muxed0 <= 28'd267941907;
			8'd192: sync_array_muxed0 <= 28'd267843219;
			8'd193: sync_array_muxed0 <= 28'd267876115;
			8'd194: sync_array_muxed0 <= 24'd16157283;
			8'd195: sync_array_muxed0 <= 10'd695;
			8'd196: sync_array_muxed0 <= 25'd17990291;
			8'd197: sync_array_muxed0 <= 23'd5514275;
			8'd198: sync_array_muxed0 <= 28'd197132399;
			8'd199: sync_array_muxed0 <= 25'd17238627;
			8'd200: sync_array_muxed0 <= 10'd695;
			8'd201: sync_array_muxed0 <= 25'd19038867;
			8'd202: sync_array_muxed0 <= 23'd5514275;
			8'd203: sync_array_muxed0 <= 28'd176160879;
			8'd204: sync_array_muxed0 <= 10'd695;
			8'd205: sync_array_muxed0 <= 25'd20087443;
			8'd206: sync_array_muxed0 <= 23'd5514275;
			8'd207: sync_array_muxed0 <= 12'd3987;
			8'd208: sync_array_muxed0 <= 19'd270979;
			8'd209: sync_array_muxed0 <= 21'd1241747;
			8'd210: sync_array_muxed0 <= 32'd4261584099;
			8'd211: sync_array_muxed0 <= 24'd12853891;
			8'd212: sync_array_muxed0 <= 28'd267580051;
			8'd213: sync_array_muxed0 <= 18'd168595;
			8'd214: sync_array_muxed0 <= 23'd6287283;
			8'd215: sync_array_muxed0 <= 19'd270979;
			8'd216: sync_array_muxed0 <= 21'd1241747;
			8'd217: sync_array_muxed0 <= 32'd4261584099;
			8'd218: sync_array_muxed0 <= 24'd12853891;
			8'd219: sync_array_muxed0 <= 28'd267580051;
			8'd220: sync_array_muxed0 <= 24'd8557203;
			8'd221: sync_array_muxed0 <= 23'd6287283;
			8'd222: sync_array_muxed0 <= 19'd270979;
			8'd223: sync_array_muxed0 <= 21'd1241747;
			8'd224: sync_array_muxed0 <= 32'd4261584099;
			8'd225: sync_array_muxed0 <= 24'd12853891;
			8'd226: sync_array_muxed0 <= 28'd267580051;
			8'd227: sync_array_muxed0 <= 25'd16945811;
			8'd228: sync_array_muxed0 <= 23'd6287283;
			8'd229: sync_array_muxed0 <= 19'd270979;
			8'd230: sync_array_muxed0 <= 21'd1241747;
			8'd231: sync_array_muxed0 <= 32'd4261584099;
			8'd232: sync_array_muxed0 <= 24'd12853891;
			8'd233: sync_array_muxed0 <= 28'd267580051;
			8'd234: sync_array_muxed0 <= 25'd25334419;
			8'd235: sync_array_muxed0 <= 23'd6287283;
			8'd236: sync_array_muxed0 <= 31'd1073747127;
			8'd237: sync_array_muxed0 <= 19'd296083;
			8'd238: sync_array_muxed0 <= 19'd303747;
			8'd239: sync_array_muxed0 <= 26'd50000695;
			8'd240: sync_array_muxed0 <= 28'd134415123;
			8'd241: sync_array_muxed0 <= 23'd6455987;
			8'd242: sync_array_muxed0 <= 19'd303875;
			8'd243: sync_array_muxed0 <= 32'd4266880739;
			8'd244: sync_array_muxed0 <= 20'd1016039;
			default: sync_array_muxed0 <= 7'd111;
		endcase
		dummy_d_44 <= dummy_s;
	end
	reg dummy_d_45;
	always @(*) begin
		sync_array_muxed1 <= 31'd0;
		case (pifive_rom1_bus_adr >>> 2'd2)
			1'd0: sync_array_muxed1 <= 31'd1766222160;
			1'd1: sync_array_muxed1 <= 31'd1394632054;
			default: sync_array_muxed1 <= 15'd17263;
		endcase
		dummy_d_45 <= dummy_s;
	end
	always @(posedge sys_clk_1) begin
		pifive_iocontrol_irq <= 1'd0;
		pifive_iocontrol_ff10 <= io0_i;
		pifive_iocontrol_ff20 <= pifive_iocontrol_ff10;
		pifive_iocontrol_pad_i0 <= pifive_iocontrol_ff20;
		pifive_iocontrol_last0 <= pifive_iocontrol_pad_i0;
		if ((((~io0_oe & pifive_iocontrol_pad_i0) & ~pifive_iocontrol_last0) & pifive_iocontrol_irqmode0) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io0_oe & pifive_iocontrol_last0) & ~pifive_iocontrol_pad_i0) & pifive_iocontrol_irqmode0) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff11 <= io1_i;
		pifive_iocontrol_ff21 <= pifive_iocontrol_ff11;
		pifive_iocontrol_pad_i1 <= pifive_iocontrol_ff21;
		pifive_iocontrol_last1 <= pifive_iocontrol_pad_i1;
		if ((((~io1_oe & pifive_iocontrol_pad_i1) & ~pifive_iocontrol_last1) & pifive_iocontrol_irqmode1) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io1_oe & pifive_iocontrol_last1) & ~pifive_iocontrol_pad_i1) & pifive_iocontrol_irqmode1) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff12 <= io2_i;
		pifive_iocontrol_ff22 <= pifive_iocontrol_ff12;
		pifive_iocontrol_pad_i2 <= pifive_iocontrol_ff22;
		pifive_iocontrol_last2 <= pifive_iocontrol_pad_i2;
		if ((((~io2_oe & pifive_iocontrol_pad_i2) & ~pifive_iocontrol_last2) & pifive_iocontrol_irqmode2) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io2_oe & pifive_iocontrol_last2) & ~pifive_iocontrol_pad_i2) & pifive_iocontrol_irqmode2) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff13 <= io3_i;
		pifive_iocontrol_ff23 <= pifive_iocontrol_ff13;
		pifive_iocontrol_pad_i3 <= pifive_iocontrol_ff23;
		pifive_iocontrol_last3 <= pifive_iocontrol_pad_i3;
		if ((((~io3_oe & pifive_iocontrol_pad_i3) & ~pifive_iocontrol_last3) & pifive_iocontrol_irqmode3) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io3_oe & pifive_iocontrol_last3) & ~pifive_iocontrol_pad_i3) & pifive_iocontrol_irqmode3) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff14 <= io4_i;
		pifive_iocontrol_ff24 <= pifive_iocontrol_ff14;
		pifive_iocontrol_pad_i4 <= pifive_iocontrol_ff24;
		pifive_iocontrol_last4 <= pifive_iocontrol_pad_i4;
		if ((((~io4_oe & pifive_iocontrol_pad_i4) & ~pifive_iocontrol_last4) & pifive_iocontrol_irqmode4) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io4_oe & pifive_iocontrol_last4) & ~pifive_iocontrol_pad_i4) & pifive_iocontrol_irqmode4) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff15 <= io5_i;
		pifive_iocontrol_ff25 <= pifive_iocontrol_ff15;
		pifive_iocontrol_pad_i5 <= pifive_iocontrol_ff25;
		pifive_iocontrol_last5 <= pifive_iocontrol_pad_i5;
		if ((((~io5_oe & pifive_iocontrol_pad_i5) & ~pifive_iocontrol_last5) & pifive_iocontrol_irqmode5) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io5_oe & pifive_iocontrol_last5) & ~pifive_iocontrol_pad_i5) & pifive_iocontrol_irqmode5) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff16 <= io6_i;
		pifive_iocontrol_ff26 <= pifive_iocontrol_ff16;
		pifive_iocontrol_pad_i6 <= pifive_iocontrol_ff26;
		pifive_iocontrol_last6 <= pifive_iocontrol_pad_i6;
		if ((((~io6_oe & pifive_iocontrol_pad_i6) & ~pifive_iocontrol_last6) & pifive_iocontrol_irqmode6) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io6_oe & pifive_iocontrol_last6) & ~pifive_iocontrol_pad_i6) & pifive_iocontrol_irqmode6) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff17 <= io7_i;
		pifive_iocontrol_ff27 <= pifive_iocontrol_ff17;
		pifive_iocontrol_pad_i7 <= pifive_iocontrol_ff27;
		pifive_iocontrol_last7 <= pifive_iocontrol_pad_i7;
		if ((((~io7_oe & pifive_iocontrol_pad_i7) & ~pifive_iocontrol_last7) & pifive_iocontrol_irqmode7) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io7_oe & pifive_iocontrol_last7) & ~pifive_iocontrol_pad_i7) & pifive_iocontrol_irqmode7) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff18 <= io8_i;
		pifive_iocontrol_ff28 <= pifive_iocontrol_ff18;
		pifive_iocontrol_pad_i8 <= pifive_iocontrol_ff28;
		pifive_iocontrol_last8 <= pifive_iocontrol_pad_i8;
		if ((((~io8_oe & pifive_iocontrol_pad_i8) & ~pifive_iocontrol_last8) & pifive_iocontrol_irqmode8) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io8_oe & pifive_iocontrol_last8) & ~pifive_iocontrol_pad_i8) & pifive_iocontrol_irqmode8) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff19 <= io9_i;
		pifive_iocontrol_ff29 <= pifive_iocontrol_ff19;
		pifive_iocontrol_pad_i9 <= pifive_iocontrol_ff29;
		pifive_iocontrol_last9 <= pifive_iocontrol_pad_i9;
		if ((((~io9_oe & pifive_iocontrol_pad_i9) & ~pifive_iocontrol_last9) & pifive_iocontrol_irqmode9) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io9_oe & pifive_iocontrol_last9) & ~pifive_iocontrol_pad_i9) & pifive_iocontrol_irqmode9) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff110 <= io10_i;
		pifive_iocontrol_ff210 <= pifive_iocontrol_ff110;
		pifive_iocontrol_pad_i10 <= pifive_iocontrol_ff210;
		pifive_iocontrol_last10 <= pifive_iocontrol_pad_i10;
		if ((((~io10_oe & pifive_iocontrol_pad_i10) & ~pifive_iocontrol_last10) & pifive_iocontrol_irqmode10) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io10_oe & pifive_iocontrol_last10) & ~pifive_iocontrol_pad_i10) & pifive_iocontrol_irqmode10) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff111 <= io11_i;
		pifive_iocontrol_ff211 <= pifive_iocontrol_ff111;
		pifive_iocontrol_pad_i11 <= pifive_iocontrol_ff211;
		pifive_iocontrol_last11 <= pifive_iocontrol_pad_i11;
		if ((((~io11_oe & pifive_iocontrol_pad_i11) & ~pifive_iocontrol_last11) & pifive_iocontrol_irqmode11) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io11_oe & pifive_iocontrol_last11) & ~pifive_iocontrol_pad_i11) & pifive_iocontrol_irqmode11) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff112 <= io12_i;
		pifive_iocontrol_ff212 <= pifive_iocontrol_ff112;
		pifive_iocontrol_pad_i12 <= pifive_iocontrol_ff212;
		pifive_iocontrol_last12 <= pifive_iocontrol_pad_i12;
		if ((((~io12_oe & pifive_iocontrol_pad_i12) & ~pifive_iocontrol_last12) & pifive_iocontrol_irqmode12) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io12_oe & pifive_iocontrol_last12) & ~pifive_iocontrol_pad_i12) & pifive_iocontrol_irqmode12) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff113 <= io13_i;
		pifive_iocontrol_ff213 <= pifive_iocontrol_ff113;
		pifive_iocontrol_pad_i13 <= pifive_iocontrol_ff213;
		pifive_iocontrol_last13 <= pifive_iocontrol_pad_i13;
		if ((((~io13_oe & pifive_iocontrol_pad_i13) & ~pifive_iocontrol_last13) & pifive_iocontrol_irqmode13) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io13_oe & pifive_iocontrol_last13) & ~pifive_iocontrol_pad_i13) & pifive_iocontrol_irqmode13) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff114 <= io14_i;
		pifive_iocontrol_ff214 <= pifive_iocontrol_ff114;
		pifive_iocontrol_pad_i14 <= pifive_iocontrol_ff214;
		pifive_iocontrol_last14 <= pifive_iocontrol_pad_i14;
		if ((((~io14_oe & pifive_iocontrol_pad_i14) & ~pifive_iocontrol_last14) & pifive_iocontrol_irqmode14) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io14_oe & pifive_iocontrol_last14) & ~pifive_iocontrol_pad_i14) & pifive_iocontrol_irqmode14) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff115 <= io15_i;
		pifive_iocontrol_ff215 <= pifive_iocontrol_ff115;
		pifive_iocontrol_pad_i15 <= pifive_iocontrol_ff215;
		pifive_iocontrol_last15 <= pifive_iocontrol_pad_i15;
		if ((((~io15_oe & pifive_iocontrol_pad_i15) & ~pifive_iocontrol_last15) & pifive_iocontrol_irqmode15) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io15_oe & pifive_iocontrol_last15) & ~pifive_iocontrol_pad_i15) & pifive_iocontrol_irqmode15) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff116 <= io16_i;
		pifive_iocontrol_ff216 <= pifive_iocontrol_ff116;
		pifive_iocontrol_pad_i16 <= pifive_iocontrol_ff216;
		pifive_iocontrol_last16 <= pifive_iocontrol_pad_i16;
		if ((((~io16_oe & pifive_iocontrol_pad_i16) & ~pifive_iocontrol_last16) & pifive_iocontrol_irqmode16) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io16_oe & pifive_iocontrol_last16) & ~pifive_iocontrol_pad_i16) & pifive_iocontrol_irqmode16) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff117 <= io17_i;
		pifive_iocontrol_ff217 <= pifive_iocontrol_ff117;
		pifive_iocontrol_pad_i17 <= pifive_iocontrol_ff217;
		pifive_iocontrol_last17 <= pifive_iocontrol_pad_i17;
		if ((((~io17_oe & pifive_iocontrol_pad_i17) & ~pifive_iocontrol_last17) & pifive_iocontrol_irqmode17) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io17_oe & pifive_iocontrol_last17) & ~pifive_iocontrol_pad_i17) & pifive_iocontrol_irqmode17) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff118 <= io18_i;
		pifive_iocontrol_ff218 <= pifive_iocontrol_ff118;
		pifive_iocontrol_pad_i18 <= pifive_iocontrol_ff218;
		pifive_iocontrol_last18 <= pifive_iocontrol_pad_i18;
		if ((((~io18_oe & pifive_iocontrol_pad_i18) & ~pifive_iocontrol_last18) & pifive_iocontrol_irqmode18) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io18_oe & pifive_iocontrol_last18) & ~pifive_iocontrol_pad_i18) & pifive_iocontrol_irqmode18) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_ff119 <= io19_i;
		pifive_iocontrol_ff219 <= pifive_iocontrol_ff119;
		pifive_iocontrol_pad_i19 <= pifive_iocontrol_ff219;
		pifive_iocontrol_last19 <= pifive_iocontrol_pad_i19;
		if ((((~io19_oe & pifive_iocontrol_pad_i19) & ~pifive_iocontrol_last19) & pifive_iocontrol_irqmode19) == 1'd1)
			pifive_iocontrol_irq <= 1'd1;
		if ((((~io19_oe & pifive_iocontrol_last19) & ~pifive_iocontrol_pad_i19) & pifive_iocontrol_irqmode19) == 2'd2)
			pifive_iocontrol_irq <= 1'd1;
		pifive_iocontrol_bus_ack <= 1'd0;
		pifive_iocontrol_bus_err <= 1'd0;
		if ((pifive_iocontrol_bus_stb & pifive_iocontrol_bus_cyc) & ~pifive_iocontrol_bus_ack) begin
			pifive_iocontrol_bus_ack <= 1'd1;
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 1'd0) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable0, pifive_iocontrol_select0, pifive_iocontrol_irqmode0, io0_oe, io0_o, pifive_iocontrol_pad_i0}, 1'd0, pifive_iocontrol_enable0, pifive_iocontrol_select0, pifive_iocontrol_irqmode0, 5'd0, pifive_iocontrol_gpio_oe0, pifive_iocontrol_gpio_out0, pifive_iocontrol_gpio_in0};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out0 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe0 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode0 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select0 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable0 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 1'd1) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable1, pifive_iocontrol_select1, pifive_iocontrol_irqmode1, io1_oe, io1_o, pifive_iocontrol_pad_i1}, 1'd0, pifive_iocontrol_enable1, pifive_iocontrol_select1, pifive_iocontrol_irqmode1, 5'd0, pifive_iocontrol_gpio_oe1, pifive_iocontrol_gpio_out1, pifive_iocontrol_gpio_in1};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out1 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe1 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode1 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select1 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable1 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 2'd2) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable2, pifive_iocontrol_select2, pifive_iocontrol_irqmode2, io2_oe, io2_o, pifive_iocontrol_pad_i2}, 1'd0, pifive_iocontrol_enable2, pifive_iocontrol_select2, pifive_iocontrol_irqmode2, 5'd0, pifive_iocontrol_gpio_oe2, pifive_iocontrol_gpio_out2, pifive_iocontrol_gpio_in2};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out2 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe2 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode2 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select2 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable2 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 2'd3) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable3, pifive_iocontrol_select3, pifive_iocontrol_irqmode3, io3_oe, io3_o, pifive_iocontrol_pad_i3}, 1'd0, pifive_iocontrol_enable3, pifive_iocontrol_select3, pifive_iocontrol_irqmode3, 5'd0, pifive_iocontrol_gpio_oe3, pifive_iocontrol_gpio_out3, pifive_iocontrol_gpio_in3};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out3 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe3 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode3 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select3 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable3 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 3'd4) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable4, pifive_iocontrol_select4, pifive_iocontrol_irqmode4, io4_oe, io4_o, pifive_iocontrol_pad_i4}, 1'd0, pifive_iocontrol_enable4, pifive_iocontrol_select4, pifive_iocontrol_irqmode4, 5'd0, pifive_iocontrol_gpio_oe4, pifive_iocontrol_gpio_out4, pifive_iocontrol_gpio_in4};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out4 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe4 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode4 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select4 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable4 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 3'd5) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable5, pifive_iocontrol_select5, pifive_iocontrol_irqmode5, io5_oe, io5_o, pifive_iocontrol_pad_i5}, 1'd0, pifive_iocontrol_enable5, pifive_iocontrol_select5, pifive_iocontrol_irqmode5, 5'd0, pifive_iocontrol_gpio_oe5, pifive_iocontrol_gpio_out5, pifive_iocontrol_gpio_in5};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out5 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe5 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode5 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select5 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable5 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 3'd6) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable6, pifive_iocontrol_select6, pifive_iocontrol_irqmode6, io6_oe, io6_o, pifive_iocontrol_pad_i6}, 1'd0, pifive_iocontrol_enable6, pifive_iocontrol_select6, pifive_iocontrol_irqmode6, 5'd0, pifive_iocontrol_gpio_oe6, pifive_iocontrol_gpio_out6, pifive_iocontrol_gpio_in6};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out6 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe6 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode6 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select6 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable6 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 3'd7) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable7, pifive_iocontrol_select7, pifive_iocontrol_irqmode7, io7_oe, io7_o, pifive_iocontrol_pad_i7}, 1'd0, pifive_iocontrol_enable7, pifive_iocontrol_select7, pifive_iocontrol_irqmode7, 5'd0, pifive_iocontrol_gpio_oe7, pifive_iocontrol_gpio_out7, pifive_iocontrol_gpio_in7};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out7 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe7 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode7 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select7 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable7 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 4'd8) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable8, pifive_iocontrol_select8, pifive_iocontrol_irqmode8, io8_oe, io8_o, pifive_iocontrol_pad_i8}, 1'd0, pifive_iocontrol_enable8, pifive_iocontrol_select8, pifive_iocontrol_irqmode8, 5'd0, pifive_iocontrol_gpio_oe8, pifive_iocontrol_gpio_out8, pifive_iocontrol_gpio_in8};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out8 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe8 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode8 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select8 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable8 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 4'd9) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable9, pifive_iocontrol_select9, pifive_iocontrol_irqmode9, io9_oe, io9_o, pifive_iocontrol_pad_i9}, 1'd0, pifive_iocontrol_enable9, pifive_iocontrol_select9, pifive_iocontrol_irqmode9, 5'd0, pifive_iocontrol_gpio_oe9, pifive_iocontrol_gpio_out9, pifive_iocontrol_gpio_in9};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out9 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe9 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode9 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select9 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable9 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 4'd10) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable10, pifive_iocontrol_select10, pifive_iocontrol_irqmode10, io10_oe, io10_o, pifive_iocontrol_pad_i10}, 1'd0, pifive_iocontrol_enable10, pifive_iocontrol_select10, pifive_iocontrol_irqmode10, 5'd0, pifive_iocontrol_gpio_oe10, pifive_iocontrol_gpio_out10, pifive_iocontrol_gpio_in10};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out10 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe10 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode10 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select10 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable10 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 4'd11) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable11, pifive_iocontrol_select11, pifive_iocontrol_irqmode11, io11_oe, io11_o, pifive_iocontrol_pad_i11}, 1'd0, pifive_iocontrol_enable11, pifive_iocontrol_select11, pifive_iocontrol_irqmode11, 5'd0, pifive_iocontrol_gpio_oe11, pifive_iocontrol_gpio_out11, pifive_iocontrol_gpio_in11};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out11 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe11 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode11 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select11 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable11 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 4'd12) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable12, pifive_iocontrol_select12, pifive_iocontrol_irqmode12, io12_oe, io12_o, pifive_iocontrol_pad_i12}, 1'd0, pifive_iocontrol_enable12, pifive_iocontrol_select12, pifive_iocontrol_irqmode12, 5'd0, pifive_iocontrol_gpio_oe12, pifive_iocontrol_gpio_out12, pifive_iocontrol_gpio_in12};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out12 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe12 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode12 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select12 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable12 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 4'd13) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable13, pifive_iocontrol_select13, pifive_iocontrol_irqmode13, io13_oe, io13_o, pifive_iocontrol_pad_i13}, 1'd0, pifive_iocontrol_enable13, pifive_iocontrol_select13, pifive_iocontrol_irqmode13, 5'd0, pifive_iocontrol_gpio_oe13, pifive_iocontrol_gpio_out13, pifive_iocontrol_gpio_in13};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out13 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe13 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode13 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select13 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable13 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 4'd14) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable14, pifive_iocontrol_select14, pifive_iocontrol_irqmode14, io14_oe, io14_o, pifive_iocontrol_pad_i14}, 1'd0, pifive_iocontrol_enable14, pifive_iocontrol_select14, pifive_iocontrol_irqmode14, 5'd0, pifive_iocontrol_gpio_oe14, pifive_iocontrol_gpio_out14, pifive_iocontrol_gpio_in14};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out14 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe14 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode14 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select14 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable14 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 4'd15) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable15, pifive_iocontrol_select15, pifive_iocontrol_irqmode15, io15_oe, io15_o, pifive_iocontrol_pad_i15}, 1'd0, pifive_iocontrol_enable15, pifive_iocontrol_select15, pifive_iocontrol_irqmode15, 5'd0, pifive_iocontrol_gpio_oe15, pifive_iocontrol_gpio_out15, pifive_iocontrol_gpio_in15};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out15 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe15 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode15 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select15 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable15 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 5'd16) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable16, pifive_iocontrol_select16, pifive_iocontrol_irqmode16, io16_oe, io16_o, pifive_iocontrol_pad_i16}, 1'd0, pifive_iocontrol_enable16, pifive_iocontrol_select16, pifive_iocontrol_irqmode16, 5'd0, pifive_iocontrol_gpio_oe16, pifive_iocontrol_gpio_out16, pifive_iocontrol_gpio_in16};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out16 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe16 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode16 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select16 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable16 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 5'd17) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable17, pifive_iocontrol_select17, pifive_iocontrol_irqmode17, io17_oe, io17_o, pifive_iocontrol_pad_i17}, 1'd0, pifive_iocontrol_enable17, pifive_iocontrol_select17, pifive_iocontrol_irqmode17, 5'd0, pifive_iocontrol_gpio_oe17, pifive_iocontrol_gpio_out17, pifive_iocontrol_gpio_in17};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out17 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe17 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode17 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select17 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable17 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 5'd18) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable18, pifive_iocontrol_select18, pifive_iocontrol_irqmode18, io18_oe, io18_o, pifive_iocontrol_pad_i18}, 1'd0, pifive_iocontrol_enable18, pifive_iocontrol_select18, pifive_iocontrol_irqmode18, 5'd0, pifive_iocontrol_gpio_oe18, pifive_iocontrol_gpio_out18, pifive_iocontrol_gpio_in18};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out18 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe18 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode18 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select18 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable18 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
			if ((pifive_iocontrol_bus_adr >>> 2'd2) == 5'd19) begin
				pifive_iocontrol_bus_dat_r <= {{4'd0, 2'd0, pifive_iocontrol_enable19, pifive_iocontrol_select19, pifive_iocontrol_irqmode19, io19_oe, io19_o, pifive_iocontrol_pad_i19}, 1'd0, pifive_iocontrol_enable19, pifive_iocontrol_select19, pifive_iocontrol_irqmode19, 5'd0, pifive_iocontrol_gpio_oe19, pifive_iocontrol_gpio_out19, pifive_iocontrol_gpio_in19};
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[0]) begin
					pifive_iocontrol_gpio_out19 <= pifive_iocontrol_bus_dat_w[1];
					pifive_iocontrol_gpio_oe19 <= pifive_iocontrol_bus_dat_w[2];
				end
				if (pifive_iocontrol_bus_we & pifive_iocontrol_bus_sel[1]) begin
					pifive_iocontrol_irqmode19 <= pifive_iocontrol_bus_dat_w[9:8];
					pifive_iocontrol_select19 <= pifive_iocontrol_bus_dat_w[13:10];
					pifive_iocontrol_enable19 <= pifive_iocontrol_bus_dat_w[14];
				end
			end
		end
		pifive_iocontrol_debug_bus_ack <= 1'd0;
		pifive_iocontrol_debug_bus_err <= 1'd0;
		if ((pifive_iocontrol_debug_bus_stb & pifive_iocontrol_debug_bus_cyc) & ~pifive_iocontrol_debug_bus_ack) begin
			pifive_iocontrol_debug_bus_ack <= 1'd1;
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 1'd0)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable0, pifive_iocontrol_select0, pifive_iocontrol_irqmode0, io0_oe, io0_o, pifive_iocontrol_pad_i0}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 1'd1)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable1, pifive_iocontrol_select1, pifive_iocontrol_irqmode1, io1_oe, io1_o, pifive_iocontrol_pad_i1}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 2'd2)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable2, pifive_iocontrol_select2, pifive_iocontrol_irqmode2, io2_oe, io2_o, pifive_iocontrol_pad_i2}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 2'd3)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable3, pifive_iocontrol_select3, pifive_iocontrol_irqmode3, io3_oe, io3_o, pifive_iocontrol_pad_i3}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 3'd4)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable4, pifive_iocontrol_select4, pifive_iocontrol_irqmode4, io4_oe, io4_o, pifive_iocontrol_pad_i4}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 3'd5)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable5, pifive_iocontrol_select5, pifive_iocontrol_irqmode5, io5_oe, io5_o, pifive_iocontrol_pad_i5}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 3'd6)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable6, pifive_iocontrol_select6, pifive_iocontrol_irqmode6, io6_oe, io6_o, pifive_iocontrol_pad_i6}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 3'd7)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable7, pifive_iocontrol_select7, pifive_iocontrol_irqmode7, io7_oe, io7_o, pifive_iocontrol_pad_i7}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 4'd8)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable8, pifive_iocontrol_select8, pifive_iocontrol_irqmode8, io8_oe, io8_o, pifive_iocontrol_pad_i8}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 4'd9)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable9, pifive_iocontrol_select9, pifive_iocontrol_irqmode9, io9_oe, io9_o, pifive_iocontrol_pad_i9}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 4'd10)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable10, pifive_iocontrol_select10, pifive_iocontrol_irqmode10, io10_oe, io10_o, pifive_iocontrol_pad_i10}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 4'd11)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable11, pifive_iocontrol_select11, pifive_iocontrol_irqmode11, io11_oe, io11_o, pifive_iocontrol_pad_i11}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 4'd12)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable12, pifive_iocontrol_select12, pifive_iocontrol_irqmode12, io12_oe, io12_o, pifive_iocontrol_pad_i12}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 4'd13)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable13, pifive_iocontrol_select13, pifive_iocontrol_irqmode13, io13_oe, io13_o, pifive_iocontrol_pad_i13}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 4'd14)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable14, pifive_iocontrol_select14, pifive_iocontrol_irqmode14, io14_oe, io14_o, pifive_iocontrol_pad_i14}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 4'd15)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable15, pifive_iocontrol_select15, pifive_iocontrol_irqmode15, io15_oe, io15_o, pifive_iocontrol_pad_i15}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 5'd16)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable16, pifive_iocontrol_select16, pifive_iocontrol_irqmode16, io16_oe, io16_o, pifive_iocontrol_pad_i16}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 5'd17)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable17, pifive_iocontrol_select17, pifive_iocontrol_irqmode17, io17_oe, io17_o, pifive_iocontrol_pad_i17}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 5'd18)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable18, pifive_iocontrol_select18, pifive_iocontrol_irqmode18, io18_oe, io18_o, pifive_iocontrol_pad_i18}};
			if ((pifive_iocontrol_debug_bus_adr >>> 2'd2) == 5'd19)
				pifive_iocontrol_debug_bus_dat_r <= {16'd0, {4'd0, 2'd0, pifive_iocontrol_enable19, pifive_iocontrol_select19, pifive_iocontrol_irqmode19, io19_oe, io19_o, pifive_iocontrol_pad_i19}};
		end
		if (pifive_spi0_data_out_valid)
			pifive_spi0_data_out_reg <= pifive_spi0_data_out;
		pifive_spi0_bus_ack <= 1'd0;
		pifive_spi0_bus_err <= 1'd0;
		pifive_spi0_irq <= 1'd0;
		pifive_spi0_start_write <= 1'd0;
		pifive_spi0_last_out_valid <= pifive_spi0_data_out_valid;
		if (pifive_spi0_data_out_valid & ~pifive_spi0_last_out_valid)
			pifive_spi0_irq <= 1'd1;
		if ((pifive_spi0_bus_cyc & pifive_spi0_bus_stb) & ~pifive_spi0_bus_ack) begin
			pifive_spi0_bus_ack <= 1'd1;
			if ((pifive_spi0_bus_adr >>> 2'd2) == 1'd0) begin
				if (pifive_spi0_bus_we & pifive_spi0_bus_sel[0])
					pifive_spi0_divider[7:0] <= pifive_spi0_bus_dat_w[7:0];
				if (pifive_spi0_bus_we & pifive_spi0_bus_sel[1])
					pifive_spi0_divider[15:8] <= pifive_spi0_bus_dat_w[15:8];
				if (pifive_spi0_bus_we & pifive_spi0_bus_sel[2])
					pifive_spi0_mode <= pifive_spi0_bus_dat_w[17:16];
				pifive_spi0_bus_dat_r <= {pifive_spi0_ready, pifive_spi0_mode, pifive_spi0_divider};
			end
		end
		if ((pifive_spi0_bus_adr >>> 2'd2) == 1'd1) begin
			if (pifive_spi0_bus_we & pifive_spi0_bus_sel[0]) begin
				pifive_spi0_data_write <= pifive_spi0_bus_dat_w[7:0];
				pifive_spi0_start_write <= 1'd1;
			end
			pifive_spi0_bus_dat_r <= pifive_spi0_data_write;
		end
		if ((pifive_spi0_bus_adr >>> 2'd2) == 2'd2)
			pifive_spi0_bus_dat_r <= pifive_spi0_data_out_reg;
		if (pifive_spi1_data_out_valid)
			pifive_spi1_data_out_reg <= pifive_spi1_data_out;
		pifive_spi1_bus_ack <= 1'd0;
		pifive_spi1_bus_err <= 1'd0;
		pifive_spi1_irq <= 1'd0;
		pifive_spi1_start_write <= 1'd0;
		pifive_spi1_last_out_valid <= pifive_spi1_data_out_valid;
		if (pifive_spi1_data_out_valid & ~pifive_spi1_last_out_valid)
			pifive_spi1_irq <= 1'd1;
		if ((pifive_spi1_bus_cyc & pifive_spi1_bus_stb) & ~pifive_spi1_bus_ack) begin
			pifive_spi1_bus_ack <= 1'd1;
			if ((pifive_spi1_bus_adr >>> 2'd2) == 1'd0) begin
				if (pifive_spi1_bus_we & pifive_spi1_bus_sel[0])
					pifive_spi1_divider[7:0] <= pifive_spi1_bus_dat_w[7:0];
				if (pifive_spi1_bus_we & pifive_spi1_bus_sel[1])
					pifive_spi1_divider[15:8] <= pifive_spi1_bus_dat_w[15:8];
				if (pifive_spi1_bus_we & pifive_spi1_bus_sel[2])
					pifive_spi1_mode <= pifive_spi1_bus_dat_w[17:16];
				pifive_spi1_bus_dat_r <= {pifive_spi1_ready, pifive_spi1_mode, pifive_spi1_divider};
			end
		end
		if ((pifive_spi1_bus_adr >>> 2'd2) == 1'd1) begin
			if (pifive_spi1_bus_we & pifive_spi1_bus_sel[0]) begin
				pifive_spi1_data_write <= pifive_spi1_bus_dat_w[7:0];
				pifive_spi1_start_write <= 1'd1;
			end
			pifive_spi1_bus_dat_r <= pifive_spi1_data_write;
		end
		if ((pifive_spi1_bus_adr >>> 2'd2) == 2'd2)
			pifive_spi1_bus_dat_r <= pifive_spi1_data_out_reg;
		pifive_i2c_last_stb <= pifive_i2c_bus_stb;
		pifive_i2c_last_ack <= pifive_i2c_bus_ack;
		pifive_pwm0_bus_ack <= 1'd0;
		pifive_pwm0_bus_err <= 1'd0;
		pifive_pwm0_bus_dat_r <= 1'd0;
		if ((pifive_pwm0_bus_stb & pifive_pwm0_bus_cyc) & ~pifive_pwm0_bus_ack) begin
			pifive_pwm0_bus_ack <= 1'd1;
			if ((pifive_pwm0_bus_adr >>> 2'd2) == 1'd0) begin
				if (pifive_pwm0_bus_we & pifive_pwm0_bus_sel[0])
					pifive_pwm0_width[7:0] <= pifive_pwm0_bus_dat_w[7:0];
				if (pifive_pwm0_bus_we & pifive_pwm0_bus_sel[1])
					pifive_pwm0_width[15:8] <= pifive_pwm0_bus_dat_w[15:8];
				if (pifive_pwm0_bus_we & pifive_pwm0_bus_sel[2])
					pifive_pwm0_width[23:16] <= pifive_pwm0_bus_dat_w[23:16];
				if (pifive_pwm0_bus_we & pifive_pwm0_bus_sel[3])
					pifive_pwm0_width[31:24] <= pifive_pwm0_bus_dat_w[31:24];
				pifive_pwm0_bus_dat_r <= pifive_pwm0_width;
			end
			if ((pifive_pwm0_bus_adr >>> 2'd2) == 1'd1) begin
				if (pifive_pwm0_bus_we & pifive_pwm0_bus_sel[0])
					pifive_pwm0_period[7:0] <= pifive_pwm0_bus_dat_w[7:0];
				if (pifive_pwm0_bus_we & pifive_pwm0_bus_sel[1])
					pifive_pwm0_period[15:8] <= pifive_pwm0_bus_dat_w[15:8];
				if (pifive_pwm0_bus_we & pifive_pwm0_bus_sel[2])
					pifive_pwm0_period[23:16] <= pifive_pwm0_bus_dat_w[23:16];
				if (pifive_pwm0_bus_we & pifive_pwm0_bus_sel[3])
					pifive_pwm0_period[31:24] <= pifive_pwm0_bus_dat_w[31:24];
				pifive_pwm0_bus_dat_r <= pifive_pwm0_period;
			end
		end
		pifive_pwm0_ctr <= pifive_pwm0_ctr + 1'd1;
		if (pifive_pwm0_ctr >= (pifive_pwm0_period - 1'd1))
			pifive_pwm0_ctr <= 1'd0;
		pifive_pwm1_bus_ack <= 1'd0;
		pifive_pwm1_bus_err <= 1'd0;
		pifive_pwm1_bus_dat_r <= 1'd0;
		if ((pifive_pwm1_bus_stb & pifive_pwm1_bus_cyc) & ~pifive_pwm1_bus_ack) begin
			pifive_pwm1_bus_ack <= 1'd1;
			if ((pifive_pwm1_bus_adr >>> 2'd2) == 1'd0) begin
				if (pifive_pwm1_bus_we & pifive_pwm1_bus_sel[0])
					pifive_pwm1_width[7:0] <= pifive_pwm1_bus_dat_w[7:0];
				if (pifive_pwm1_bus_we & pifive_pwm1_bus_sel[1])
					pifive_pwm1_width[15:8] <= pifive_pwm1_bus_dat_w[15:8];
				if (pifive_pwm1_bus_we & pifive_pwm1_bus_sel[2])
					pifive_pwm1_width[23:16] <= pifive_pwm1_bus_dat_w[23:16];
				if (pifive_pwm1_bus_we & pifive_pwm1_bus_sel[3])
					pifive_pwm1_width[31:24] <= pifive_pwm1_bus_dat_w[31:24];
				pifive_pwm1_bus_dat_r <= pifive_pwm1_width;
			end
			if ((pifive_pwm1_bus_adr >>> 2'd2) == 1'd1) begin
				if (pifive_pwm1_bus_we & pifive_pwm1_bus_sel[0])
					pifive_pwm1_period[7:0] <= pifive_pwm1_bus_dat_w[7:0];
				if (pifive_pwm1_bus_we & pifive_pwm1_bus_sel[1])
					pifive_pwm1_period[15:8] <= pifive_pwm1_bus_dat_w[15:8];
				if (pifive_pwm1_bus_we & pifive_pwm1_bus_sel[2])
					pifive_pwm1_period[23:16] <= pifive_pwm1_bus_dat_w[23:16];
				if (pifive_pwm1_bus_we & pifive_pwm1_bus_sel[3])
					pifive_pwm1_period[31:24] <= pifive_pwm1_bus_dat_w[31:24];
				pifive_pwm1_bus_dat_r <= pifive_pwm1_period;
			end
		end
		pifive_pwm1_ctr <= pifive_pwm1_ctr + 1'd1;
		if (pifive_pwm1_ctr >= (pifive_pwm1_period - 1'd1))
			pifive_pwm1_ctr <= 1'd0;
		pifive_pwm2_bus_ack <= 1'd0;
		pifive_pwm2_bus_err <= 1'd0;
		pifive_pwm2_bus_dat_r <= 1'd0;
		if ((pifive_pwm2_bus_stb & pifive_pwm2_bus_cyc) & ~pifive_pwm2_bus_ack) begin
			pifive_pwm2_bus_ack <= 1'd1;
			if ((pifive_pwm2_bus_adr >>> 2'd2) == 1'd0) begin
				if (pifive_pwm2_bus_we & pifive_pwm2_bus_sel[0])
					pifive_pwm2_width[7:0] <= pifive_pwm2_bus_dat_w[7:0];
				if (pifive_pwm2_bus_we & pifive_pwm2_bus_sel[1])
					pifive_pwm2_width[15:8] <= pifive_pwm2_bus_dat_w[15:8];
				if (pifive_pwm2_bus_we & pifive_pwm2_bus_sel[2])
					pifive_pwm2_width[23:16] <= pifive_pwm2_bus_dat_w[23:16];
				if (pifive_pwm2_bus_we & pifive_pwm2_bus_sel[3])
					pifive_pwm2_width[31:24] <= pifive_pwm2_bus_dat_w[31:24];
				pifive_pwm2_bus_dat_r <= pifive_pwm2_width;
			end
			if ((pifive_pwm2_bus_adr >>> 2'd2) == 1'd1) begin
				if (pifive_pwm2_bus_we & pifive_pwm2_bus_sel[0])
					pifive_pwm2_period[7:0] <= pifive_pwm2_bus_dat_w[7:0];
				if (pifive_pwm2_bus_we & pifive_pwm2_bus_sel[1])
					pifive_pwm2_period[15:8] <= pifive_pwm2_bus_dat_w[15:8];
				if (pifive_pwm2_bus_we & pifive_pwm2_bus_sel[2])
					pifive_pwm2_period[23:16] <= pifive_pwm2_bus_dat_w[23:16];
				if (pifive_pwm2_bus_we & pifive_pwm2_bus_sel[3])
					pifive_pwm2_period[31:24] <= pifive_pwm2_bus_dat_w[31:24];
				pifive_pwm2_bus_dat_r <= pifive_pwm2_period;
			end
		end
		pifive_pwm2_ctr <= pifive_pwm2_ctr + 1'd1;
		if (pifive_pwm2_ctr >= (pifive_pwm2_period - 1'd1))
			pifive_pwm2_ctr <= 1'd0;
		pifive_pwm3_bus_ack <= 1'd0;
		pifive_pwm3_bus_err <= 1'd0;
		pifive_pwm3_bus_dat_r <= 1'd0;
		if ((pifive_pwm3_bus_stb & pifive_pwm3_bus_cyc) & ~pifive_pwm3_bus_ack) begin
			pifive_pwm3_bus_ack <= 1'd1;
			if ((pifive_pwm3_bus_adr >>> 2'd2) == 1'd0) begin
				if (pifive_pwm3_bus_we & pifive_pwm3_bus_sel[0])
					pifive_pwm3_width[7:0] <= pifive_pwm3_bus_dat_w[7:0];
				if (pifive_pwm3_bus_we & pifive_pwm3_bus_sel[1])
					pifive_pwm3_width[15:8] <= pifive_pwm3_bus_dat_w[15:8];
				if (pifive_pwm3_bus_we & pifive_pwm3_bus_sel[2])
					pifive_pwm3_width[23:16] <= pifive_pwm3_bus_dat_w[23:16];
				if (pifive_pwm3_bus_we & pifive_pwm3_bus_sel[3])
					pifive_pwm3_width[31:24] <= pifive_pwm3_bus_dat_w[31:24];
				pifive_pwm3_bus_dat_r <= pifive_pwm3_width;
			end
			if ((pifive_pwm3_bus_adr >>> 2'd2) == 1'd1) begin
				if (pifive_pwm3_bus_we & pifive_pwm3_bus_sel[0])
					pifive_pwm3_period[7:0] <= pifive_pwm3_bus_dat_w[7:0];
				if (pifive_pwm3_bus_we & pifive_pwm3_bus_sel[1])
					pifive_pwm3_period[15:8] <= pifive_pwm3_bus_dat_w[15:8];
				if (pifive_pwm3_bus_we & pifive_pwm3_bus_sel[2])
					pifive_pwm3_period[23:16] <= pifive_pwm3_bus_dat_w[23:16];
				if (pifive_pwm3_bus_we & pifive_pwm3_bus_sel[3])
					pifive_pwm3_period[31:24] <= pifive_pwm3_bus_dat_w[31:24];
				pifive_pwm3_bus_dat_r <= pifive_pwm3_period;
			end
		end
		pifive_pwm3_ctr <= pifive_pwm3_ctr + 1'd1;
		if (pifive_pwm3_ctr >= (pifive_pwm3_period - 1'd1))
			pifive_pwm3_ctr <= 1'd0;
		pifive_pwm4_bus_ack <= 1'd0;
		pifive_pwm4_bus_err <= 1'd0;
		pifive_pwm4_bus_dat_r <= 1'd0;
		if ((pifive_pwm4_bus_stb & pifive_pwm4_bus_cyc) & ~pifive_pwm4_bus_ack) begin
			pifive_pwm4_bus_ack <= 1'd1;
			if ((pifive_pwm4_bus_adr >>> 2'd2) == 1'd0) begin
				if (pifive_pwm4_bus_we & pifive_pwm4_bus_sel[0])
					pifive_pwm4_width[7:0] <= pifive_pwm4_bus_dat_w[7:0];
				if (pifive_pwm4_bus_we & pifive_pwm4_bus_sel[1])
					pifive_pwm4_width[15:8] <= pifive_pwm4_bus_dat_w[15:8];
				if (pifive_pwm4_bus_we & pifive_pwm4_bus_sel[2])
					pifive_pwm4_width[23:16] <= pifive_pwm4_bus_dat_w[23:16];
				if (pifive_pwm4_bus_we & pifive_pwm4_bus_sel[3])
					pifive_pwm4_width[31:24] <= pifive_pwm4_bus_dat_w[31:24];
				pifive_pwm4_bus_dat_r <= pifive_pwm4_width;
			end
			if ((pifive_pwm4_bus_adr >>> 2'd2) == 1'd1) begin
				if (pifive_pwm4_bus_we & pifive_pwm4_bus_sel[0])
					pifive_pwm4_period[7:0] <= pifive_pwm4_bus_dat_w[7:0];
				if (pifive_pwm4_bus_we & pifive_pwm4_bus_sel[1])
					pifive_pwm4_period[15:8] <= pifive_pwm4_bus_dat_w[15:8];
				if (pifive_pwm4_bus_we & pifive_pwm4_bus_sel[2])
					pifive_pwm4_period[23:16] <= pifive_pwm4_bus_dat_w[23:16];
				if (pifive_pwm4_bus_we & pifive_pwm4_bus_sel[3])
					pifive_pwm4_period[31:24] <= pifive_pwm4_bus_dat_w[31:24];
				pifive_pwm4_bus_dat_r <= pifive_pwm4_period;
			end
		end
		pifive_pwm4_ctr <= pifive_pwm4_ctr + 1'd1;
		if (pifive_pwm4_ctr >= (pifive_pwm4_period - 1'd1))
			pifive_pwm4_ctr <= 1'd0;
		pifive_pwm5_bus_ack <= 1'd0;
		pifive_pwm5_bus_err <= 1'd0;
		pifive_pwm5_bus_dat_r <= 1'd0;
		if ((pifive_pwm5_bus_stb & pifive_pwm5_bus_cyc) & ~pifive_pwm5_bus_ack) begin
			pifive_pwm5_bus_ack <= 1'd1;
			if ((pifive_pwm5_bus_adr >>> 2'd2) == 1'd0) begin
				if (pifive_pwm5_bus_we & pifive_pwm5_bus_sel[0])
					pifive_pwm5_width[7:0] <= pifive_pwm5_bus_dat_w[7:0];
				if (pifive_pwm5_bus_we & pifive_pwm5_bus_sel[1])
					pifive_pwm5_width[15:8] <= pifive_pwm5_bus_dat_w[15:8];
				if (pifive_pwm5_bus_we & pifive_pwm5_bus_sel[2])
					pifive_pwm5_width[23:16] <= pifive_pwm5_bus_dat_w[23:16];
				if (pifive_pwm5_bus_we & pifive_pwm5_bus_sel[3])
					pifive_pwm5_width[31:24] <= pifive_pwm5_bus_dat_w[31:24];
				pifive_pwm5_bus_dat_r <= pifive_pwm5_width;
			end
			if ((pifive_pwm5_bus_adr >>> 2'd2) == 1'd1) begin
				if (pifive_pwm5_bus_we & pifive_pwm5_bus_sel[0])
					pifive_pwm5_period[7:0] <= pifive_pwm5_bus_dat_w[7:0];
				if (pifive_pwm5_bus_we & pifive_pwm5_bus_sel[1])
					pifive_pwm5_period[15:8] <= pifive_pwm5_bus_dat_w[15:8];
				if (pifive_pwm5_bus_we & pifive_pwm5_bus_sel[2])
					pifive_pwm5_period[23:16] <= pifive_pwm5_bus_dat_w[23:16];
				if (pifive_pwm5_bus_we & pifive_pwm5_bus_sel[3])
					pifive_pwm5_period[31:24] <= pifive_pwm5_bus_dat_w[31:24];
				pifive_pwm5_bus_dat_r <= pifive_pwm5_period;
			end
		end
		pifive_pwm5_ctr <= pifive_pwm5_ctr + 1'd1;
		if (pifive_pwm5_ctr >= (pifive_pwm5_period - 1'd1))
			pifive_pwm5_ctr <= 1'd0;
		pifive_rom0_bus_ack <= (pifive_rom0_bus_cyc & pifive_rom0_bus_stb) & ~pifive_rom0_bus_ack;
		pifive_rom0_bus_dat_r <= sync_array_muxed0;
		pifive_interface0_ack0 <= 1'd0;
		if ((pifive_interface0_cyc0 & pifive_interface0_stb0) & ~pifive_interface0_ack0)
			pifive_interface0_ack0 <= 1'd1;
		pifive_interface1_ack0 <= 1'd0;
		if ((pifive_interface1_cyc0 & pifive_interface1_stb0) & ~pifive_interface1_ack0)
			pifive_interface1_ack0 <= 1'd1;
		pifive_rom1_bus_ack <= (pifive_rom1_bus_cyc & pifive_rom1_bus_stb) & ~pifive_rom1_bus_ack;
		pifive_rom1_bus_dat_r <= sync_array_muxed1;
		pifive_uptimetimer_bus_ack <= 1'd0;
		pifive_uptimetimer_bus_err <= 1'd0;
		pifive_uptimetimer_bus_dat_r <= 1'd0;
		if ((pifive_uptimetimer_bus_stb & pifive_uptimetimer_bus_cyc) & ~pifive_uptimetimer_bus_ack) begin
			pifive_uptimetimer_bus_ack <= 1'd1;
			if ((pifive_uptimetimer_bus_adr >>> 2'd2) == 1'd0)
				pifive_uptimetimer_bus_dat_r <= pifive_uptimetimer_ctr[31:0];
			if ((pifive_uptimetimer_bus_adr >>> 2'd2) == 1'd1)
				pifive_uptimetimer_bus_dat_r <= pifive_uptimetimer_ctr[63:32];
		end
		pifive_uptimetimer_ctr <= pifive_uptimetimer_ctr + 1'd1;
		pifive_timer0_irq <= 1'd0;
		if (pifive_timer0_running) begin
			pifive_timer0_ctr <= pifive_timer0_ctr - 1'd1;
			if ((pifive_timer0_ctr == 1'd1) | (pifive_timer0_ctr == 1'd0)) begin
				pifive_timer0_triggered <= 1'd1;
				pifive_timer0_irq <= 1'd1;
				if (pifive_timer0_reload != 1'd0)
					pifive_timer0_ctr <= pifive_timer0_reload;
				else
					pifive_timer0_ctr <= 1'd0;
			end
		end
		else begin
			pifive_timer0_ctr <= 1'd0;
			pifive_timer0_triggered <= 1'd0;
		end
		pifive_timer0_bus_ack <= 1'd0;
		pifive_timer0_bus_err <= 1'd0;
		pifive_timer0_bus_dat_r <= 1'd0;
		if ((pifive_timer0_bus_stb & pifive_timer0_bus_cyc) & ~pifive_timer0_bus_ack) begin
			pifive_timer0_bus_ack <= 1'd1;
			if ((pifive_timer0_bus_adr >>> 2'd2) == 1'd0)
				pifive_timer0_bus_dat_r <= pifive_timer0_ctr;
			if ((pifive_timer0_bus_adr >>> 2'd2) == 1'd1) begin
				if (pifive_timer0_bus_we & pifive_timer0_bus_sel[0])
					pifive_timer0_reload[7:0] <= pifive_timer0_bus_dat_w[7:0];
				if (pifive_timer0_bus_we & pifive_timer0_bus_sel[1])
					pifive_timer0_reload[15:8] <= pifive_timer0_bus_dat_w[15:8];
				if (pifive_timer0_bus_we & pifive_timer0_bus_sel[2])
					pifive_timer0_reload[23:16] <= pifive_timer0_bus_dat_w[23:16];
				if (pifive_timer0_bus_we & pifive_timer0_bus_sel[3])
					pifive_timer0_reload[31:24] <= pifive_timer0_bus_dat_w[31:24];
				pifive_timer0_bus_dat_r <= pifive_timer0_reload;
			end
			if ((pifive_timer0_bus_adr >>> 2'd2) == 2'd2) begin
				if (pifive_timer0_bus_we & pifive_timer0_bus_sel[0])
					pifive_timer0_load[7:0] <= pifive_timer0_bus_dat_w[7:0];
				if (pifive_timer0_bus_we & pifive_timer0_bus_sel[1])
					pifive_timer0_load[15:8] <= pifive_timer0_bus_dat_w[15:8];
				if (pifive_timer0_bus_we & pifive_timer0_bus_sel[2])
					pifive_timer0_load[23:16] <= pifive_timer0_bus_dat_w[23:16];
				if (pifive_timer0_bus_we & pifive_timer0_bus_sel[3])
					pifive_timer0_load[31:24] <= pifive_timer0_bus_dat_w[31:24];
				pifive_timer0_bus_dat_r <= pifive_timer0_load;
			end
			if ((pifive_timer0_bus_adr >>> 2'd2) == 2'd3) begin
				if (pifive_timer0_bus_we & pifive_timer0_bus_sel[0]) begin
					pifive_timer0_running <= pifive_timer0_bus_dat_w[0];
					if (pifive_timer0_bus_dat_w[0])
						pifive_timer0_ctr <= pifive_timer0_load;
				end
				pifive_timer0_bus_dat_r <= pifive_timer0_running;
			end
			if ((pifive_timer0_bus_adr >>> 2'd2) == 3'd4) begin
				if (((pifive_timer0_bus_we & pifive_timer0_bus_sel[0]) & pifive_timer0_bus_dat_w[0]) == 1'd0)
					pifive_timer0_triggered <= 1'd0;
				pifive_timer0_bus_dat_r <= pifive_timer0_triggered;
			end
		end
		pifive_timer1_irq <= 1'd0;
		if (pifive_timer1_running) begin
			pifive_timer1_ctr <= pifive_timer1_ctr - 1'd1;
			if ((pifive_timer1_ctr == 1'd1) | (pifive_timer1_ctr == 1'd0)) begin
				pifive_timer1_triggered <= 1'd1;
				pifive_timer1_irq <= 1'd1;
				if (pifive_timer1_reload != 1'd0)
					pifive_timer1_ctr <= pifive_timer1_reload;
				else
					pifive_timer1_ctr <= 1'd0;
			end
		end
		else begin
			pifive_timer1_ctr <= 1'd0;
			pifive_timer1_triggered <= 1'd0;
		end
		pifive_timer1_bus_ack <= 1'd0;
		pifive_timer1_bus_err <= 1'd0;
		pifive_timer1_bus_dat_r <= 1'd0;
		if ((pifive_timer1_bus_stb & pifive_timer1_bus_cyc) & ~pifive_timer1_bus_ack) begin
			pifive_timer1_bus_ack <= 1'd1;
			if ((pifive_timer1_bus_adr >>> 2'd2) == 1'd0)
				pifive_timer1_bus_dat_r <= pifive_timer1_ctr;
			if ((pifive_timer1_bus_adr >>> 2'd2) == 1'd1) begin
				if (pifive_timer1_bus_we & pifive_timer1_bus_sel[0])
					pifive_timer1_reload[7:0] <= pifive_timer1_bus_dat_w[7:0];
				if (pifive_timer1_bus_we & pifive_timer1_bus_sel[1])
					pifive_timer1_reload[15:8] <= pifive_timer1_bus_dat_w[15:8];
				if (pifive_timer1_bus_we & pifive_timer1_bus_sel[2])
					pifive_timer1_reload[23:16] <= pifive_timer1_bus_dat_w[23:16];
				if (pifive_timer1_bus_we & pifive_timer1_bus_sel[3])
					pifive_timer1_reload[31:24] <= pifive_timer1_bus_dat_w[31:24];
				pifive_timer1_bus_dat_r <= pifive_timer1_reload;
			end
			if ((pifive_timer1_bus_adr >>> 2'd2) == 2'd2) begin
				if (pifive_timer1_bus_we & pifive_timer1_bus_sel[0])
					pifive_timer1_load[7:0] <= pifive_timer1_bus_dat_w[7:0];
				if (pifive_timer1_bus_we & pifive_timer1_bus_sel[1])
					pifive_timer1_load[15:8] <= pifive_timer1_bus_dat_w[15:8];
				if (pifive_timer1_bus_we & pifive_timer1_bus_sel[2])
					pifive_timer1_load[23:16] <= pifive_timer1_bus_dat_w[23:16];
				if (pifive_timer1_bus_we & pifive_timer1_bus_sel[3])
					pifive_timer1_load[31:24] <= pifive_timer1_bus_dat_w[31:24];
				pifive_timer1_bus_dat_r <= pifive_timer1_load;
			end
			if ((pifive_timer1_bus_adr >>> 2'd2) == 2'd3) begin
				if (pifive_timer1_bus_we & pifive_timer1_bus_sel[0]) begin
					pifive_timer1_running <= pifive_timer1_bus_dat_w[0];
					if (pifive_timer1_bus_dat_w[0])
						pifive_timer1_ctr <= pifive_timer1_load;
				end
				pifive_timer1_bus_dat_r <= pifive_timer1_running;
			end
			if ((pifive_timer1_bus_adr >>> 2'd2) == 3'd4) begin
				if (((pifive_timer1_bus_we & pifive_timer1_bus_sel[0]) & pifive_timer1_bus_dat_w[0]) == 1'd0)
					pifive_timer1_triggered <= 1'd0;
				pifive_timer1_bus_dat_r <= pifive_timer1_triggered;
			end
		end
		pifive_wishbonedebugbus_last_stb <= pifive_wishbonedebugbus_bus_stb;
		if (pifive_wishbonedebugbus_bus_cyc & pifive_wishbonedebugbus_bus_stb)
			if (~pifive_wishbonedebugbus_last_stb)
				pifive_wishbonedebugbus_ctr <= 1'd0;
			else
				pifive_wishbonedebugbus_ctr <= pifive_wishbonedebugbus_ctr + 1'd1;
		pifive_wishbonedebugbus_bus_sel <= 4'd15;
		pifive_periph_bridge_slave_sel_r <= pifive_periph_bridge_slave_sel;
		case (pifive_arbiter0_grant)
			1'd0:
				if (~pifive_arbiter0_request[0])
					if (pifive_arbiter0_request[1])
						pifive_arbiter0_grant <= 1'd1;
					else if (pifive_arbiter0_request[2])
						pifive_arbiter0_grant <= 2'd2;
			1'd1:
				if (~pifive_arbiter0_request[1])
					if (pifive_arbiter0_request[2])
						pifive_arbiter0_grant <= 2'd2;
					else if (pifive_arbiter0_request[0])
						pifive_arbiter0_grant <= 1'd0;
			2'd2:
				if (~pifive_arbiter0_request[2])
					if (pifive_arbiter0_request[0])
						pifive_arbiter0_grant <= 1'd0;
					else if (pifive_arbiter0_request[1])
						pifive_arbiter0_grant <= 1'd1;
		endcase
		case (pifive_arbiter1_grant)
			1'd0:
				if (~pifive_arbiter1_request[0])
					if (pifive_arbiter1_request[1])
						pifive_arbiter1_grant <= 1'd1;
					else if (pifive_arbiter1_request[2])
						pifive_arbiter1_grant <= 2'd2;
			1'd1:
				if (~pifive_arbiter1_request[1])
					if (pifive_arbiter1_request[2])
						pifive_arbiter1_grant <= 2'd2;
					else if (pifive_arbiter1_request[0])
						pifive_arbiter1_grant <= 1'd0;
			2'd2:
				if (~pifive_arbiter1_request[2])
					if (pifive_arbiter1_request[0])
						pifive_arbiter1_grant <= 1'd0;
					else if (pifive_arbiter1_request[1])
						pifive_arbiter1_grant <= 1'd1;
		endcase
		case (pifive_arbiter2_grant)
			1'd0:
				if (~pifive_arbiter2_request[0])
					if (pifive_arbiter2_request[1])
						pifive_arbiter2_grant <= 1'd1;
					else if (pifive_arbiter2_request[2])
						pifive_arbiter2_grant <= 2'd2;
			1'd1:
				if (~pifive_arbiter2_request[1])
					if (pifive_arbiter2_request[2])
						pifive_arbiter2_grant <= 2'd2;
					else if (pifive_arbiter2_request[0])
						pifive_arbiter2_grant <= 1'd0;
			2'd2:
				if (~pifive_arbiter2_request[2])
					if (pifive_arbiter2_request[0])
						pifive_arbiter2_grant <= 1'd0;
					else if (pifive_arbiter2_request[1])
						pifive_arbiter2_grant <= 1'd1;
		endcase
		pifive_debug_interconnect_slave_sel_r <= pifive_debug_interconnect_slave_sel;
		if (sys_rst_1) begin
			pifive_iocontrol_bus_ack <= 1'd0;
			pifive_iocontrol_bus_err <= 1'd0;
			pifive_iocontrol_debug_bus_ack <= 1'd0;
			pifive_iocontrol_debug_bus_err <= 1'd0;
			pifive_iocontrol_irq <= 1'd0;
			pifive_iocontrol_last0 <= 1'd0;
			pifive_iocontrol_gpio_out0 <= 1'd0;
			pifive_iocontrol_gpio_oe0 <= 1'd0;
			pifive_iocontrol_irqmode0 <= 2'd0;
			pifive_iocontrol_select0 <= 4'd0;
			pifive_iocontrol_enable0 <= 1'd0;
			pifive_iocontrol_last1 <= 1'd0;
			pifive_iocontrol_gpio_out1 <= 1'd0;
			pifive_iocontrol_gpio_oe1 <= 1'd0;
			pifive_iocontrol_irqmode1 <= 2'd0;
			pifive_iocontrol_select1 <= 4'd0;
			pifive_iocontrol_enable1 <= 1'd0;
			pifive_iocontrol_last2 <= 1'd0;
			pifive_iocontrol_gpio_out2 <= 1'd0;
			pifive_iocontrol_gpio_oe2 <= 1'd0;
			pifive_iocontrol_irqmode2 <= 2'd0;
			pifive_iocontrol_select2 <= 4'd0;
			pifive_iocontrol_enable2 <= 1'd0;
			pifive_iocontrol_last3 <= 1'd0;
			pifive_iocontrol_gpio_out3 <= 1'd0;
			pifive_iocontrol_gpio_oe3 <= 1'd0;
			pifive_iocontrol_irqmode3 <= 2'd0;
			pifive_iocontrol_select3 <= 4'd0;
			pifive_iocontrol_enable3 <= 1'd0;
			pifive_iocontrol_last4 <= 1'd0;
			pifive_iocontrol_gpio_out4 <= 1'd0;
			pifive_iocontrol_gpio_oe4 <= 1'd0;
			pifive_iocontrol_irqmode4 <= 2'd0;
			pifive_iocontrol_select4 <= 4'd0;
			pifive_iocontrol_enable4 <= 1'd0;
			pifive_iocontrol_last5 <= 1'd0;
			pifive_iocontrol_gpio_out5 <= 1'd0;
			pifive_iocontrol_gpio_oe5 <= 1'd0;
			pifive_iocontrol_irqmode5 <= 2'd0;
			pifive_iocontrol_select5 <= 4'd0;
			pifive_iocontrol_enable5 <= 1'd0;
			pifive_iocontrol_last6 <= 1'd0;
			pifive_iocontrol_gpio_out6 <= 1'd0;
			pifive_iocontrol_gpio_oe6 <= 1'd0;
			pifive_iocontrol_irqmode6 <= 2'd0;
			pifive_iocontrol_select6 <= 4'd0;
			pifive_iocontrol_enable6 <= 1'd0;
			pifive_iocontrol_last7 <= 1'd0;
			pifive_iocontrol_gpio_out7 <= 1'd0;
			pifive_iocontrol_gpio_oe7 <= 1'd0;
			pifive_iocontrol_irqmode7 <= 2'd0;
			pifive_iocontrol_select7 <= 4'd0;
			pifive_iocontrol_enable7 <= 1'd0;
			pifive_iocontrol_last8 <= 1'd0;
			pifive_iocontrol_gpio_out8 <= 1'd0;
			pifive_iocontrol_gpio_oe8 <= 1'd0;
			pifive_iocontrol_irqmode8 <= 2'd0;
			pifive_iocontrol_select8 <= 4'd0;
			pifive_iocontrol_enable8 <= 1'd0;
			pifive_iocontrol_last9 <= 1'd0;
			pifive_iocontrol_gpio_out9 <= 1'd0;
			pifive_iocontrol_gpio_oe9 <= 1'd0;
			pifive_iocontrol_irqmode9 <= 2'd0;
			pifive_iocontrol_select9 <= 4'd0;
			pifive_iocontrol_enable9 <= 1'd0;
			pifive_iocontrol_last10 <= 1'd0;
			pifive_iocontrol_gpio_out10 <= 1'd0;
			pifive_iocontrol_gpio_oe10 <= 1'd0;
			pifive_iocontrol_irqmode10 <= 2'd0;
			pifive_iocontrol_select10 <= 4'd0;
			pifive_iocontrol_enable10 <= 1'd0;
			pifive_iocontrol_last11 <= 1'd0;
			pifive_iocontrol_gpio_out11 <= 1'd0;
			pifive_iocontrol_gpio_oe11 <= 1'd0;
			pifive_iocontrol_irqmode11 <= 2'd0;
			pifive_iocontrol_select11 <= 4'd0;
			pifive_iocontrol_enable11 <= 1'd0;
			pifive_iocontrol_last12 <= 1'd0;
			pifive_iocontrol_gpio_out12 <= 1'd0;
			pifive_iocontrol_gpio_oe12 <= 1'd0;
			pifive_iocontrol_irqmode12 <= 2'd0;
			pifive_iocontrol_select12 <= 4'd0;
			pifive_iocontrol_enable12 <= 1'd0;
			pifive_iocontrol_last13 <= 1'd0;
			pifive_iocontrol_gpio_out13 <= 1'd0;
			pifive_iocontrol_gpio_oe13 <= 1'd0;
			pifive_iocontrol_irqmode13 <= 2'd0;
			pifive_iocontrol_select13 <= 4'd0;
			pifive_iocontrol_enable13 <= 1'd0;
			pifive_iocontrol_last14 <= 1'd0;
			pifive_iocontrol_gpio_out14 <= 1'd0;
			pifive_iocontrol_gpio_oe14 <= 1'd0;
			pifive_iocontrol_irqmode14 <= 2'd0;
			pifive_iocontrol_select14 <= 4'd0;
			pifive_iocontrol_enable14 <= 1'd0;
			pifive_iocontrol_last15 <= 1'd0;
			pifive_iocontrol_gpio_out15 <= 1'd0;
			pifive_iocontrol_gpio_oe15 <= 1'd0;
			pifive_iocontrol_irqmode15 <= 2'd0;
			pifive_iocontrol_select15 <= 4'd0;
			pifive_iocontrol_enable15 <= 1'd0;
			pifive_iocontrol_last16 <= 1'd0;
			pifive_iocontrol_gpio_out16 <= 1'd0;
			pifive_iocontrol_gpio_oe16 <= 1'd0;
			pifive_iocontrol_irqmode16 <= 2'd0;
			pifive_iocontrol_select16 <= 4'd0;
			pifive_iocontrol_enable16 <= 1'd0;
			pifive_iocontrol_last17 <= 1'd0;
			pifive_iocontrol_gpio_out17 <= 1'd0;
			pifive_iocontrol_gpio_oe17 <= 1'd0;
			pifive_iocontrol_irqmode17 <= 2'd0;
			pifive_iocontrol_select17 <= 4'd0;
			pifive_iocontrol_enable17 <= 1'd0;
			pifive_iocontrol_last18 <= 1'd0;
			pifive_iocontrol_gpio_out18 <= 1'd0;
			pifive_iocontrol_gpio_oe18 <= 1'd0;
			pifive_iocontrol_irqmode18 <= 2'd0;
			pifive_iocontrol_select18 <= 4'd0;
			pifive_iocontrol_enable18 <= 1'd0;
			pifive_iocontrol_last19 <= 1'd0;
			pifive_iocontrol_gpio_out19 <= 1'd0;
			pifive_iocontrol_gpio_oe19 <= 1'd0;
			pifive_iocontrol_irqmode19 <= 2'd0;
			pifive_iocontrol_select19 <= 4'd0;
			pifive_iocontrol_enable19 <= 1'd0;
			pifive_spi0_bus_ack <= 1'd0;
			pifive_spi0_bus_err <= 1'd0;
			pifive_spi0_irq <= 1'd0;
			pifive_spi0_data_out_reg <= 8'd0;
			pifive_spi0_data_write <= 8'd0;
			pifive_spi0_start_write <= 1'd0;
			pifive_spi0_mode <= 2'd0;
			pifive_spi0_divider <= 16'd25;
			pifive_spi0_last_out_valid <= 1'd0;
			pifive_spi1_bus_ack <= 1'd0;
			pifive_spi1_bus_err <= 1'd0;
			pifive_spi1_irq <= 1'd0;
			pifive_spi1_data_out_reg <= 8'd0;
			pifive_spi1_data_write <= 8'd0;
			pifive_spi1_start_write <= 1'd0;
			pifive_spi1_mode <= 2'd0;
			pifive_spi1_divider <= 16'd25;
			pifive_spi1_last_out_valid <= 1'd0;
			pifive_i2c_last_stb <= 1'd0;
			pifive_i2c_last_ack <= 1'd0;
			pifive_pwm0_bus_ack <= 1'd0;
			pifive_pwm0_bus_err <= 1'd0;
			pifive_pwm0_ctr <= 32'd0;
			pifive_pwm0_width <= 32'd0;
			pifive_pwm0_period <= 32'd0;
			pifive_pwm1_bus_ack <= 1'd0;
			pifive_pwm1_bus_err <= 1'd0;
			pifive_pwm1_ctr <= 32'd0;
			pifive_pwm1_width <= 32'd0;
			pifive_pwm1_period <= 32'd0;
			pifive_pwm2_bus_ack <= 1'd0;
			pifive_pwm2_bus_err <= 1'd0;
			pifive_pwm2_ctr <= 32'd0;
			pifive_pwm2_width <= 32'd0;
			pifive_pwm2_period <= 32'd0;
			pifive_pwm3_bus_ack <= 1'd0;
			pifive_pwm3_bus_err <= 1'd0;
			pifive_pwm3_ctr <= 32'd0;
			pifive_pwm3_width <= 32'd0;
			pifive_pwm3_period <= 32'd0;
			pifive_pwm4_bus_ack <= 1'd0;
			pifive_pwm4_bus_err <= 1'd0;
			pifive_pwm4_ctr <= 32'd0;
			pifive_pwm4_width <= 32'd0;
			pifive_pwm4_period <= 32'd0;
			pifive_pwm5_bus_ack <= 1'd0;
			pifive_pwm5_bus_err <= 1'd0;
			pifive_pwm5_ctr <= 32'd0;
			pifive_pwm5_width <= 32'd0;
			pifive_pwm5_period <= 32'd0;
			pifive_rom0_bus_ack <= 1'd0;
			pifive_interface0_ack0 <= 1'd0;
			pifive_interface1_ack0 <= 1'd0;
			pifive_rom1_bus_ack <= 1'd0;
			pifive_uptimetimer_bus_ack <= 1'd0;
			pifive_uptimetimer_bus_err <= 1'd0;
			pifive_uptimetimer_ctr <= 64'd0;
			pifive_timer0_irq <= 1'd0;
			pifive_timer0_bus_ack <= 1'd0;
			pifive_timer0_bus_err <= 1'd0;
			pifive_timer0_ctr <= 32'd0;
			pifive_timer0_running <= 1'd0;
			pifive_timer0_triggered <= 1'd0;
			pifive_timer0_reload <= 32'd0;
			pifive_timer0_load <= 32'd0;
			pifive_timer1_irq <= 1'd0;
			pifive_timer1_bus_ack <= 1'd0;
			pifive_timer1_bus_err <= 1'd0;
			pifive_timer1_ctr <= 32'd0;
			pifive_timer1_running <= 1'd0;
			pifive_timer1_triggered <= 1'd0;
			pifive_timer1_reload <= 32'd0;
			pifive_timer1_load <= 32'd0;
			pifive_wishbonedebugbus_ctr <= 16'd0;
			pifive_wishbonedebugbus_last_stb <= 1'd0;
			pifive_periph_bridge_slave_sel_r <= 17'd0;
			pifive_arbiter0_grant <= 2'd0;
			pifive_arbiter1_grant <= 2'd0;
			pifive_arbiter2_grant <= 2'd0;
			pifive_debug_interconnect_slave_sel_r <= 1'd0;
		end
	end
	spi_controller spi_controller(
		.i_CPHA(pifive_spi0_mode[0]),
		.i_CPOL(pifive_spi0_mode[1]),
		.i_Clk(sys_clk_1),
		.i_Rst(sys_rst_1),
		.i_SPI_MISO(pifive1),
		.i_TX_Byte(pifive_spi0_data_write),
		.i_TX_DV(pifive_spi0_start_write),
		.i_divider(pifive_spi0_divider),
		.o_RX_Byte(pifive_spi0_data_out),
		.o_RX_DV(pifive_spi0_data_out_valid),
		.o_SPI_Clk(pifive2),
		.o_SPI_MOSI(pifive0),
		.o_TX_Ready(pifive_spi0_ready)
	);
	spi_controller spi_controller_1(
		.i_CPHA(pifive_spi1_mode[0]),
		.i_CPOL(pifive_spi1_mode[1]),
		.i_Clk(sys_clk_1),
		.i_Rst(sys_rst_1),
		.i_SPI_MISO(pifive4),
		.i_TX_Byte(pifive_spi1_data_write),
		.i_TX_DV(pifive_spi1_start_write),
		.i_divider(pifive_spi1_divider),
		.o_RX_Byte(pifive_spi1_data_out),
		.o_RX_DV(pifive_spi1_data_out_valid),
		.o_SPI_Clk(pifive5),
		.o_SPI_MOSI(pifive3),
		.o_TX_Ready(pifive_spi1_ready)
	);
	wbuart #(
		.ADDR_CONFIG(3'd4),
		.ADDR_READ(4'd12),
		.ADDR_STATUS(1'd0),
		.ADDR_WRITE(4'd8),
		.FIFO_DEPTH(4'd8)
	) wbuart(
		.i_clk(sys_clk_1),
		.i_rst(sys_rst_1),
		.i_rx(pifive6),
		.i_wb_addr(pifive_uart0_bus_adr),
		.i_wb_cyc(pifive_uart0_bus_cyc),
		.i_wb_data(pifive_uart0_bus_dat_w),
		.i_wb_stb(pifive_uart0_bus_stb),
		.i_wb_we(pifive_uart0_bus_we & pifive_uart0_bus_sel[0]),
		.o_tx(pifive7),
		.o_wb_ack(pifive_uart0_bus_ack),
		.o_wb_data(pifive_uart0_bus_dat_r),
		.o_wb_err(pifive_uart0_bus_err)
	);
	wbuart #(
		.ADDR_CONFIG(3'd4),
		.ADDR_READ(4'd12),
		.ADDR_STATUS(1'd0),
		.ADDR_WRITE(4'd8),
		.FIFO_DEPTH(4'd8)
	) wbuart_1(
		.i_clk(sys_clk_1),
		.i_rst(sys_rst_1),
		.i_rx(pifive8),
		.i_wb_addr(pifive_uart1_bus_adr),
		.i_wb_cyc(pifive_uart1_bus_cyc),
		.i_wb_data(pifive_uart1_bus_dat_w),
		.i_wb_stb(pifive_uart1_bus_stb),
		.i_wb_we(pifive_uart1_bus_we & pifive_uart1_bus_sel[0]),
		.o_tx(pifive9),
		.o_wb_ack(pifive_uart1_bus_ack),
		.o_wb_data(pifive_uart1_bus_dat_r),
		.o_wb_err(pifive_uart1_bus_err)
	);
	i2c_master_wbs_16 #(
		.CMD_FIFO(1'd1),
		.CMD_FIFO_ADDR_WIDTH(2'd3),
		.DEFAULT_PRESCALE(6'd32),
		.FIXED_PRESCALE(1'd0),
		.READ_FIFO(1'd1),
		.READ_FIFO_ADDR_WIDTH(2'd3),
		.WRITE_FIFO(1'd1),
		.WRITE_FIFO_ADDR_WIDTH(2'd3)
	) i2c_master_wbs_16(
		.clk(sys_clk_1),
		.i2c_scl_i(pifive13),
		.i2c_sda_i(pifive10),
		.rst(sys_rst_1),
		.wbs_adr_i(pifive_i2c_bus_adr >>> 1'd1),
		.wbs_cyc_i(pifive_i2c_bus_cyc),
		.wbs_dat_i(pifive_i2c_bus_dat_w),
		.wbs_sel_i(pifive_i2c_bus_sel),
		.wbs_stb_i(pifive_i2c_bus_stb & (~pifive_i2c_last_stb | pifive_i2c_last_ack)),
		.wbs_we_i(pifive_i2c_bus_we & (pifive_i2c_bus_sel[1] | pifive_i2c_bus_sel[0])),
		.i2c_scl_o(pifive14),
		.i2c_scl_t(pifive15),
		.i2c_sda_o(pifive11),
		.i2c_sda_t(pifive12),
		.wbs_ack_o(pifive_i2c_bus_ack),
		.wbs_dat_o(pifive_i2c_bus_dat_r)
	);
	reg [31:0] mem [0:3];
	reg [1:0] memadr;
	always @(posedge sys_clk_1) begin
		if (pifive_sram0_we[0])
			mem[pifive_sram0_adr][7:0] <= pifive_sram0_dat_w[7:0];
		if (pifive_sram0_we[1])
			mem[pifive_sram0_adr][15:8] <= pifive_sram0_dat_w[15:8];
		if (pifive_sram0_we[2])
			mem[pifive_sram0_adr][23:16] <= pifive_sram0_dat_w[23:16];
		if (pifive_sram0_we[3])
			mem[pifive_sram0_adr][31:24] <= pifive_sram0_dat_w[31:24];
		memadr <= pifive_sram0_adr;
	end
	assign pifive_sram0_dat_r = mem[memadr];
	reg [31:0] mem_1 [0:3];
	reg [1:0] memadr_1;
	always @(posedge sys_clk_1) begin
		if (pifive_sram1_we[0])
			mem_1[pifive_sram1_adr][7:0] <= pifive_sram1_dat_w[7:0];
		if (pifive_sram1_we[1])
			mem_1[pifive_sram1_adr][15:8] <= pifive_sram1_dat_w[15:8];
		if (pifive_sram1_we[2])
			mem_1[pifive_sram1_adr][23:16] <= pifive_sram1_dat_w[23:16];
		if (pifive_sram1_we[3])
			mem_1[pifive_sram1_adr][31:24] <= pifive_sram1_dat_w[31:24];
		memadr_1 <= pifive_sram1_adr;
	end
	assign pifive_sram1_dat_r = mem_1[memadr_1];
	wbdbgbus #(
		.CLK_FREQ(25'd25000000),
		.DROP_CLKS(25'd25000000),
		.FIFO_DEPTH(5'd16),
		.UART_BAUD(17'd115200)
	) wbdbgbus(
		.i_clk(sys_clk_1),
		.i_interrupt_1(1'd0),
		.i_interrupt_2(1'd0),
		.i_interrupt_3(1'd0),
		.i_interrupt_4(1'd0),
		.i_rx(uart_main_dbg_rx),
		.i_wb_ack(pifive_wishbonedebugbus_bus_ack),
		.i_wb_data(pifive_wishbonedebugbus_bus_dat_r),
		.i_wb_err(pifive_wishbonedebugbus_bus_err),
		.i_wb_stall(1'd0),
		.o_tx(uart_main_dbg_tx),
		.o_wb_addr(pifive_wishbonedebugbus_bus_adr),
		.o_wb_cyc(pifive_wishbonedebugbus_bus_cyc),
		.o_wb_data(pifive_wishbonedebugbus_bus_dat_w),
		.o_wb_stb(pifive_wishbonedebugbus_bus_stb),
		.o_wb_we(pifive_wishbonedebugbus_bus_we)
	);
	cpu #(
		.USE_BARREL_SHIFTER(1'd1),
		.WISHBONE_PIPELINED(1'd0)
	) cpu(
		.data_wb_ack(pifive_data_bus_ack),
		.data_wb_data_rd(pifive_data_bus_dat_r),
		.data_wb_err(pifive_data_bus_err),
		.i_clk(sys_clk_1),
		.i_init_pc(pifive_init_pc),
		.i_rst(sys_rst_1 | pifive_cpu_reset),
		.i_stall_in(pifive_stall_in),
		.instr_wb_ack(pifive_instr_bus_ack),
		.instr_wb_data_rd(pifive_instr_bus_dat_r),
		.instr_wb_err(pifive_instr_bus_err),
		.data_wb_addr(pifive_data_bus_adr),
		.data_wb_cyc(pifive_data_bus_cyc),
		.data_wb_data_wr(pifive_data_bus_dat_w),
		.data_wb_sel(pifive_data_bus_sel),
		.data_wb_stb(pifive_data_bus_stb),
		.data_wb_we(pifive_data_bus_we),
		.instr_wb_addr(pifive_instr_bus_adr),
		.instr_wb_cyc(pifive_instr_bus_cyc),
		.instr_wb_data_wr(pifive_instr_bus_dat_w),
		.instr_wb_sel(pifive_instr_bus_sel),
		.instr_wb_stb(pifive_instr_bus_stb),
		.instr_wb_we(pifive_instr_bus_we),
		.o_pc_out(pifive_pc_out),
		.o_stall_out(pifive_stall_out)
	);
endmodule
`default_nettype none
module wbram (
	wb_cyc,
	wb_stb,
	wb_we,
	wb_sel,
	wb_addr,
	wb_data_wr,
	wb_ack,
	wb_err,
	wb_data_rd,
	i_clk,
	i_rst
);
	parameter BASE_ADDR = 32'h00000000;
	parameter DEPTH_WORDS = 512;
	parameter [1023:0] INIT_FILE = "";
	localparam ADDR_WIDTH = $clog2(DEPTH_WORDS);
	parameter LATENCY = 0;
	parameter WIDTH_OVERRIDE = 32;
	localparam wb_N = 32;
	localparam wb_NUM_BYTES = wb_N / 8;
	input wire wb_cyc;
	input wire wb_stb;
	input wire wb_we;
	input wire [wb_NUM_BYTES - 1:0] wb_sel;
	input wire [wb_N - 1:0] wb_addr;
	input wire [wb_N - 1:0] wb_data_wr;
	output reg wb_ack;
	output reg wb_err;
	output reg [wb_N - 1:0] wb_data_rd;
	input wire i_clk;
	input wire i_rst;
	reg [WIDTH_OVERRIDE - 1:0] ram [0:DEPTH_WORDS - 1];
	initial if (|INIT_FILE)
		$readmemb(INIT_FILE, ram);
	wire [31:0] addr = (wb_addr - BASE_ADDR) >> 2;
	wire valid_addr = (wb_addr >= BASE_ADDR) && (wb_addr < (BASE_ADDR + (4 * DEPTH_WORDS)));
	wire aligned = wb_addr[1:0] == 0;
	reg [31:0] r_addr;
	reg [$clog2(LATENCY):0] ctr = 0;
	always @(posedge i_clk) begin
		wb_ack <= 0;
		wb_err <= 0;
		if (i_rst)
			ctr <= 0;
		if (wb_cyc && wb_stb)
			if (valid_addr && aligned) begin
				if (wb_we) begin
					if (wb_sel[0])
						ram[addr][7:0] <= wb_data_wr[7:0];
					if (wb_sel[1])
						ram[addr][15:8] <= wb_data_wr[15:8];
					if (wb_sel[2])
						ram[addr][23:16] <= wb_data_wr[23:16];
					if (wb_sel[3])
						ram[addr][31:24] <= wb_data_wr[31:24];
					if (LATENCY == 0)
						wb_ack <= 1;
					else
						ctr <= LATENCY[$clog2(LATENCY):0];
				end
				else begin
					r_addr <= addr;
					if (LATENCY == 0) begin
						wb_data_rd <= ram[addr];
						wb_ack <= 1;
					end
					else
						ctr <= LATENCY[$clog2(LATENCY):0];
				end
			end
			else begin
				$display("INVALID MEMORY ACCESS");
				wb_err <= 1;
			end
		if (ctr > 0) begin
			ctr <= ctr - 1;
			if ((ctr - 1) == 0) begin
				ctr <= 0;
				wb_data_rd <= ram[r_addr];
				wb_ack <= 1;
			end
		end
	end
endmodule
`default_nettype none
module wbram_withgpio (
	wb_cyc,
	wb_stb,
	wb_we,
	wb_sel,
	wb_addr,
	wb_data_wr,
	wb_ack,
	wb_err,
	wb_data_rd,
	o_gpio_out,
	i_clk,
	i_rst
);
	parameter BASE_ADDR = 32'h00000000;
	parameter DEPTH_WORDS = 512;
	parameter [1023:0] INIT_FILE = "";
	localparam ADDR_WIDTH = $clog2(DEPTH_WORDS);
	parameter GPIO_ADDR = 32'h80000000;
	parameter LATENCY = 0;
	parameter WIDTH_OVERRIDE = 32;
	localparam wb_N = 32;
	localparam wb_NUM_BYTES = wb_N / 8;
	input wire wb_cyc;
	input wire wb_stb;
	input wire wb_we;
	input wire [wb_NUM_BYTES - 1:0] wb_sel;
	input wire [wb_N - 1:0] wb_addr;
	input wire [wb_N - 1:0] wb_data_wr;
	output reg wb_ack;
	output reg wb_err;
	output reg [wb_N - 1:0] wb_data_rd;
	output reg [31:0] o_gpio_out;
	input wire i_clk;
	input wire i_rst;
	reg [WIDTH_OVERRIDE - 1:0] ram [0:DEPTH_WORDS - 1];
	initial if (|INIT_FILE)
		$readmemb(INIT_FILE, ram);
	wire [31:0] addr = (wb_addr - BASE_ADDR) >> 2;
	wire valid_addr = (wb_addr >= BASE_ADDR) && (wb_addr < (BASE_ADDR + (4 * DEPTH_WORDS)));
	wire aligned = wb_addr[1:0] == 0;
	reg [31:0] r_addr;
	reg [$clog2(LATENCY):0] ctr = 0;
	always @(posedge i_clk) begin
		wb_ack <= 0;
		wb_err <= 0;
		if (i_rst) begin
			ctr <= 0;
			o_gpio_out <= 0;
		end
		if (wb_cyc && wb_stb)
			if (valid_addr && aligned) begin
				if (wb_we) begin
					if (wb_sel[0])
						ram[addr][7:0] <= wb_data_wr[7:0];
					if (wb_sel[1])
						ram[addr][15:8] <= wb_data_wr[15:8];
					if (wb_sel[2])
						ram[addr][23:16] <= wb_data_wr[23:16];
					if (wb_sel[3])
						ram[addr][31:24] <= wb_data_wr[31:24];
					if (LATENCY == 0)
						wb_ack <= 1;
					else
						ctr <= LATENCY[$clog2(LATENCY):0];
				end
				else begin
					r_addr <= addr;
					if (LATENCY == 0) begin
						wb_data_rd <= ram[addr];
						wb_ack <= 1;
					end
					else
						ctr <= LATENCY[$clog2(LATENCY):0];
				end
			end
			else if (wb_addr == GPIO_ADDR) begin
				if (wb_we) begin
					if (wb_sel[0])
						o_gpio_out[7:0] <= wb_data_wr[7:0];
					if (wb_sel[1])
						o_gpio_out[15:8] <= wb_data_wr[15:8];
					if (wb_sel[2])
						o_gpio_out[23:16] <= wb_data_wr[23:16];
					if (wb_sel[3])
						o_gpio_out[31:24] <= wb_data_wr[31:24];
				end
				wb_data_rd <= o_gpio_out;
				wb_ack <= 1;
			end
			else begin
				$display("INVALID MEMORY ACCESS");
				wb_err <= 1;
			end
		if (ctr > 0) begin
			ctr <= ctr - 1;
			if ((ctr - 1) == 0) begin
				ctr <= 0;
				wb_data_rd <= ram[r_addr];
				wb_ack <= 1;
			end
		end
	end
endmodule
`default_nettype none
module bram32 (
	o_data,
	i_addr,
	i_data,
	i_we,
	i_wr_subaddr,
	i_clk
);
	parameter DEPTH = 512;
	parameter INIT_FILE = "";
	localparam ADDR_WIDTH = $clog2(DEPTH);
	output wire [31:0] o_data;
	input wire [ADDR_WIDTH - 1:0] i_addr;
	input wire [31:0] i_data;
	input wire i_we;
	input wire [2:0] i_wr_subaddr;
	input wire i_clk;
	reg [35:0] ram [0:DEPTH - 1];
	initial if (|INIT_FILE)
		$readmemb(INIT_FILE, ram);
	reg [ADDR_WIDTH - 1:0] r_addr;
	always @(posedge i_clk) begin
		if (i_we)
			case (i_wr_subaddr)
				1: ram[i_addr][31:0] <= i_data[31:0];
				2: ram[i_addr][15:0] <= i_data[15:0];
				3: ram[i_addr][31:16] <= i_data[15:0];
				4: ram[i_addr][7:0] <= i_data[7:0];
				5: ram[i_addr][15:8] <= i_data[7:0];
				6: ram[i_addr][23:16] <= i_data[7:0];
				7: ram[i_addr][31:24] <= i_data[7:0];
			endcase
		r_addr <= i_addr;
	end
	assign o_data = ram[r_addr][31:0];
endmodule
`default_nettype none
module rom32 (
	o_data,
	i_addr,
	i_clk
);
	parameter DEPTH = 512;
	parameter INIT_FILE = "";
	localparam ADDR_WIDTH = $clog2(DEPTH);
	output wire [31:0] o_data;
	input wire [ADDR_WIDTH - 1:0] i_addr;
	input wire i_clk;
	wire [35:0] ram [0:DEPTH - 1];
	initial if (|INIT_FILE)
		$readmemb(INIT_FILE, ram);
	reg [ADDR_WIDTH - 1:0] r_addr;
	always @(posedge i_clk) r_addr <= i_addr;
	assign o_data = ram[r_addr][31:0];
endmodule
module decode (
	i_instr,
	i_pc,
	o_out
);
	input wire [31:0] i_instr;
	input wire [31:0] i_pc;
	output reg [127:0] o_out;
	always @(*) o_out[127-:33] = {1'b1, i_instr};
	wire [6:0] opcode = i_instr[6:0];
	wire [6:0] funct7 = i_instr[31:25];
	wire [2:0] funct3 = i_instr[14:12];
	reg invalid_opcode;
	always @(*) o_out[94] = invalid_opcode;
	always @(*) begin
		invalid_opcode = 0;
		o_out[89] = ((opcode == 7'b1100011) | (opcode == 7'b1101111)) | (opcode == 7'b0010111);
		o_out[88] = opcode != 7'b0110011;
		o_out[87] = opcode == 7'b1100011;
		o_out[86-:3] = funct3;
		o_out[83] = (opcode == 7'b1101111) | (opcode == 7'b1100111);
		o_out[82] = funct3[2];
		if ((opcode == 7'b0000011) | (opcode == 7'b0100011))
			o_out[81-:3] = {opcode == 7'b0100011, funct3[1:0] + 1'b1};
		else
			o_out[81-:3] = 0;
		o_out[78-:5] = ((opcode == 7'b0100011) | (opcode == 7'b1100011) ? 0 : i_instr[11:7]);
		o_out[73-:5] = (opcode == 7'b0110111 ? 0 : i_instr[19:15]);
		o_out[68-:5] = i_instr[24:20];
		o_out[31-:32] = i_pc;
		o_out[93-:4] = 0;
		o_out[63-:32] = 0;
		case (i_instr[6:0])
			7'b0110011: o_out[93-:4] = {funct7[5], funct3};
			7'b0010011: begin
				o_out[93-:4] = {(funct3 == 3'd5) & funct7[5], funct3};
				o_out[63-:32] = {{20 {i_instr[31]}}, i_instr[31:20]};
			end
			7'b0000011: o_out[63-:32] = {{20 {i_instr[31]}}, i_instr[31:20]};
			7'b0100011: o_out[63-:32] = {{20 {i_instr[31]}}, i_instr[31:25], i_instr[11:7]};
			7'b1100011: o_out[63-:32] = {{19 {i_instr[31]}}, i_instr[31], i_instr[7], i_instr[30:25], i_instr[11:8], 1'b0};
			7'b1101111: o_out[63-:32] = {{11 {i_instr[31]}}, i_instr[31], i_instr[19:12], i_instr[20], i_instr[30:21], 1'b0};
			7'b1100111: o_out[63-:32] = {{20 {i_instr[31]}}, i_instr[31:20]};
			7'b0110111: o_out[63-:32] = {i_instr[31:12], 12'b0};
			7'b0010111: o_out[63-:32] = {i_instr[31:12], 12'b0};
			default: invalid_opcode = 1;
		endcase
	end
endmodule
`default_nettype none
`default_nettype none
module cpu (
	instr_wb_cyc,
	instr_wb_stb,
	instr_wb_we,
	instr_wb_sel,
	instr_wb_addr,
	instr_wb_data_wr,
	instr_wb_ack,
	instr_wb_err,
	instr_wb_data_rd,
	data_wb_cyc,
	data_wb_stb,
	data_wb_we,
	data_wb_sel,
	data_wb_addr,
	data_wb_data_wr,
	data_wb_ack,
	data_wb_err,
	data_wb_data_rd,
	i_stall_in,
	i_init_pc,
	o_stall_out,
	o_pc_out,
	i_rst,
	i_clk
);
	parameter INIT_PC = 32'h10000000;
	parameter USE_BARREL_SHIFTER = 1;
	parameter WISHBONE_PIPELINED = 0;
	parameter INST_STALL_BUBBLE = 1;
	localparam instr_wb_N = 32;
	localparam instr_wb_NUM_BYTES = instr_wb_N / 8;
	output wire instr_wb_cyc;
	output wire instr_wb_stb;
	output wire instr_wb_we;
	output wire [instr_wb_NUM_BYTES - 1:0] instr_wb_sel;
	output wire [instr_wb_N - 1:0] instr_wb_addr;
	output wire [instr_wb_N - 1:0] instr_wb_data_wr;
	input wire instr_wb_ack;
	input wire instr_wb_err;
	input wire [instr_wb_N - 1:0] instr_wb_data_rd;
	localparam data_wb_N = 32;
	localparam data_wb_NUM_BYTES = data_wb_N / 8;
	output wire data_wb_cyc;
	output wire data_wb_stb;
	output wire data_wb_we;
	output wire [data_wb_NUM_BYTES - 1:0] data_wb_sel;
	output wire [data_wb_N - 1:0] data_wb_addr;
	output wire [data_wb_N - 1:0] data_wb_data_wr;
	input wire data_wb_ack;
	input wire data_wb_err;
	input wire [data_wb_N - 1:0] data_wb_data_rd;
	input wire i_stall_in;
	input wire [31:0] i_init_pc;
	output wire o_stall_out;
	output wire [31:0] o_pc_out;
	input wire i_rst;
	input wire i_clk;
	wire alu_stall;
	wire inst_stall;
	wire data_stall;
	wire stall = ((alu_stall || data_stall) || i_stall_in) || (INST_STALL_BUBBLE ? 0 : inst_stall);
	assign o_stall_out = stall;
	wire inst_valid;
	wire take_branch;
	wire take_jump;
	reg [31:0] rd_write;
	wire [127:0] instr_1;
	reg [127:0] instr_2;
	wire [31:0] raw_instr;
	reg [31:0] pc;
	reg [31:0] next_pc;
	reg first;
	assign o_pc_out = pc;
	wire [31:0] data_addr;
	wire [31:0] data_rdata;
	wire [31:0] data_wdata;
	wire [1:0] data_width;
	wire data_we;
	wire data_read_en;
	wire data_zeroextend;
	wire [31:0] pc_req;
	generate
		if (|WISHBONE_PIPELINED) imembus_wbp imembus(
			.wb_cyc(instr_wb_cyc),
			.wb_stb(instr_wb_stb),
			.wb_we(instr_wb_we),
			.wb_sel(instr_wb_sel),
			.wb_addr(instr_wb_addr),
			.wb_data_wr(instr_wb_data_wr),
			.wb_ack(instr_wb_ack),
			.wb_err(instr_wb_err),
			.wb_data_rd(instr_wb_data_rd),
			.i_addr(next_pc),
			.o_data(raw_instr),
			.o_read_addr(pc_req),
			.i_re(~(stall || inst_stall)),
			.o_stall(inst_stall),
			.o_valid(inst_valid),
			.o_error(),
			.o_unaligned(),
			.i_clk(i_clk),
			.i_rst(i_rst)
		);
		else imembus_wbc imembus(
			.wb_cyc(instr_wb_cyc),
			.wb_stb(instr_wb_stb),
			.wb_we(instr_wb_we),
			.wb_sel(instr_wb_sel),
			.wb_addr(instr_wb_addr),
			.wb_data_wr(instr_wb_data_wr),
			.wb_ack(instr_wb_ack),
			.wb_err(instr_wb_err),
			.wb_data_rd(instr_wb_data_rd),
			.i_addr(next_pc),
			.o_data(raw_instr),
			.o_read_addr(pc_req),
			.i_re(~(stall || inst_stall)),
			.o_stall(inst_stall),
			.o_valid(inst_valid),
			.o_error(),
			.o_unaligned(),
			.i_clk(i_clk),
			.i_rst(i_rst)
		);
	endgenerate
	generate
		if (|WISHBONE_PIPELINED) dmembus_wbp_alignedonly dmembus(
			.wb_cyc(data_wb_cyc),
			.wb_stb(data_wb_stb),
			.wb_we(data_wb_we),
			.wb_sel(data_wb_sel),
			.wb_addr(data_wb_addr),
			.wb_data_wr(data_wb_data_wr),
			.wb_ack(data_wb_ack),
			.wb_err(data_wb_err),
			.wb_data_rd(data_wb_data_rd),
			.o_bus_width_hint(),
			.i_addr(data_addr),
			.o_data(data_rdata),
			.i_data(data_wdata),
			.i_width(data_width),
			.i_we(data_we),
			.i_re(~stall && data_read_en),
			.i_zeroextend(data_zeroextend),
			.o_stall(data_stall),
			.o_error(),
			.o_unaligned(),
			.i_clk(i_clk),
			.i_rst(i_rst)
		);
		else dmembus_wbc_alignedonly dmembus(
			.wb_cyc(data_wb_cyc),
			.wb_stb(data_wb_stb),
			.wb_we(data_wb_we),
			.wb_sel(data_wb_sel),
			.wb_addr(data_wb_addr),
			.wb_data_wr(data_wb_data_wr),
			.wb_ack(data_wb_ack),
			.wb_err(data_wb_err),
			.wb_data_rd(data_wb_data_rd),
			.o_bus_width_hint(),
			.i_addr(data_addr),
			.o_data(data_rdata),
			.i_data(data_wdata),
			.i_width(data_width),
			.i_we(data_we),
			.i_re(~stall && data_read_en),
			.i_zeroextend(data_zeroextend),
			.o_stall(data_stall),
			.o_error(),
			.o_unaligned(),
			.i_clk(i_clk),
			.i_rst(i_rst)
		);
	endgenerate
	decode decode(
		.i_instr((inst_stall && INST_STALL_BUBBLE ? 32'h13 : raw_instr)),
		.i_pc(pc_req),
		.o_out(instr_1)
	);
	wire [31:0] rs1_read;
	wire [31:0] rs2_read;
	wire fwd1 = ((instr_1[73-:5] == instr_2[78-:5]) && (instr_2[78-:5] != 0)) && ~stall;
	wire fwd2 = ((instr_1[68-:5] == instr_2[78-:5]) && (instr_2[78-:5] != 0)) && ~stall;
	wire [31:0] rs1 = (fwd1 ? rd_write : rs1_read);
	wire [31:0] rs2 = (fwd2 ? rd_write : rs2_read);
	regfile regfile(
		.i_rd_addr((stall ? 0 : instr_2[78-:5])),
		.i_rd_data(rd_write),
		.i_rs1_addr(instr_1[73-:5]),
		.o_rs1_data(rs1_read),
		.i_rs2_addr(instr_1[68-:5]),
		.o_rs2_data(rs2_read),
		.i_clk(i_clk),
		.i_rst(i_rst)
	);
	wire [31:0] alu_A = (instr_1[89] ? instr_1[31-:32] : rs1);
	wire [31:0] alu_B = (instr_1[88] ? instr_1[63-:32] : rs2);
	wire [31:0] alu_out;
	wire alu_valid;
	assign alu_stall = ~alu_valid;
	alu #(.USE_BARREL_SHIFTER(USE_BARREL_SHIFTER)) alu(
		.i_op(instr_1[93-:4]),
		.i_A(alu_A),
		.i_B(alu_B),
		.o_out(alu_out),
		.i_valid(~stall),
		.o_valid(alu_valid),
		.i_clk(i_clk),
		.i_rst(i_rst)
	);
	wire branch_out;
	assign take_branch = branch_out && instr_1[87];
	branch_controller branch(
		.i_rs1(rs1),
		.i_rs2(rs2),
		.i_branch_type(instr_1[86-:3]),
		.o_take_branch(branch_out)
	);
	assign take_jump = instr_1[83];
	assign data_wdata = rs2;
	assign data_addr = rs1 + instr_1[63-:32];
	assign data_width = instr_1[80:79];
	assign data_we = ~stall && (instr_1[81-:3] > 4);
	assign data_read_en = ~stall && ((instr_1[81-:3] > 0) && (instr_1[81-:3] < 4));
	assign data_zeroextend = instr_1[82];
	always @(*)
		if (instr_2[83])
			rd_write = instr_2[31-:32] + 4;
		else if ((instr_2[81-:3] > 0) && (instr_2[81-:3] < 4))
			rd_write = data_rdata;
		else
			rd_write = alu_out;
	always @(posedge i_clk)
		if (i_rst)
			first <= 1;
		else if (inst_valid)
			first <= 0;
	wire [31:0] alu_sum = alu_A + alu_B;
	always @(*)
		if (i_rst || first)
			next_pc = i_init_pc;
		else if (stall || inst_stall)
			next_pc = pc;
		else if (take_jump | take_branch)
			next_pc = {alu_sum[31:1], 1'b0};
		else
			next_pc = pc + 4;
	always @(posedge i_clk)
		if (i_rst)
			instr_2 <= 0;
		else if (~stall) begin
			instr_2 <= (i_rst ? 0 : instr_1);
			pc <= next_pc;
		end
endmodule
`default_nettype none
module dmembus_wbp (
	wb_cyc,
	wb_stb,
	wb_we,
	wb_sel,
	wb_addr,
	wb_data_wr,
	wb_ack,
	wb_err,
	wb_data_rd,
	o_bus_width_hint,
	i_addr,
	o_data,
	i_data,
	i_width,
	i_we,
	i_re,
	i_zeroextend,
	o_stall,
	o_error,
	i_clk,
	i_rst
);
	localparam wb_N = 32;
	localparam wb_NUM_BYTES = wb_N / 8;
	output wire wb_cyc;
	output wire wb_stb;
	output wire wb_we;
	output reg [wb_NUM_BYTES - 1:0] wb_sel;
	output wire [wb_N - 1:0] wb_addr;
	output wire [wb_N - 1:0] wb_data_wr;
	input wire wb_ack;
	input wire wb_err;
	input wire [wb_N - 1:0] wb_data_rd;
	output wire [1:0] o_bus_width_hint;
	input wire [31:0] i_addr;
	output wire [31:0] o_data;
	input wire [31:0] i_data;
	input wire [1:0] i_width;
	input wire i_we;
	input wire i_re;
	input wire i_zeroextend;
	output wire o_stall;
	output wire o_error;
	input wire i_clk;
	input wire i_rst;
	reg started;
	wire in_progress = started && ~(wb_ack || wb_err);
	assign o_stall = in_progress;
	wire i_req = i_we || i_re;
	reg [31:0] r_addr;
	always @(posedge i_clk)
		if (i_req)
			r_addr <= i_addr;
	wire [31:0] l_addr = (i_req ? i_addr : r_addr);
	assign wb_addr = l_addr;
	reg [2:0] r_width;
	always @(posedge i_clk)
		if (i_req)
			r_width <= {i_zeroextend, i_width};
	wire [2:0] l_width = (i_req ? {i_zeroextend, i_width} : r_width);
	assign o_bus_width_hint = l_width[1:0];
	reg [31:0] r_data_wr;
	always @(posedge i_clk)
		if (i_req)
			r_data_wr <= i_data;
	wire [31:0] l_data_wr = (i_req ? i_data : r_data_wr);
	assign wb_data_wr = l_data_wr;
	reg r_we;
	always @(posedge i_clk)
		if (i_req)
			r_we <= i_we;
	wire l_we = (i_req ? i_we : r_we);
	assign wb_we = l_we;
	reg [31:0] aligned_recv_data;
	reg [31:0] r_data_rd;
	always @(posedge i_clk)
		if (wb_ack)
			r_data_rd <= aligned_recv_data;
	wire [31:0] l_data_rd = (wb_ack ? aligned_recv_data : r_data_rd);
	assign o_data = l_data_rd;
	wire stb = (i_req && ~in_progress) && ~i_rst;
	assign wb_cyc = stb || in_progress;
	assign wb_stb = stb;
	reg r_err;
	always @(posedge i_clk) begin
		if (wb_err)
			r_err <= 1;
		if (i_req)
			r_err <= 0;
		if (i_rst)
			r_err <= 0;
	end
	wire l_err = (wb_err ? 1 : r_err);
	assign o_error = l_err;
	always @(posedge i_clk)
		if (i_rst)
			started <= 0;
		else begin
			if (wb_ack || wb_err)
				started <= 0;
			if (wb_stb)
				started <= 1;
		end
	always @(*) begin
		case (l_width[1:0])
			2'd1: wb_sel = 4'b0001;
			2'd2: wb_sel = 4'b0011;
			default: wb_sel = 4'b1111;
		endcase
		aligned_recv_data = wb_data_rd;
		case (r_width)
			{1'b0, 2'd1}: aligned_recv_data = {{24 {wb_data_rd[7]}}, wb_data_rd[7:0]};
			{1'b1, 2'd1}: aligned_recv_data = {24'b0, wb_data_rd[7:0]};
			{1'b0, 2'd2}: aligned_recv_data = {{16 {wb_data_rd[15]}}, wb_data_rd[15:0]};
			{1'b1, 2'd2}: aligned_recv_data = {16'b0, wb_data_rd[15:0]};
			default: aligned_recv_data = wb_data_rd[31:0];
		endcase
	end
endmodule
`default_nettype none
module dmembus_wbp_alignedonly (
	wb_cyc,
	wb_stb,
	wb_we,
	wb_sel,
	wb_addr,
	wb_data_wr,
	wb_ack,
	wb_err,
	wb_data_rd,
	o_bus_width_hint,
	i_addr,
	o_data,
	i_data,
	i_width,
	i_we,
	i_re,
	i_zeroextend,
	o_stall,
	o_error,
	o_unaligned,
	i_clk,
	i_rst
);
	localparam wb_N = 32;
	localparam wb_NUM_BYTES = wb_N / 8;
	output wire wb_cyc;
	output wire wb_stb;
	output wire wb_we;
	output reg [wb_NUM_BYTES - 1:0] wb_sel;
	output wire [wb_N - 1:0] wb_addr;
	output reg [wb_N - 1:0] wb_data_wr;
	input wire wb_ack;
	input wire wb_err;
	input wire [wb_N - 1:0] wb_data_rd;
	output wire [1:0] o_bus_width_hint;
	input wire [31:0] i_addr;
	output wire [31:0] o_data;
	input wire [31:0] i_data;
	input wire [1:0] i_width;
	input wire i_we;
	input wire i_re;
	input wire i_zeroextend;
	output wire o_stall;
	output wire o_error;
	output reg o_unaligned = 0;
	input wire i_clk;
	input wire i_rst;
	reg started;
	wire in_progress = started && ~(wb_ack || wb_err);
	assign o_stall = in_progress && ~(wb_ack || wb_err);
	wire i_req = i_we || i_re;
	reg addr_unaligned;
	wire unaligned = i_req && addr_unaligned;
	reg [31:0] r_addr;
	always @(posedge i_clk)
		if (i_req)
			r_addr <= i_addr;
	wire [31:0] l_addr = (i_req ? i_addr : r_addr);
	assign wb_addr = {l_addr[31:2], 2'b00};
	reg [2:0] r_width;
	always @(posedge i_clk)
		if (i_req)
			r_width <= {i_zeroextend, i_width};
	wire [2:0] l_width = (i_req ? {i_zeroextend, i_width} : r_width);
	assign o_bus_width_hint = l_width[1:0];
	reg [31:0] r_data_wr;
	always @(posedge i_clk)
		if (i_req)
			r_data_wr <= i_data;
	wire [31:0] l_data_wr = (i_req ? i_data : r_data_wr);
	reg r_we;
	always @(posedge i_clk)
		if (i_req)
			r_we <= i_we;
	wire l_we = (i_req ? i_we : r_we);
	assign wb_we = l_we;
	reg [31:0] aligned_recv_data;
	reg [31:0] r_data_rd;
	always @(posedge i_clk)
		if (wb_ack)
			r_data_rd <= aligned_recv_data;
	wire [31:0] l_data_rd = (wb_ack ? aligned_recv_data : r_data_rd);
	assign o_data = l_data_rd;
	wire stb = (~unaligned && (i_req && ~in_progress)) && ~i_rst;
	assign wb_cyc = stb || in_progress;
	assign wb_stb = stb;
	reg r_err;
	always @(posedge i_clk) begin
		if (wb_err)
			r_err <= 1;
		if (i_req)
			r_err <= 0;
		if (i_rst)
			r_err <= 0;
	end
	wire l_err = (wb_err ? 1 : r_err);
	assign o_error = l_err;
	always @(posedge i_clk)
		if (i_rst) begin
			started <= 0;
			o_unaligned <= 0;
		end
		else begin
			o_unaligned <= unaligned;
			if (wb_ack || wb_err)
				started <= 0;
			if (wb_stb)
				started <= 1;
		end
	reg ext;
	always @(*) begin
		if ((({2'b01, 2'b00} ^ ({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]})) === ({l_width[1:0], l_addr[1:0]} ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00}))) & (((({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]}) ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00})) === ({2'b01, 2'b00} ^ {2'b01, 2'b00})) | 1'bx)) begin
			wb_sel = 4'b0001;
			wb_data_wr = {24'b0, l_data_wr[7:0]};
		end
		else if ((({2'b01, 2'b01} ^ ({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]})) === ({l_width[1:0], l_addr[1:0]} ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01}))) & (((({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]}) ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01})) === ({2'b01, 2'b01} ^ {2'b01, 2'b01})) | 1'bx)) begin
			wb_sel = 4'b0010;
			wb_data_wr = {16'b0, l_data_wr[7:0], 8'b0};
		end
		else if ((({2'b01, 2'b10} ^ ({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]})) === ({l_width[1:0], l_addr[1:0]} ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10}))) & (((({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]}) ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10})) === ({2'b01, 2'b10} ^ {2'b01, 2'b10})) | 1'bx)) begin
			wb_sel = 4'b0100;
			wb_data_wr = {8'b0, l_data_wr[7:0], 16'b0};
		end
		else if ((({2'b01, 2'b11} ^ ({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]})) === ({l_width[1:0], l_addr[1:0]} ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11}))) & (((({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]}) ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11})) === ({2'b01, 2'b11} ^ {2'b01, 2'b11})) | 1'bx)) begin
			wb_sel = 4'b1000;
			wb_data_wr = {l_data_wr[7:0], 24'b0};
		end
		else if ((({2'b10, 2'b00} ^ ({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]})) === ({l_width[1:0], l_addr[1:0]} ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00}))) & (((({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]}) ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00})) === ({2'b10, 2'b00} ^ {2'b10, 2'b00})) | 1'bx)) begin
			wb_sel = 4'b0011;
			wb_data_wr = {16'b0, l_data_wr[15:0]};
		end
		else if ((({2'b10, 2'b10} ^ ({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]})) === ({l_width[1:0], l_addr[1:0]} ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10}))) & (((({l_width[1:0], l_addr[1:0]} ^ {l_width[1:0], l_addr[1:0]}) ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10})) === ({2'b10, 2'b10} ^ {2'b10, 2'b10})) | 1'bx)) begin
			wb_sel = 4'b1100;
			wb_data_wr = {l_data_wr[15:0], 16'b0};
		end
		else begin
			wb_sel = 4'b1111;
			wb_data_wr = l_data_wr;
		end
		ext = 0;
		aligned_recv_data = wb_data_rd;
		if ((({2'b01, 2'b00} ^ ({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]})) === ({r_width[1:0], r_addr[1:0]} ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00}))) & (((({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]}) ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00})) === ({2'b01, 2'b00} ^ {2'b01, 2'b00})) | 1'bx)) begin
			ext = (r_width[2] ? 0 : wb_data_rd[7]);
			aligned_recv_data = {{24 {ext}}, wb_data_rd[7:0]};
		end
		else if ((({2'b01, 2'b01} ^ ({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]})) === ({r_width[1:0], r_addr[1:0]} ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01}))) & (((({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]}) ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01})) === ({2'b01, 2'b01} ^ {2'b01, 2'b01})) | 1'bx)) begin
			ext = (r_width[2] ? 0 : wb_data_rd[15]);
			aligned_recv_data = {{24 {ext}}, wb_data_rd[15:8]};
		end
		else if ((({2'b01, 2'b10} ^ ({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]})) === ({r_width[1:0], r_addr[1:0]} ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10}))) & (((({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]}) ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10})) === ({2'b01, 2'b10} ^ {2'b01, 2'b10})) | 1'bx)) begin
			ext = (r_width[2] ? 0 : wb_data_rd[23]);
			aligned_recv_data = {{24 {ext}}, wb_data_rd[23:16]};
		end
		else if ((({2'b01, 2'b11} ^ ({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]})) === ({r_width[1:0], r_addr[1:0]} ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11}))) & (((({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]}) ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11})) === ({2'b01, 2'b11} ^ {2'b01, 2'b11})) | 1'bx)) begin
			ext = (r_width[2] ? 0 : wb_data_rd[31]);
			aligned_recv_data = {{24 {ext}}, wb_data_rd[31:24]};
		end
		else if ((({2'b10, 2'b00} ^ ({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]})) === ({r_width[1:0], r_addr[1:0]} ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00}))) & (((({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]}) ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00})) === ({2'b10, 2'b00} ^ {2'b10, 2'b00})) | 1'bx)) begin
			ext = (r_width[2] ? 0 : wb_data_rd[15]);
			aligned_recv_data = {{16 {ext}}, wb_data_rd[15:0]};
		end
		else if ((({2'b10, 2'b10} ^ ({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]})) === ({r_width[1:0], r_addr[1:0]} ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10}))) & (((({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]}) ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10})) === ({2'b10, 2'b10} ^ {2'b10, 2'b10})) | 1'bx)) begin
			ext = (r_width[2] ? 0 : wb_data_rd[31]);
			aligned_recv_data = {{16 {ext}}, wb_data_rd[31:16]};
		end
		else if (|{(({2'b11, 2'b00} ^ ({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]})) === ({r_width[1:0], r_addr[1:0]} ^ ({2'b11, 2'b00} ^ {2'b11, 2'b00}))) & (((({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]}) ^ ({2'b11, 2'b00} ^ {2'b11, 2'b00})) === ({2'b11, 2'b00} ^ {2'b11, 2'b00})) | 1'bx), (({2'b00, 2'b00} ^ ({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]})) === ({r_width[1:0], r_addr[1:0]} ^ ({2'b00, 2'b00} ^ {2'b00, 2'b00}))) & (((({r_width[1:0], r_addr[1:0]} ^ {r_width[1:0], r_addr[1:0]}) ^ ({2'b00, 2'b00} ^ {2'b00, 2'b00})) === ({2'b00, 2'b00} ^ {2'b00, 2'b00})) | 1'bx)})
			aligned_recv_data = wb_data_rd[31:0];
		if ((({2'b01, 2'b00} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00})) === ({2'b01, 2'b00} ^ {2'b01, 2'b00})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b01, 2'b01} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01})) === ({2'b01, 2'b01} ^ {2'b01, 2'b01})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b01, 2'b10} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10})) === ({2'b01, 2'b10} ^ {2'b01, 2'b10})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b01, 2'b11} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11})) === ({2'b01, 2'b11} ^ {2'b01, 2'b11})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b10, 2'b00} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00})) === ({2'b10, 2'b00} ^ {2'b10, 2'b00})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b10, 2'b10} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10})) === ({2'b10, 2'b10} ^ {2'b10, 2'b10})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b00, 2'b00} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b00, 2'b00} ^ {2'b00, 2'b00}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b00, 2'b00} ^ {2'b00, 2'b00})) === ({2'b00, 2'b00} ^ {2'b00, 2'b00})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b11, 2'b00} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b11, 2'b00} ^ {2'b11, 2'b00}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b11, 2'b00} ^ {2'b11, 2'b00})) === ({2'b11, 2'b00} ^ {2'b11, 2'b00})) | 1'bx))
			addr_unaligned = 0;
		else
			addr_unaligned = 1;
	end
endmodule
`default_nettype none
module dmembus_wbc_alignedonly (
	wb_cyc,
	wb_stb,
	wb_we,
	wb_sel,
	wb_addr,
	wb_data_wr,
	wb_ack,
	wb_err,
	wb_data_rd,
	o_bus_width_hint,
	i_addr,
	o_data,
	i_data,
	i_width,
	i_we,
	i_re,
	i_zeroextend,
	o_stall,
	o_error,
	o_unaligned,
	i_clk,
	i_rst
);
	localparam wb_N = 32;
	localparam wb_NUM_BYTES = wb_N / 8;
	output wire wb_cyc;
	output reg wb_stb;
	output reg wb_we;
	output reg [wb_NUM_BYTES - 1:0] wb_sel;
	output reg [wb_N - 1:0] wb_addr;
	output reg [wb_N - 1:0] wb_data_wr;
	input wire wb_ack;
	input wire wb_err;
	input wire [wb_N - 1:0] wb_data_rd;
	output wire [1:0] o_bus_width_hint;
	input wire [31:0] i_addr;
	output reg [31:0] o_data;
	input wire [31:0] i_data;
	input wire [1:0] i_width;
	input wire i_we;
	input wire i_re;
	input wire i_zeroextend;
	output reg o_stall;
	output reg o_error;
	output reg o_unaligned = 0;
	input wire i_clk;
	input wire i_rst;
	assign wb_cyc = wb_stb;
	wire i_req = i_we || i_re;
	reg [4:0] r_width;
	reg addr_unaligned;
	wire unaligned = i_req && addr_unaligned;
	reg [3:0] sel;
	reg [31:0] aligned_send_data;
	reg [31:0] aligned_recv_data;
	always @(posedge i_clk)
		if (i_rst) begin
			o_error <= 0;
			o_stall <= 0;
			o_unaligned <= 0;
			wb_stb <= 0;
		end
		else begin
			o_unaligned <= unaligned;
			if (wb_ack || wb_err) begin
				if (wb_err)
					o_error <= 1;
				wb_stb <= 0;
				o_stall <= 0;
				o_data <= aligned_recv_data;
			end
			if (i_req && ~unaligned) begin
				r_width <= {i_zeroextend, i_width, i_addr[1:0]};
				wb_stb <= 1;
				wb_addr <= {i_addr[31:2], 2'b00};
				wb_we <= i_we;
				wb_sel <= sel;
				wb_data_wr <= aligned_send_data;
				o_stall <= 1;
				o_error <= 0;
			end
		end
	reg ext;
	always @(*) begin
		if ((({2'b01, 2'b00} ^ ({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]})) === ({i_width[1:0], i_addr[1:0]} ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00}))) & (((({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]}) ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00})) === ({2'b01, 2'b00} ^ {2'b01, 2'b00})) | 1'bx)) begin
			sel = 4'b0001;
			aligned_send_data = {24'b0, i_data[7:0]};
		end
		else if ((({2'b01, 2'b01} ^ ({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]})) === ({i_width[1:0], i_addr[1:0]} ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01}))) & (((({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]}) ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01})) === ({2'b01, 2'b01} ^ {2'b01, 2'b01})) | 1'bx)) begin
			sel = 4'b0010;
			aligned_send_data = {16'b0, i_data[7:0], 8'b0};
		end
		else if ((({2'b01, 2'b10} ^ ({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]})) === ({i_width[1:0], i_addr[1:0]} ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10}))) & (((({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]}) ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10})) === ({2'b01, 2'b10} ^ {2'b01, 2'b10})) | 1'bx)) begin
			sel = 4'b0100;
			aligned_send_data = {8'b0, i_data[7:0], 16'b0};
		end
		else if ((({2'b01, 2'b11} ^ ({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]})) === ({i_width[1:0], i_addr[1:0]} ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11}))) & (((({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]}) ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11})) === ({2'b01, 2'b11} ^ {2'b01, 2'b11})) | 1'bx)) begin
			sel = 4'b1000;
			aligned_send_data = {i_data[7:0], 24'b0};
		end
		else if ((({2'b10, 2'b00} ^ ({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]})) === ({i_width[1:0], i_addr[1:0]} ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00}))) & (((({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]}) ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00})) === ({2'b10, 2'b00} ^ {2'b10, 2'b00})) | 1'bx)) begin
			sel = 4'b0011;
			aligned_send_data = {16'b0, i_data[15:0]};
		end
		else if ((({2'b10, 2'b10} ^ ({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]})) === ({i_width[1:0], i_addr[1:0]} ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10}))) & (((({i_width[1:0], i_addr[1:0]} ^ {i_width[1:0], i_addr[1:0]}) ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10})) === ({2'b10, 2'b10} ^ {2'b10, 2'b10})) | 1'bx)) begin
			sel = 4'b1100;
			aligned_send_data = {i_data[15:0], 16'b0};
		end
		else begin
			sel = 4'b1111;
			aligned_send_data = i_data;
		end
		ext = 0;
		aligned_recv_data = wb_data_rd;
		if ((({2'b01, 2'b00} ^ (r_width[3:0] ^ r_width[3:0])) === (r_width[3:0] ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00}))) & ((((r_width[3:0] ^ r_width[3:0]) ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00})) === ({2'b01, 2'b00} ^ {2'b01, 2'b00})) | 1'bx)) begin
			ext = (r_width[4] ? 0 : wb_data_rd[7]);
			aligned_recv_data = {{24 {ext}}, wb_data_rd[7:0]};
		end
		else if ((({2'b01, 2'b01} ^ (r_width[3:0] ^ r_width[3:0])) === (r_width[3:0] ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01}))) & ((((r_width[3:0] ^ r_width[3:0]) ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01})) === ({2'b01, 2'b01} ^ {2'b01, 2'b01})) | 1'bx)) begin
			ext = (r_width[4] ? 0 : wb_data_rd[15]);
			aligned_recv_data = {{24 {ext}}, wb_data_rd[15:8]};
		end
		else if ((({2'b01, 2'b10} ^ (r_width[3:0] ^ r_width[3:0])) === (r_width[3:0] ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10}))) & ((((r_width[3:0] ^ r_width[3:0]) ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10})) === ({2'b01, 2'b10} ^ {2'b01, 2'b10})) | 1'bx)) begin
			ext = (r_width[4] ? 0 : wb_data_rd[23]);
			aligned_recv_data = {{24 {ext}}, wb_data_rd[23:16]};
		end
		else if ((({2'b01, 2'b11} ^ (r_width[3:0] ^ r_width[3:0])) === (r_width[3:0] ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11}))) & ((((r_width[3:0] ^ r_width[3:0]) ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11})) === ({2'b01, 2'b11} ^ {2'b01, 2'b11})) | 1'bx)) begin
			ext = (r_width[4] ? 0 : wb_data_rd[31]);
			aligned_recv_data = {{24 {ext}}, wb_data_rd[31:24]};
		end
		else if ((({2'b10, 2'b00} ^ (r_width[3:0] ^ r_width[3:0])) === (r_width[3:0] ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00}))) & ((((r_width[3:0] ^ r_width[3:0]) ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00})) === ({2'b10, 2'b00} ^ {2'b10, 2'b00})) | 1'bx)) begin
			ext = (r_width[4] ? 0 : wb_data_rd[15]);
			aligned_recv_data = {{16 {ext}}, wb_data_rd[15:0]};
		end
		else if ((({2'b10, 2'b10} ^ (r_width[3:0] ^ r_width[3:0])) === (r_width[3:0] ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10}))) & ((((r_width[3:0] ^ r_width[3:0]) ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10})) === ({2'b10, 2'b10} ^ {2'b10, 2'b10})) | 1'bx)) begin
			ext = (r_width[4] ? 0 : wb_data_rd[31]);
			aligned_recv_data = {{16 {ext}}, wb_data_rd[31:16]};
		end
		else if (|{(({2'b11, 2'b00} ^ (r_width[3:0] ^ r_width[3:0])) === (r_width[3:0] ^ ({2'b11, 2'b00} ^ {2'b11, 2'b00}))) & ((((r_width[3:0] ^ r_width[3:0]) ^ ({2'b11, 2'b00} ^ {2'b11, 2'b00})) === ({2'b11, 2'b00} ^ {2'b11, 2'b00})) | 1'bx), (({2'b00, 2'b00} ^ (r_width[3:0] ^ r_width[3:0])) === (r_width[3:0] ^ ({2'b00, 2'b00} ^ {2'b00, 2'b00}))) & ((((r_width[3:0] ^ r_width[3:0]) ^ ({2'b00, 2'b00} ^ {2'b00, 2'b00})) === ({2'b00, 2'b00} ^ {2'b00, 2'b00})) | 1'bx)})
			aligned_recv_data = wb_data_rd[31:0];
		if ((({2'b01, 2'b00} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b01, 2'b00} ^ {2'b01, 2'b00})) === ({2'b01, 2'b00} ^ {2'b01, 2'b00})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b01, 2'b01} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b01, 2'b01} ^ {2'b01, 2'b01})) === ({2'b01, 2'b01} ^ {2'b01, 2'b01})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b01, 2'b10} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b01, 2'b10} ^ {2'b01, 2'b10})) === ({2'b01, 2'b10} ^ {2'b01, 2'b10})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b01, 2'b11} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b01, 2'b11} ^ {2'b01, 2'b11})) === ({2'b01, 2'b11} ^ {2'b01, 2'b11})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b10, 2'b00} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b10, 2'b00} ^ {2'b10, 2'b00})) === ({2'b10, 2'b00} ^ {2'b10, 2'b00})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b10, 2'b10} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b10, 2'b10} ^ {2'b10, 2'b10})) === ({2'b10, 2'b10} ^ {2'b10, 2'b10})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b00, 2'b00} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b00, 2'b00} ^ {2'b00, 2'b00}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b00, 2'b00} ^ {2'b00, 2'b00})) === ({2'b00, 2'b00} ^ {2'b00, 2'b00})) | 1'bx))
			addr_unaligned = 0;
		else if ((({2'b11, 2'b00} ^ ({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]})) === ({i_width, i_addr[1:0]} ^ ({2'b11, 2'b00} ^ {2'b11, 2'b00}))) & (((({i_width, i_addr[1:0]} ^ {i_width, i_addr[1:0]}) ^ ({2'b11, 2'b00} ^ {2'b11, 2'b00})) === ({2'b11, 2'b00} ^ {2'b11, 2'b00})) | 1'bx))
			addr_unaligned = 0;
		else
			addr_unaligned = 1;
	end
endmodule
`default_nettype none
module imembus_wbp (
	wb_cyc,
	wb_stb,
	wb_we,
	wb_sel,
	wb_addr,
	wb_data_wr,
	wb_ack,
	wb_err,
	wb_data_rd,
	i_addr,
	o_data,
	o_read_addr,
	i_re,
	o_stall,
	o_valid,
	o_error,
	o_unaligned,
	i_clk,
	i_rst
);
	localparam wb_N = 32;
	localparam wb_NUM_BYTES = wb_N / 8;
	output wire wb_cyc;
	output wire wb_stb;
	output wire wb_we;
	output wire [wb_NUM_BYTES - 1:0] wb_sel;
	output wire [wb_N - 1:0] wb_addr;
	output wire [wb_N - 1:0] wb_data_wr;
	input wire wb_ack;
	input wire wb_err;
	input wire [wb_N - 1:0] wb_data_rd;
	input wire [31:0] i_addr;
	output wire [31:0] o_data;
	output wire [31:0] o_read_addr;
	input wire i_re;
	output wire o_stall;
	output wire o_valid;
	output wire o_error;
	output reg o_unaligned = 0;
	input wire i_clk;
	input wire i_rst;
	assign wb_we = 0;
	assign wb_sel = 4'b1111;
	assign wb_data_wr = 0;
	reg first;
	assign o_valid = ((~first || wb_ack) || wb_err) && ~o_stall;
	reg started;
	wire in_progress = started && ~(wb_ack || wb_err);
	assign o_stall = in_progress && ~(wb_ack || wb_err);
	reg [31:0] r_addr;
	always @(posedge i_clk)
		if (i_re)
			r_addr <= i_addr;
	wire [31:0] l_addr = (i_re ? i_addr : r_addr);
	assign wb_addr = l_addr;
	reg [31:0] r_data;
	always @(posedge i_clk)
		if (wb_ack)
			r_data <= wb_data_rd;
	wire [31:0] l_data = (wb_ack ? wb_data_rd : r_data);
	assign o_data = l_data;
	reg [31:0] r_read_addr;
	always @(posedge i_clk)
		if (wb_ack)
			r_read_addr <= r_addr;
	wire [31:0] l_read_addr = (wb_ack ? r_addr : r_read_addr);
	assign o_read_addr = l_read_addr;
	reg r_err;
	always @(posedge i_clk) begin
		if (wb_err)
			r_err <= 1;
		if (i_re)
			r_err <= 0;
		if (i_rst)
			r_err <= 0;
	end
	wire l_err = (wb_err ? 1 : r_err);
	assign o_error = l_err;
	wire unaligned = i_re && (i_addr[1:0] != 0);
	wire stb = (~unaligned && (i_re && ~in_progress)) && ~i_rst;
	assign wb_cyc = stb || in_progress;
	assign wb_stb = stb;
	always @(posedge i_clk)
		if (i_rst) begin
			first <= 1;
			started <= 0;
			o_unaligned <= 0;
		end
		else begin
			o_unaligned <= unaligned;
			if (wb_ack || wb_err) begin
				first <= 0;
				started <= 0;
			end
			if (wb_stb)
				started <= 1;
		end
endmodule
`default_nettype none
module imembus_wbc (
	wb_cyc,
	wb_stb,
	wb_we,
	wb_sel,
	wb_addr,
	wb_data_wr,
	wb_ack,
	wb_err,
	wb_data_rd,
	i_addr,
	o_data,
	o_read_addr,
	i_re,
	o_stall,
	o_valid,
	o_error,
	o_unaligned,
	i_clk,
	i_rst
);
	localparam wb_N = 32;
	localparam wb_NUM_BYTES = wb_N / 8;
	output wire wb_cyc;
	output reg wb_stb;
	output wire wb_we;
	output wire [wb_NUM_BYTES - 1:0] wb_sel;
	output reg [wb_N - 1:0] wb_addr;
	output wire [wb_N - 1:0] wb_data_wr;
	input wire wb_ack;
	input wire wb_err;
	input wire [wb_N - 1:0] wb_data_rd;
	input wire [31:0] i_addr;
	output reg [31:0] o_data;
	output reg [31:0] o_read_addr;
	input wire i_re;
	output reg o_stall;
	output reg o_valid;
	output reg o_error;
	output reg o_unaligned = 0;
	input wire i_clk;
	input wire i_rst;
	assign wb_we = 0;
	assign wb_sel = 4'b1111;
	assign wb_data_wr = 0;
	assign wb_cyc = wb_stb;
	wire unaligned = i_re && (i_addr[1:0] != 0);
	always @(posedge i_clk)
		if (i_rst) begin
			o_error <= 0;
			o_valid <= 0;
			o_stall <= 0;
			o_unaligned <= 0;
			wb_stb <= 0;
		end
		else begin
			o_unaligned <= unaligned;
			if (wb_ack || wb_err) begin
				if (wb_err)
					o_error <= 1;
				wb_stb <= 0;
				o_valid <= 1;
				o_stall <= 0;
				o_data <= wb_data_rd;
				o_read_addr <= wb_addr;
			end
			if (i_re && ~unaligned) begin
				wb_stb <= 1;
				wb_addr <= i_addr;
				o_stall <= 1;
				o_error <= 0;
			end
		end
endmodule
`default_nettype none
`default_nettype none
module regfile (
	i_rd_addr,
	i_rd_data,
	i_rs1_addr,
	o_rs1_data,
	i_rs2_addr,
	o_rs2_data,
	d_regs_out,
	i_rst,
	i_clk
);
	parameter RESET_REGS = 1;
	input wire [4:0] i_rd_addr;
	input wire [31:0] i_rd_data;
	input wire [4:0] i_rs1_addr;
	output wire [31:0] o_rs1_data;
	input wire [4:0] i_rs2_addr;
	output wire [31:0] o_rs2_data;
	output wire [1023:0] d_regs_out;
	input wire i_rst;
	input wire i_clk;
	assign d_regs_out = registers;
	reg [1023:0] registers;
	assign o_rs1_data = (i_rs1_addr == 0 ? 0 : registers[(31 - i_rs1_addr) * 32+:32]);
	assign o_rs2_data = (i_rs2_addr == 0 ? 0 : registers[(31 - i_rs2_addr) * 32+:32]);
	always @(posedge i_clk)
		if (i_rst)
			;
		else if (i_rd_addr != 0)
			registers[(31 - i_rd_addr) * 32+:32] <= i_rd_data;
endmodule
`default_nettype none
module branch_controller (
	i_rs1,
	i_rs2,
	i_branch_type,
	o_take_branch
);
	input wire [31:0] i_rs1;
	input wire [31:0] i_rs2;
	input wire [2:0] i_branch_type;
	output wire o_take_branch;
	wire invert = i_branch_type[0];
	wire [1:0] btype = i_branch_type[2:1];
	reg condition;
	assign o_take_branch = (invert ? ~condition : condition);
	always @(*)
		case (btype)
			0: condition = i_rs1 == i_rs2;
			2: condition = $signed(i_rs1) < $signed(i_rs2);
			3: condition = i_rs1 < i_rs2;
			default: condition = 0;
		endcase
endmodule
`default_nettype none
module alu (
	i_op,
	i_A,
	i_B,
	o_out,
	i_valid,
	o_valid,
	i_clk,
	i_rst
);
	parameter USE_BARREL_SHIFTER = 1;
	input wire [3:0] i_op;
	input wire [31:0] i_A;
	input wire [31:0] i_B;
	output reg [31:0] o_out;
	input wire i_valid;
	output reg o_valid;
	input wire i_clk;
	input wire i_rst;
	wire sp = i_op[3];
	wire [2:0] op = i_op[2:0];
	wire [31:0] shift_out;
	barrel_shifter shifter(
		.i_in(i_A),
		.i_amt(i_B[4:0]),
		.i_dir(op[2]),
		.i_arith(sp),
		.o_out(shift_out)
	);
	reg [31:0] next;
	reg next_valid = 0;
	always @(posedge i_clk) begin
		o_valid <= 1;
		if (~o_valid && next_valid) begin
			o_valid <= 1;
			next_valid <= 0;
			o_out <= next;
		end
		else
			case (op)
				3'd0: begin
					next <= i_A + (sp ? ~i_B + 1 : i_B);
					next_valid <= 1;
					o_valid <= 0;
				end
				3'd4: o_out <= i_A ^ i_B;
				3'd6: o_out <= i_A | i_B;
				3'd7: o_out <= i_A & i_B;
				3'd1: o_out <= (USE_BARREL_SHIFTER ? shift_out : 0);
				3'd5: o_out <= (USE_BARREL_SHIFTER ? shift_out : 0);
				3'd2: o_out <= ($signed(i_A) < $signed(i_B) ? 1 : 0);
				3'd3: o_out <= (i_A < i_B ? 1 : 0);
			endcase
	end
endmodule
`default_nettype none
module barrel_shifter (
	i_in,
	i_amt,
	i_dir,
	i_arith,
	o_out
);
	input wire [31:0] i_in;
	input wire [4:0] i_amt;
	input wire i_dir;
	input wire i_arith;
	output reg [31:0] o_out;
	reg [31:0] lt_shifts [0:31];
	reg [31:0] rt_shifts [0:31];
	integer ind;
	always @(*) begin
		for (ind = 0; ind < 32; ind = ind + 1)
			begin
				lt_shifts[ind] = i_in << ind;
				rt_shifts[ind] = (i_arith ? $unsigned($signed(i_in) >>> ind) : i_in >> ind);
			end
		o_out = (i_dir ? rt_shifts[i_amt] : lt_shifts[i_amt]);
	end
endmodule
module ICache (
	clock,
	reset,
	io_flush_all,
	io_bus_cyc,
	io_bus_stb,
	io_bus_we,
	io_bus_addr,
	io_bus_ack,
	io_bus_data_rd,
	io_cache_mem_addr,
	io_cache_mem_rd_d,
	io_cache_mem_we,
	io_cache_mem_wr_d,
	io_main_mem_rd_req,
	io_main_mem_addr,
	io_main_mem_rd_d,
	io_main_mem_rd_rdy,
	io_main_mem_busy
);
	input clock;
	input reset;
	input io_flush_all;
	input io_bus_cyc;
	input io_bus_stb;
	input io_bus_we;
	input [31:0] io_bus_addr;
	output io_bus_ack;
	output [31:0] io_bus_data_rd;
	output [31:0] io_cache_mem_addr;
	input [31:0] io_cache_mem_rd_d;
	output io_cache_mem_we;
	output [31:0] io_cache_mem_wr_d;
	output io_main_mem_rd_req;
	output [31:0] io_main_mem_addr;
	input [31:0] io_main_mem_rd_d;
	input io_main_mem_rd_rdy;
	input io_main_mem_busy;
	reg valids_0;
	reg valids_1;
	reg valids_2;
	reg valids_3;
	reg valids_4;
	reg valids_5;
	reg valids_6;
	reg valids_7;
	reg [23:0] tags_0;
	reg [23:0] tags_1;
	reg [23:0] tags_2;
	reg [23:0] tags_3;
	reg [23:0] tags_4;
	reg [23:0] tags_5;
	reg [23:0] tags_6;
	reg [23:0] tags_7;
	wire _GEN_0 = (io_flush_all ? 1'h0 : valids_0);
	wire _GEN_1 = (io_flush_all ? 1'h0 : valids_1);
	wire _GEN_2 = (io_flush_all ? 1'h0 : valids_2);
	wire _GEN_3 = (io_flush_all ? 1'h0 : valids_3);
	wire _GEN_4 = (io_flush_all ? 1'h0 : valids_4);
	wire _GEN_5 = (io_flush_all ? 1'h0 : valids_5);
	wire _GEN_6 = (io_flush_all ? 1'h0 : valids_6);
	wire _GEN_7 = (io_flush_all ? 1'h0 : valids_7);
	reg [1:0] state;
	wire _T_10 = state == 2'h0;
	wire _T_11 = _T_10 & io_bus_stb;
	wire _T_12 = _T_11 & io_bus_cyc;
	wire _T_13 = ~io_bus_ack;
	wire _T_14 = _T_12 & _T_13;
	wire _T_17 = ~io_flush_all;
	wire [2:0] addr_set_index = io_bus_addr[7:5];
	wire _GEN_9 = (3'h1 == addr_set_index ? valids_1 : valids_0);
	wire _GEN_10 = (3'h2 == addr_set_index ? valids_2 : _GEN_9);
	wire _GEN_11 = (3'h3 == addr_set_index ? valids_3 : _GEN_10);
	wire _GEN_12 = (3'h4 == addr_set_index ? valids_4 : _GEN_11);
	wire _GEN_13 = (3'h5 == addr_set_index ? valids_5 : _GEN_12);
	wire _GEN_14 = (3'h6 == addr_set_index ? valids_6 : _GEN_13);
	wire _GEN_15 = (3'h7 == addr_set_index ? valids_7 : _GEN_14);
	wire _T_18 = _T_17 & _GEN_15;
	wire [23:0] _GEN_17 = (3'h1 == addr_set_index ? tags_1 : tags_0);
	wire [23:0] _GEN_18 = (3'h2 == addr_set_index ? tags_2 : _GEN_17);
	wire [23:0] _GEN_19 = (3'h3 == addr_set_index ? tags_3 : _GEN_18);
	wire [23:0] _GEN_20 = (3'h4 == addr_set_index ? tags_4 : _GEN_19);
	wire [23:0] _GEN_21 = (3'h5 == addr_set_index ? tags_5 : _GEN_20);
	wire [23:0] _GEN_22 = (3'h6 == addr_set_index ? tags_6 : _GEN_21);
	wire [23:0] _GEN_23 = (3'h7 == addr_set_index ? tags_7 : _GEN_22);
	wire [23:0] addr_tag_bits = io_bus_addr[31:8];
	wire _T_19 = _GEN_23 == addr_tag_bits;
	wire _T_20 = _T_18 & _T_19;
	wire _T_23 = state == 2'h1;
	wire _T_24 = ~io_main_mem_busy;
	wire _T_27 = state == 2'h2;
	wire _T_28 = _T_27 & io_main_mem_rd_rdy;
	reg [2:0] word_ctr;
	wire [3:0] _T_34 = 4'h8 - 4'h1;
	wire [3:0] _GEN_173 = {1'd0, word_ctr};
	wire _T_35 = _GEN_173 == _T_34;
	wire _T_36 = state == 2'h3;
	reg _T_6;
	reg [23:0] pending_tag_bits;
	reg [2:0] pending_set_index;
	reg [2:0] pending_block_offset;
	wire [2:0] addr_block_offset_word = io_bus_addr[4:2];
	wire [5:0] _T_15 = {addr_set_index, addr_block_offset_word};
	wire [29:0] _T_22 = {addr_tag_bits, addr_set_index, 3'h0};
	wire _GEN_28 = (io_main_mem_busy ? 1'h0 : 1'h1);
	wire [31:0] _GEN_29 = (io_main_mem_busy ? 32'h0 : {2'd0, _T_22});
	wire _GEN_36 = (_T_20 ? 1'h0 : _GEN_28);
	wire [31:0] _GEN_37 = (_T_20 ? 32'h0 : _GEN_29);
	wire _GEN_48 = io_bus_we | _T_20;
	wire [5:0] _GEN_49 = (io_bus_we ? 6'h0 : _T_15);
	wire _GEN_55 = (io_bus_we ? 1'h0 : _GEN_36);
	wire [31:0] _GEN_56 = (io_bus_we ? 32'h0 : _GEN_37);
	wire [29:0] _T_26 = {pending_tag_bits, pending_set_index, 3'h0};
	wire [31:0] _GEN_60 = (_T_24 ? {2'd0, _T_26} : 32'h0);
	wire [5:0] _T_30 = {pending_set_index, word_ctr};
	wire [2:0] _T_32 = word_ctr + 3'h1;
	wire _GEN_174 = 3'h0 == pending_set_index;
	wire _GEN_64 = _GEN_174 | _GEN_0;
	wire _GEN_175 = 3'h1 == pending_set_index;
	wire _GEN_65 = _GEN_175 | _GEN_1;
	wire _GEN_176 = 3'h2 == pending_set_index;
	wire _GEN_66 = _GEN_176 | _GEN_2;
	wire _GEN_177 = 3'h3 == pending_set_index;
	wire _GEN_67 = _GEN_177 | _GEN_3;
	wire _GEN_178 = 3'h4 == pending_set_index;
	wire _GEN_68 = _GEN_178 | _GEN_4;
	wire _GEN_179 = 3'h5 == pending_set_index;
	wire _GEN_69 = _GEN_179 | _GEN_5;
	wire _GEN_180 = 3'h6 == pending_set_index;
	wire _GEN_70 = _GEN_180 | _GEN_6;
	wire _GEN_181 = 3'h7 == pending_set_index;
	wire _GEN_71 = _GEN_181 | _GEN_7;
	wire [5:0] _T_37 = {pending_set_index, pending_block_offset};
	wire [5:0] _GEN_98 = (_T_36 ? _T_37 : 6'h0);
	wire [31:0] _GEN_100 = (_T_28 ? io_main_mem_rd_d : 32'h0);
	wire [5:0] _GEN_101 = (_T_28 ? _T_30 : _GEN_98);
	wire _GEN_122 = _T_23 & _T_24;
	wire [31:0] _GEN_123 = (_T_23 ? _GEN_60 : 32'h0);
	wire _GEN_125 = (_T_23 ? 1'h0 : _T_28);
	wire [31:0] _GEN_126 = (_T_23 ? 32'h0 : _GEN_100);
	wire [5:0] _GEN_127 = (_T_23 ? 6'h0 : _GEN_101);
	wire [5:0] _GEN_146 = (_T_14 ? _GEN_49 : _GEN_127);
	assign io_bus_ack = _T_6;
	assign io_bus_data_rd = io_cache_mem_rd_d;
	assign io_cache_mem_addr = {26'd0, _GEN_146};
	assign io_cache_mem_we = (_T_14 ? 1'h0 : _GEN_125);
	assign io_cache_mem_wr_d = (_T_14 ? 32'h0 : _GEN_126);
	assign io_main_mem_rd_req = (_T_14 ? _GEN_55 : _GEN_122);
	assign io_main_mem_addr = (_T_14 ? _GEN_56 : _GEN_123);
	always @(posedge clock) begin
		if (reset)
			valids_0 <= 1'h0;
		else if (_T_14) begin
			if (io_flush_all)
				valids_0 <= 1'h0;
		end
		else if (_T_23) begin
			if (io_flush_all)
				valids_0 <= 1'h0;
		end
		else if (_T_28) begin
			if (io_flush_all)
				valids_0 <= 1'h0;
		end
		else if (_T_36)
			valids_0 <= _GEN_64;
		else if (io_flush_all)
			valids_0 <= 1'h0;
		if (reset)
			valids_1 <= 1'h0;
		else if (_T_14) begin
			if (io_flush_all)
				valids_1 <= 1'h0;
		end
		else if (_T_23) begin
			if (io_flush_all)
				valids_1 <= 1'h0;
		end
		else if (_T_28) begin
			if (io_flush_all)
				valids_1 <= 1'h0;
		end
		else if (_T_36)
			valids_1 <= _GEN_65;
		else if (io_flush_all)
			valids_1 <= 1'h0;
		if (reset)
			valids_2 <= 1'h0;
		else if (_T_14) begin
			if (io_flush_all)
				valids_2 <= 1'h0;
		end
		else if (_T_23) begin
			if (io_flush_all)
				valids_2 <= 1'h0;
		end
		else if (_T_28) begin
			if (io_flush_all)
				valids_2 <= 1'h0;
		end
		else if (_T_36)
			valids_2 <= _GEN_66;
		else if (io_flush_all)
			valids_2 <= 1'h0;
		if (reset)
			valids_3 <= 1'h0;
		else if (_T_14) begin
			if (io_flush_all)
				valids_3 <= 1'h0;
		end
		else if (_T_23) begin
			if (io_flush_all)
				valids_3 <= 1'h0;
		end
		else if (_T_28) begin
			if (io_flush_all)
				valids_3 <= 1'h0;
		end
		else if (_T_36)
			valids_3 <= _GEN_67;
		else if (io_flush_all)
			valids_3 <= 1'h0;
		if (reset)
			valids_4 <= 1'h0;
		else if (_T_14) begin
			if (io_flush_all)
				valids_4 <= 1'h0;
		end
		else if (_T_23) begin
			if (io_flush_all)
				valids_4 <= 1'h0;
		end
		else if (_T_28) begin
			if (io_flush_all)
				valids_4 <= 1'h0;
		end
		else if (_T_36)
			valids_4 <= _GEN_68;
		else if (io_flush_all)
			valids_4 <= 1'h0;
		if (reset)
			valids_5 <= 1'h0;
		else if (_T_14) begin
			if (io_flush_all)
				valids_5 <= 1'h0;
		end
		else if (_T_23) begin
			if (io_flush_all)
				valids_5 <= 1'h0;
		end
		else if (_T_28) begin
			if (io_flush_all)
				valids_5 <= 1'h0;
		end
		else if (_T_36)
			valids_5 <= _GEN_69;
		else if (io_flush_all)
			valids_5 <= 1'h0;
		if (reset)
			valids_6 <= 1'h0;
		else if (_T_14) begin
			if (io_flush_all)
				valids_6 <= 1'h0;
		end
		else if (_T_23) begin
			if (io_flush_all)
				valids_6 <= 1'h0;
		end
		else if (_T_28) begin
			if (io_flush_all)
				valids_6 <= 1'h0;
		end
		else if (_T_36)
			valids_6 <= _GEN_70;
		else if (io_flush_all)
			valids_6 <= 1'h0;
		if (reset)
			valids_7 <= 1'h0;
		else if (_T_14) begin
			if (io_flush_all)
				valids_7 <= 1'h0;
		end
		else if (_T_23) begin
			if (io_flush_all)
				valids_7 <= 1'h0;
		end
		else if (_T_28) begin
			if (io_flush_all)
				valids_7 <= 1'h0;
		end
		else if (_T_36)
			valids_7 <= _GEN_71;
		else if (io_flush_all)
			valids_7 <= 1'h0;
		if (reset)
			tags_0 <= 24'h0;
		else if (!_T_14)
			if (!_T_23)
				if (!_T_28)
					if (_T_36)
						if (3'h0 == pending_set_index)
							tags_0 <= pending_tag_bits;
		if (reset)
			tags_1 <= 24'h0;
		else if (!_T_14)
			if (!_T_23)
				if (!_T_28)
					if (_T_36)
						if (3'h1 == pending_set_index)
							tags_1 <= pending_tag_bits;
		if (reset)
			tags_2 <= 24'h0;
		else if (!_T_14)
			if (!_T_23)
				if (!_T_28)
					if (_T_36)
						if (3'h2 == pending_set_index)
							tags_2 <= pending_tag_bits;
		if (reset)
			tags_3 <= 24'h0;
		else if (!_T_14)
			if (!_T_23)
				if (!_T_28)
					if (_T_36)
						if (3'h3 == pending_set_index)
							tags_3 <= pending_tag_bits;
		if (reset)
			tags_4 <= 24'h0;
		else if (!_T_14)
			if (!_T_23)
				if (!_T_28)
					if (_T_36)
						if (3'h4 == pending_set_index)
							tags_4 <= pending_tag_bits;
		if (reset)
			tags_5 <= 24'h0;
		else if (!_T_14)
			if (!_T_23)
				if (!_T_28)
					if (_T_36)
						if (3'h5 == pending_set_index)
							tags_5 <= pending_tag_bits;
		if (reset)
			tags_6 <= 24'h0;
		else if (!_T_14)
			if (!_T_23)
				if (!_T_28)
					if (_T_36)
						if (3'h6 == pending_set_index)
							tags_6 <= pending_tag_bits;
		if (reset)
			tags_7 <= 24'h0;
		else if (!_T_14)
			if (!_T_23)
				if (!_T_28)
					if (_T_36)
						if (3'h7 == pending_set_index)
							tags_7 <= pending_tag_bits;
		if (reset)
			state <= 2'h0;
		else if (_T_14) begin
			if (!io_bus_we)
				if (!_T_20)
					if (io_main_mem_busy)
						state <= 2'h1;
					else
						state <= 2'h2;
		end
		else if (_T_23) begin
			if (_T_24)
				state <= 2'h2;
		end
		else if (_T_28) begin
			if (_T_35)
				state <= 2'h3;
		end
		else if (_T_36)
			state <= 2'h0;
		if (reset)
			word_ctr <= 3'h0;
		else if (_T_14) begin
			if (!io_bus_we)
				if (!_T_20)
					if (!io_main_mem_busy)
						word_ctr <= 3'h0;
		end
		else if (_T_23) begin
			if (_T_24)
				word_ctr <= 3'h0;
		end
		else if (_T_28)
			if (_T_35)
				word_ctr <= 3'h0;
			else
				word_ctr <= _T_32;
		if (_T_14)
			_T_6 <= _GEN_48;
		else if (_T_23)
			_T_6 <= 1'h0;
		else if (_T_28)
			_T_6 <= 1'h0;
		else
			_T_6 <= _T_36;
		if (reset)
			pending_tag_bits <= 24'h0;
		else if (_T_14)
			if (!io_bus_we)
				if (!_T_20)
					pending_tag_bits <= addr_tag_bits;
		if (reset)
			pending_set_index <= 3'h0;
		else if (_T_14)
			if (!io_bus_we)
				if (!_T_20)
					pending_set_index <= addr_set_index;
		if (reset)
			pending_block_offset <= 3'h0;
		else if (_T_14)
			if (!io_bus_we)
				if (!_T_20)
					pending_block_offset <= addr_block_offset_word;
	end
endmodule
module WishboneMemoryBridge (
	clock,
	reset,
	io_bus_cyc,
	io_bus_stb,
	io_bus_we,
	io_bus_sel,
	io_bus_addr,
	io_bus_data_wr,
	io_bus_ack,
	io_bus_data_rd,
	io_mem_rd_req,
	io_mem_wr_req,
	io_mem_mem_or_reg,
	io_mem_wr_byte_en,
	io_mem_addr,
	io_mem_wr_d,
	io_mem_rd_d,
	io_mem_rd_rdy,
	io_mem_busy,
	io_mem_burst_wr_rdy
);
	input clock;
	input reset;
	input io_bus_cyc;
	input io_bus_stb;
	input io_bus_we;
	input [3:0] io_bus_sel;
	input [31:0] io_bus_addr;
	input [31:0] io_bus_data_wr;
	output io_bus_ack;
	output [31:0] io_bus_data_rd;
	output io_mem_rd_req;
	output io_mem_wr_req;
	output io_mem_mem_or_reg;
	output [3:0] io_mem_wr_byte_en;
	output [31:0] io_mem_addr;
	output [31:0] io_mem_wr_d;
	input [31:0] io_mem_rd_d;
	input io_mem_rd_rdy;
	input io_mem_busy;
	input io_mem_burst_wr_rdy;
	reg ack;
	reg [31:0] ack_data;
	reg txn_queued;
	reg txn_active;
	reg txn_we;
	wire _T = ~txn_active;
	wire _T_1 = _T & io_bus_stb;
	wire _T_2 = _T_1 & io_bus_cyc;
	wire _T_3 = ~io_bus_ack;
	wire _T_4 = _T_2 & _T_3;
	wire _T_5 = ~ack;
	wire wb_txn_valid = _T_4 & _T_5;
	reg [31:0] _T_6;
	wire [31:0] _GEN_0 = (wb_txn_valid ? io_bus_addr : _T_6);
	reg [3:0] _T_7;
	reg [31:0] _T_8;
	reg _T_9;
	wire _GEN_3 = (wb_txn_valid ? io_bus_we : _T_9);
	wire _T_12 = ~io_mem_busy;
	wire _T_13 = (txn_we ? _T_12 : io_mem_rd_rdy);
	wire _GEN_4 = _T_13 | ack;
	wire _GEN_6 = (_T_13 ? 1'h0 : txn_active);
	wire _T_15 = ~io_mem_burst_wr_rdy;
	wire _T_16 = _T_12 & _T_15;
	wire _T_18 = (_GEN_3 ? _T_16 : _T_12);
	wire _T_19 = ~_GEN_3;
	wire _GEN_7 = _T_18 & _T_19;
	wire _GEN_8 = _T_18 & _GEN_3;
	wire _GEN_10 = _T_18 | txn_active;
	wire _GEN_12 = txn_queued & _GEN_7;
	wire _GEN_13 = txn_queued & _GEN_8;
	wire _GEN_15 = (txn_queued ? _GEN_10 : txn_active);
	wire _GEN_19 = (txn_active ? _GEN_6 : _GEN_15);
	wire _GEN_20 = (txn_active ? 1'h0 : _GEN_12);
	wire _GEN_21 = (txn_active ? 1'h0 : _GEN_13);
	wire _GEN_28 = (ack ? txn_active : _GEN_19);
	wire _GEN_29 = (ack ? 1'h0 : _GEN_20);
	wire _GEN_30 = (ack ? 1'h0 : _GEN_21);
	wire _GEN_33 = (_T_18 ? _T_19 : _GEN_29);
	wire _GEN_34 = (_T_18 ? _GEN_3 : _GEN_30);
	wire _GEN_36 = _T_18 | _GEN_28;
	assign io_bus_ack = ack;
	assign io_bus_data_rd = (ack ? ack_data : 32'h0);
	assign io_mem_rd_req = (wb_txn_valid ? _GEN_33 : _GEN_29);
	assign io_mem_wr_req = (wb_txn_valid ? _GEN_34 : _GEN_30);
	assign io_mem_mem_or_reg = _GEN_0[27];
	assign io_mem_wr_byte_en = (wb_txn_valid ? io_bus_sel : _T_7);
	assign io_mem_addr = {7'd0, _GEN_0[26:2]};
	assign io_mem_wr_d = (wb_txn_valid ? io_bus_data_wr : _T_8);
	always @(posedge clock) begin
		if (reset)
			ack <= 1'h0;
		else if (ack)
			ack <= 1'h0;
		else if (txn_active)
			ack <= _GEN_4;
		if (!ack)
			if (txn_active)
				if (_T_13)
					ack_data <= io_mem_rd_d;
		if (reset)
			txn_queued <= 1'h0;
		else if (wb_txn_valid) begin
			if (_T_18)
				txn_queued <= 1'h0;
			else
				txn_queued <= 1'h1;
		end
		else if (!ack)
			if (!txn_active)
				if (txn_queued)
					if (_T_18)
						txn_queued <= 1'h0;
		if (reset)
			txn_active <= 1'h0;
		else if (wb_txn_valid)
			txn_active <= _GEN_36;
		else if (!ack)
			if (txn_active) begin
				if (_T_13)
					txn_active <= 1'h0;
			end
			else if (txn_queued)
				txn_active <= _GEN_10;
		if (reset)
			txn_we <= 1'h0;
		else if (wb_txn_valid) begin
			if (_T_18) begin
				if (wb_txn_valid)
					txn_we <= io_bus_we;
				else
					txn_we <= _T_9;
			end
			else if (!ack)
				if (!txn_active)
					if (txn_queued)
						if (_T_18)
							if (wb_txn_valid)
								txn_we <= io_bus_we;
							else
								txn_we <= _T_9;
		end
		else if (!ack)
			if (!txn_active)
				if (txn_queued)
					if (_T_18)
						if (wb_txn_valid)
							txn_we <= io_bus_we;
						else
							txn_we <= _T_9;
		if (wb_txn_valid)
			_T_6 <= io_bus_addr;
		if (wb_txn_valid)
			_T_7 <= io_bus_sel;
		if (wb_txn_valid)
			_T_8 <= io_bus_data_wr;
		if (wb_txn_valid)
			_T_9 <= io_bus_we;
	end
endmodule
module MemoryArbiter (
	clock,
	reset,
	io_in0_rd_req,
	io_in0_addr,
	io_in0_rd_d,
	io_in0_rd_rdy,
	io_in0_busy,
	io_in1_rd_req,
	io_in1_wr_req,
	io_in1_mem_or_reg,
	io_in1_wr_byte_en,
	io_in1_addr,
	io_in1_wr_d,
	io_in1_rd_d,
	io_in1_rd_rdy,
	io_in1_busy,
	io_in1_burst_wr_rdy,
	io_out_rd_req,
	io_out_wr_req,
	io_out_mem_or_reg,
	io_out_wr_byte_en,
	io_out_rd_num_dwords,
	io_out_addr,
	io_out_wr_d,
	io_out_rd_d,
	io_out_rd_rdy,
	io_out_busy,
	io_out_burst_wr_rdy
);
	input clock;
	input reset;
	input io_in0_rd_req;
	input [31:0] io_in0_addr;
	output [31:0] io_in0_rd_d;
	output io_in0_rd_rdy;
	output io_in0_busy;
	input io_in1_rd_req;
	input io_in1_wr_req;
	input io_in1_mem_or_reg;
	input [3:0] io_in1_wr_byte_en;
	input [31:0] io_in1_addr;
	input [31:0] io_in1_wr_d;
	output [31:0] io_in1_rd_d;
	output io_in1_rd_rdy;
	output io_in1_busy;
	output io_in1_burst_wr_rdy;
	output io_out_rd_req;
	output io_out_wr_req;
	output io_out_mem_or_reg;
	output [3:0] io_out_wr_byte_en;
	output [5:0] io_out_rd_num_dwords;
	output [31:0] io_out_addr;
	output [31:0] io_out_wr_d;
	input [31:0] io_out_rd_d;
	input io_out_rd_rdy;
	input io_out_busy;
	input io_out_burst_wr_rdy;
	reg grant;
	wire _T = ~grant;
	wire _T_1 = ~io_out_busy;
	wire _T_2 = ~io_out_burst_wr_rdy;
	wire _T_3 = _T_1 & _T_2;
	wire _T_4 = ~io_out_rd_req;
	wire _T_5 = _T_3 & _T_4;
	wire _T_6 = ~io_out_wr_req;
	wire _T_7 = _T_5 & _T_6;
	reg _T_8;
	wire _T_9 = ~_T_8;
	wire _T_10 = _T_7 & _T_9;
	reg _T_11;
	wire _T_12 = ~_T_11;
	wire _T_13 = _T_10 & _T_12;
	reg _T_14;
	wire _T_15 = ~_T_14;
	wire _T_16 = _T_13 & _T_15;
	reg _T_17;
	wire _T_18 = ~_T_17;
	wire _T_19 = _T_16 & _T_18;
	assign io_in0_rd_d = (_T ? io_out_rd_d : 32'h0);
	assign io_in0_rd_rdy = _T & io_out_rd_rdy;
	assign io_in0_busy = (_T ? io_out_busy : 1'h1);
	assign io_in1_rd_d = (_T ? 32'h0 : io_out_rd_d);
	assign io_in1_rd_rdy = (_T ? 1'h0 : io_out_rd_rdy);
	assign io_in1_busy = _T | io_out_busy;
	assign io_in1_burst_wr_rdy = (_T ? 1'h0 : io_out_burst_wr_rdy);
	assign io_out_rd_req = (_T ? io_in0_rd_req : io_in1_rd_req);
	assign io_out_wr_req = (_T ? 1'h0 : io_in1_wr_req);
	assign io_out_mem_or_reg = (_T ? 1'h0 : io_in1_mem_or_reg);
	assign io_out_wr_byte_en = (_T ? 4'h0 : io_in1_wr_byte_en);
	assign io_out_rd_num_dwords = (_T ? 6'h8 : 6'h1);
	assign io_out_addr = (_T ? io_in0_addr : io_in1_addr);
	assign io_out_wr_d = (_T ? 32'h0 : io_in1_wr_d);
	always @(posedge clock) begin
		if (reset)
			grant <= 1'h0;
		else if (_T_19)
			grant <= _T;
		_T_8 <= io_out_busy;
		_T_11 <= io_out_burst_wr_rdy;
		_T_14 <= io_out_rd_req;
		_T_17 <= io_out_wr_req;
	end
endmodule
module MemorySubsystem (
	clock,
	reset,
	io_flush_all,
	io_bus_cached_cyc,
	io_bus_cached_stb,
	io_bus_cached_we,
	io_bus_cached_sel,
	io_bus_cached_addr,
	io_bus_cached_data_wr,
	io_bus_cached_ack,
	io_bus_cached_err,
	io_bus_cached_data_rd,
	io_bus_uncached_cyc,
	io_bus_uncached_stb,
	io_bus_uncached_we,
	io_bus_uncached_sel,
	io_bus_uncached_addr,
	io_bus_uncached_data_wr,
	io_bus_uncached_ack,
	io_bus_uncached_err,
	io_bus_uncached_data_rd,
	io_cache_mem_addr,
	io_cache_mem_rd_d,
	io_cache_mem_we,
	io_cache_mem_we_sel,
	io_cache_mem_wr_d,
	io_main_mem_rd_req,
	io_main_mem_wr_req,
	io_main_mem_mem_or_reg,
	io_main_mem_wr_byte_en,
	io_main_mem_rd_num_dwords,
	io_main_mem_addr,
	io_main_mem_wr_d,
	io_main_mem_rd_d,
	io_main_mem_rd_rdy,
	io_main_mem_busy,
	io_main_mem_burst_wr_rdy
);
	input clock;
	input reset;
	input io_flush_all;
	input io_bus_cached_cyc;
	input io_bus_cached_stb;
	input io_bus_cached_we;
	input [3:0] io_bus_cached_sel;
	input [31:0] io_bus_cached_addr;
	input [31:0] io_bus_cached_data_wr;
	output io_bus_cached_ack;
	output io_bus_cached_err;
	output [31:0] io_bus_cached_data_rd;
	input io_bus_uncached_cyc;
	input io_bus_uncached_stb;
	input io_bus_uncached_we;
	input [3:0] io_bus_uncached_sel;
	input [31:0] io_bus_uncached_addr;
	input [31:0] io_bus_uncached_data_wr;
	output io_bus_uncached_ack;
	output io_bus_uncached_err;
	output [31:0] io_bus_uncached_data_rd;
	output [31:0] io_cache_mem_addr;
	input [31:0] io_cache_mem_rd_d;
	output io_cache_mem_we;
	output [3:0] io_cache_mem_we_sel;
	output [31:0] io_cache_mem_wr_d;
	output io_main_mem_rd_req;
	output io_main_mem_wr_req;
	output io_main_mem_mem_or_reg;
	output [3:0] io_main_mem_wr_byte_en;
	output [5:0] io_main_mem_rd_num_dwords;
	output [31:0] io_main_mem_addr;
	output [31:0] io_main_mem_wr_d;
	input [31:0] io_main_mem_rd_d;
	input io_main_mem_rd_rdy;
	input io_main_mem_busy;
	input io_main_mem_burst_wr_rdy;
	wire cache_clock;
	wire cache_reset;
	wire cache_io_flush_all;
	wire cache_io_bus_cyc;
	wire cache_io_bus_stb;
	wire cache_io_bus_we;
	wire [31:0] cache_io_bus_addr;
	wire cache_io_bus_ack;
	wire [31:0] cache_io_bus_data_rd;
	wire [31:0] cache_io_cache_mem_addr;
	wire [31:0] cache_io_cache_mem_rd_d;
	wire cache_io_cache_mem_we;
	wire [31:0] cache_io_cache_mem_wr_d;
	wire cache_io_main_mem_rd_req;
	wire [31:0] cache_io_main_mem_addr;
	wire [31:0] cache_io_main_mem_rd_d;
	wire cache_io_main_mem_rd_rdy;
	wire cache_io_main_mem_busy;
	wire direct_clock;
	wire direct_reset;
	wire direct_io_bus_cyc;
	wire direct_io_bus_stb;
	wire direct_io_bus_we;
	wire [3:0] direct_io_bus_sel;
	wire [31:0] direct_io_bus_addr;
	wire [31:0] direct_io_bus_data_wr;
	wire direct_io_bus_ack;
	wire [31:0] direct_io_bus_data_rd;
	wire direct_io_mem_rd_req;
	wire direct_io_mem_wr_req;
	wire direct_io_mem_mem_or_reg;
	wire [3:0] direct_io_mem_wr_byte_en;
	wire [31:0] direct_io_mem_addr;
	wire [31:0] direct_io_mem_wr_d;
	wire [31:0] direct_io_mem_rd_d;
	wire direct_io_mem_rd_rdy;
	wire direct_io_mem_busy;
	wire direct_io_mem_burst_wr_rdy;
	wire arbiter_clock;
	wire arbiter_reset;
	wire arbiter_io_in0_rd_req;
	wire [31:0] arbiter_io_in0_addr;
	wire [31:0] arbiter_io_in0_rd_d;
	wire arbiter_io_in0_rd_rdy;
	wire arbiter_io_in0_busy;
	wire arbiter_io_in1_rd_req;
	wire arbiter_io_in1_wr_req;
	wire arbiter_io_in1_mem_or_reg;
	wire [3:0] arbiter_io_in1_wr_byte_en;
	wire [31:0] arbiter_io_in1_addr;
	wire [31:0] arbiter_io_in1_wr_d;
	wire [31:0] arbiter_io_in1_rd_d;
	wire arbiter_io_in1_rd_rdy;
	wire arbiter_io_in1_busy;
	wire arbiter_io_in1_burst_wr_rdy;
	wire arbiter_io_out_rd_req;
	wire arbiter_io_out_wr_req;
	wire arbiter_io_out_mem_or_reg;
	wire [3:0] arbiter_io_out_wr_byte_en;
	wire [5:0] arbiter_io_out_rd_num_dwords;
	wire [31:0] arbiter_io_out_addr;
	wire [31:0] arbiter_io_out_wr_d;
	wire [31:0] arbiter_io_out_rd_d;
	wire arbiter_io_out_rd_rdy;
	wire arbiter_io_out_busy;
	wire arbiter_io_out_burst_wr_rdy;
	ICache cache(
		.clock(cache_clock),
		.reset(cache_reset),
		.io_flush_all(cache_io_flush_all),
		.io_bus_cyc(cache_io_bus_cyc),
		.io_bus_stb(cache_io_bus_stb),
		.io_bus_we(cache_io_bus_we),
		.io_bus_addr(cache_io_bus_addr),
		.io_bus_ack(cache_io_bus_ack),
		.io_bus_data_rd(cache_io_bus_data_rd),
		.io_cache_mem_addr(cache_io_cache_mem_addr),
		.io_cache_mem_rd_d(cache_io_cache_mem_rd_d),
		.io_cache_mem_we(cache_io_cache_mem_we),
		.io_cache_mem_wr_d(cache_io_cache_mem_wr_d),
		.io_main_mem_rd_req(cache_io_main_mem_rd_req),
		.io_main_mem_addr(cache_io_main_mem_addr),
		.io_main_mem_rd_d(cache_io_main_mem_rd_d),
		.io_main_mem_rd_rdy(cache_io_main_mem_rd_rdy),
		.io_main_mem_busy(cache_io_main_mem_busy)
	);
	WishboneMemoryBridge direct(
		.clock(direct_clock),
		.reset(direct_reset),
		.io_bus_cyc(direct_io_bus_cyc),
		.io_bus_stb(direct_io_bus_stb),
		.io_bus_we(direct_io_bus_we),
		.io_bus_sel(direct_io_bus_sel),
		.io_bus_addr(direct_io_bus_addr),
		.io_bus_data_wr(direct_io_bus_data_wr),
		.io_bus_ack(direct_io_bus_ack),
		.io_bus_data_rd(direct_io_bus_data_rd),
		.io_mem_rd_req(direct_io_mem_rd_req),
		.io_mem_wr_req(direct_io_mem_wr_req),
		.io_mem_mem_or_reg(direct_io_mem_mem_or_reg),
		.io_mem_wr_byte_en(direct_io_mem_wr_byte_en),
		.io_mem_addr(direct_io_mem_addr),
		.io_mem_wr_d(direct_io_mem_wr_d),
		.io_mem_rd_d(direct_io_mem_rd_d),
		.io_mem_rd_rdy(direct_io_mem_rd_rdy),
		.io_mem_busy(direct_io_mem_busy),
		.io_mem_burst_wr_rdy(direct_io_mem_burst_wr_rdy)
	);
	MemoryArbiter arbiter(
		.clock(arbiter_clock),
		.reset(arbiter_reset),
		.io_in0_rd_req(arbiter_io_in0_rd_req),
		.io_in0_addr(arbiter_io_in0_addr),
		.io_in0_rd_d(arbiter_io_in0_rd_d),
		.io_in0_rd_rdy(arbiter_io_in0_rd_rdy),
		.io_in0_busy(arbiter_io_in0_busy),
		.io_in1_rd_req(arbiter_io_in1_rd_req),
		.io_in1_wr_req(arbiter_io_in1_wr_req),
		.io_in1_mem_or_reg(arbiter_io_in1_mem_or_reg),
		.io_in1_wr_byte_en(arbiter_io_in1_wr_byte_en),
		.io_in1_addr(arbiter_io_in1_addr),
		.io_in1_wr_d(arbiter_io_in1_wr_d),
		.io_in1_rd_d(arbiter_io_in1_rd_d),
		.io_in1_rd_rdy(arbiter_io_in1_rd_rdy),
		.io_in1_busy(arbiter_io_in1_busy),
		.io_in1_burst_wr_rdy(arbiter_io_in1_burst_wr_rdy),
		.io_out_rd_req(arbiter_io_out_rd_req),
		.io_out_wr_req(arbiter_io_out_wr_req),
		.io_out_mem_or_reg(arbiter_io_out_mem_or_reg),
		.io_out_wr_byte_en(arbiter_io_out_wr_byte_en),
		.io_out_rd_num_dwords(arbiter_io_out_rd_num_dwords),
		.io_out_addr(arbiter_io_out_addr),
		.io_out_wr_d(arbiter_io_out_wr_d),
		.io_out_rd_d(arbiter_io_out_rd_d),
		.io_out_rd_rdy(arbiter_io_out_rd_rdy),
		.io_out_busy(arbiter_io_out_busy),
		.io_out_burst_wr_rdy(arbiter_io_out_burst_wr_rdy)
	);
	assign io_bus_cached_ack = cache_io_bus_ack;
	assign io_bus_cached_err = 1'h0;
	assign io_bus_cached_data_rd = cache_io_bus_data_rd;
	assign io_bus_uncached_ack = direct_io_bus_ack;
	assign io_bus_uncached_err = 1'h0;
	assign io_bus_uncached_data_rd = direct_io_bus_data_rd;
	assign io_cache_mem_addr = cache_io_cache_mem_addr;
	assign io_cache_mem_we = cache_io_cache_mem_we;
	assign io_cache_mem_we_sel = 4'hf;
	assign io_cache_mem_wr_d = cache_io_cache_mem_wr_d;
	assign io_main_mem_rd_req = arbiter_io_out_rd_req;
	assign io_main_mem_wr_req = arbiter_io_out_wr_req;
	assign io_main_mem_mem_or_reg = arbiter_io_out_mem_or_reg;
	assign io_main_mem_wr_byte_en = arbiter_io_out_wr_byte_en;
	assign io_main_mem_rd_num_dwords = arbiter_io_out_rd_num_dwords;
	assign io_main_mem_addr = arbiter_io_out_addr;
	assign io_main_mem_wr_d = arbiter_io_out_wr_d;
	assign cache_clock = clock;
	assign cache_reset = reset;
	assign cache_io_flush_all = io_flush_all;
	assign cache_io_bus_cyc = io_bus_cached_cyc;
	assign cache_io_bus_stb = io_bus_cached_stb;
	assign cache_io_bus_we = io_bus_cached_we;
	assign cache_io_bus_addr = io_bus_cached_addr;
	assign cache_io_cache_mem_rd_d = io_cache_mem_rd_d;
	assign cache_io_main_mem_rd_d = arbiter_io_in0_rd_d;
	assign cache_io_main_mem_rd_rdy = arbiter_io_in0_rd_rdy;
	assign cache_io_main_mem_busy = arbiter_io_in0_busy;
	assign direct_clock = clock;
	assign direct_reset = reset;
	assign direct_io_bus_cyc = io_bus_uncached_cyc;
	assign direct_io_bus_stb = io_bus_uncached_stb;
	assign direct_io_bus_we = io_bus_uncached_we;
	assign direct_io_bus_sel = io_bus_uncached_sel;
	assign direct_io_bus_addr = io_bus_uncached_addr;
	assign direct_io_bus_data_wr = io_bus_uncached_data_wr;
	assign direct_io_mem_rd_d = arbiter_io_in1_rd_d;
	assign direct_io_mem_rd_rdy = arbiter_io_in1_rd_rdy;
	assign direct_io_mem_busy = arbiter_io_in1_busy;
	assign direct_io_mem_burst_wr_rdy = arbiter_io_in1_burst_wr_rdy;
	assign arbiter_clock = clock;
	assign arbiter_reset = reset;
	assign arbiter_io_in0_rd_req = cache_io_main_mem_rd_req;
	assign arbiter_io_in0_addr = cache_io_main_mem_addr;
	assign arbiter_io_in1_rd_req = direct_io_mem_rd_req;
	assign arbiter_io_in1_wr_req = direct_io_mem_wr_req;
	assign arbiter_io_in1_mem_or_reg = direct_io_mem_mem_or_reg;
	assign arbiter_io_in1_wr_byte_en = direct_io_mem_wr_byte_en;
	assign arbiter_io_in1_addr = direct_io_mem_addr;
	assign arbiter_io_in1_wr_d = direct_io_mem_wr_d;
	assign arbiter_io_out_rd_d = io_main_mem_rd_d;
	assign arbiter_io_out_rd_rdy = io_main_mem_rd_rdy;
	assign arbiter_io_out_busy = io_main_mem_busy;
	assign arbiter_io_out_burst_wr_rdy = io_main_mem_burst_wr_rdy;
endmodule
`default_nettype none
module uart_tx (
	o_ready,
	o_out,
	i_divider,
	i_data,
	i_valid,
	i_clk,
	i_rst
);
	output wire o_ready;
	output reg o_out;
	input wire [15:0] i_divider;
	input wire [7:0] i_data;
	input wire i_valid;
	input wire i_clk;
	input wire i_rst;
	reg [16:0] counter;
	reg [3:0] state;
	reg [7:0] data_send;
	assign o_ready = (state == 0) && ~i_rst;
	always @(posedge i_clk)
		if (i_rst) begin
			counter <= 10;
			state <= 0;
			data_send <= 0;
		end
		else begin
			counter <= 10;
			if (state == 0) begin
				if (i_valid) begin
					state <= 1;
					data_send <= i_data;
					counter <= 2 * i_divider;
				end
			end
			else if (counter == 0) begin
				if (state == 10)
					state <= 0;
				else begin
					state <= state + 1;
					if (state == 10)
						counter <= (2 * i_divider) - 1;
					else
						counter <= 2 * i_divider;
				end
			end
			else
				counter <= counter - 1;
		end
	always @(*)
		if (i_rst)
			o_out = 1;
		else if (state == 0)
			o_out = 1;
		else if (state == 1)
			o_out = 0;
		else if (state == 10)
			o_out = 1;
		else
			o_out = data_send[state - 2];
endmodule
`default_nettype none
module uart_rx (
	o_data,
	o_valid,
	i_divider,
	i_in,
	i_clk,
	i_rst
);
	output reg [7:0] o_data;
	output reg o_valid;
	input wire [15:0] i_divider;
	input wire i_in;
	input wire i_clk;
	input wire i_rst;
	reg [16:0] counter;
	reg [3:0] state = 0;
	always @(posedge i_clk)
		if (i_rst) begin
			counter <= 10;
			state <= 0;
			o_valid <= 0;
		end
		else begin
			o_valid <= 0;
			counter <= 10;
			if (state == 0) begin
				if (i_in == 0) begin
					state <= 1;
					counter <= 3 * i_divider;
				end
			end
			else if (counter == 0) begin
				if (state == 9) begin
					if (i_in == 1)
						o_valid <= 1;
					state <= 0;
				end
				else begin
					state <= state + 1;
					o_data[state - 1] <= i_in;
					counter <= 2 * i_divider;
				end
			end
			else
				counter <= counter - 1;
		end
endmodule
`default_nettype none
module uart_fifo (
	i_rd_en,
	o_rd_data,
	o_rd_valid,
	i_wr_en,
	i_wr_data,
	o_empty,
	o_full,
	i_clk,
	i_rst
);
	parameter WIDTH = 9;
	parameter DEPTH = 128;
	input wire i_rd_en;
	output reg [WIDTH - 1:0] o_rd_data;
	output reg o_rd_valid;
	input wire i_wr_en;
	input wire [WIDTH - 1:0] i_wr_data;
	output wire o_empty;
	output wire o_full;
	input wire i_clk;
	input wire i_rst;
	localparam ADDR_WIDTH = $clog2(DEPTH);
	reg [ADDR_WIDTH - 1:0] wr_ptr;
	reg [ADDR_WIDTH - 1:0] rd_ptr;
	reg [ADDR_WIDTH:0] len = 0;
	reg [WIDTH - 1:0] ram [0:DEPTH - 1];
	assign o_empty = (len == 0) && ~i_rst;
	assign o_full = (len == DEPTH) && ~i_rst;
	always @(posedge i_clk)
		if (i_rst)
			wr_ptr <= 0;
		else if (i_wr_en) begin
			wr_ptr <= wr_ptr + 1;
			ram[wr_ptr] <= i_wr_data;
			if (o_full)
				$display("ERROR: WROTE TO FULL FIFO");
		end
	always @(posedge i_clk) begin
		o_rd_valid <= 0;
		if (i_rst)
			rd_ptr <= 0;
		else if (i_rd_en) begin
			rd_ptr <= rd_ptr + 1;
			o_rd_data <= ram[rd_ptr];
			o_rd_valid <= ~o_empty;
			if (o_empty)
				$display("ERROR: READ FROM EMPTY FIFO");
		end
	end
	always @(posedge i_clk)
		if (i_rst)
			len <= 0;
		else if ((i_rd_en && ~i_wr_en) && ~o_empty)
			len <= len - 1;
		else if ((i_wr_en && ~i_rd_en) && ~o_full)
			len <= len + 1;
endmodule
`default_nettype none
module wbuart (
	i_wb_cyc,
	i_wb_stb,
	i_wb_we,
	i_wb_addr,
	i_wb_data,
	o_wb_ack,
	o_wb_err,
	o_wb_data,
	o_tx,
	i_rx,
	i_clk,
	i_rst
);
	parameter FIFO_DEPTH = 8;
	parameter ADDR_STATUS = 4'h0;
	parameter ADDR_CONFIG = 4'h4;
	parameter ADDR_WRITE = 4'h8;
	parameter ADDR_READ = 4'hC;
	parameter DEFAULT_DIVIDER = 217;
	parameter USE_SYNC = 1;
	input wire i_wb_cyc;
	input wire i_wb_stb;
	input wire i_wb_we;
	input wire [3:0] i_wb_addr;
	input wire [31:0] i_wb_data;
	output reg o_wb_ack;
	output reg o_wb_err;
	output reg [31:0] o_wb_data;
	output wire o_tx;
	input wire i_rx;
	input wire i_clk;
	input wire i_rst;
	reg [15:0] divider;
	wire uart_tx_ready;
	wire [7:0] uart_tx_data;
	wire uart_tx_valid;
	uart_tx tx_ctrl(
		.o_ready(uart_tx_ready),
		.o_out(o_tx),
		.i_data(uart_tx_data[7:0]),
		.i_valid(uart_tx_valid),
		.i_divider(divider),
		.i_clk(i_clk),
		.i_rst(i_rst)
	);
	wire uart_tx_fifo_empty;
	wire uart_tx_fifo_full;
	wire uart_tx_write_en = ((i_wb_addr == ADDR_WRITE) && ~uart_tx_fifo_full) && ((((i_wb_cyc && i_wb_stb) && i_wb_we) && ~o_wb_ack) && ~o_wb_err);
	uart_fifo #(
		.WIDTH(8),
		.DEPTH(FIFO_DEPTH)
	) tx_fifo(
		.i_rd_en((uart_tx_ready && ~uart_tx_fifo_empty) && ~uart_tx_valid),
		.o_rd_data(uart_tx_data),
		.o_rd_valid(uart_tx_valid),
		.i_wr_en(uart_tx_write_en),
		.i_wr_data(i_wb_data),
		.o_empty(uart_tx_fifo_empty),
		.o_full(uart_tx_fifo_full),
		.i_clk(i_clk),
		.i_rst(i_rst)
	);
	wire rx;
	sync_2ff #(.DEFAULT(1)) rx_sync(
		.i_in(i_rx),
		.o_out(rx),
		.i_clk(i_clk),
		.i_rst(i_rst)
	);
	wire [7:0] uart_rx_data;
	wire uart_rx_valid;
	uart_rx rx_ctrl(
		.o_data(uart_rx_data),
		.o_valid(uart_rx_valid),
		.i_in((USE_SYNC ? rx : i_rx)),
		.i_divider(divider),
		.i_clk(i_clk),
		.i_rst(i_rst)
	);
	wire uart_rx_fifo_empty;
	wire uart_rx_fifo_full;
	wire uart_rx_read_en = ((i_wb_addr == ADDR_READ) && ~uart_rx_fifo_empty) && (((i_wb_cyc && i_wb_stb) && ~o_wb_ack) && ~o_wb_err);
	wire [7:0] uart_rx_fifo_data;
	wire uart_rx_fifo_valid;
	uart_fifo #(
		.WIDTH(8),
		.DEPTH(FIFO_DEPTH)
	) rx_fifo(
		.i_rd_en(uart_rx_read_en),
		.o_rd_data(uart_rx_fifo_data),
		.o_rd_valid(uart_rx_fifo_valid),
		.i_wr_en(uart_rx_valid & ~uart_rx_fifo_full),
		.i_wr_data(uart_rx_data[7:0]),
		.o_empty(uart_rx_fifo_empty),
		.o_full(uart_rx_fifo_full),
		.i_clk(i_clk),
		.i_rst(i_rst)
	);
	reg [31:0] last_addr;
	always @(posedge i_clk) begin
		o_wb_ack <= 0;
		o_wb_err <= 0;
		last_addr <= i_wb_addr;
		if (i_rst)
			divider <= DEFAULT_DIVIDER;
		else if (((i_wb_cyc && i_wb_stb) && ~o_wb_ack) && ~o_wb_err)
			if ((((i_wb_addr == ADDR_READ) || (i_wb_addr == ADDR_WRITE)) || (i_wb_addr == ADDR_STATUS)) || (i_wb_addr == ADDR_CONFIG)) begin
				o_wb_ack <= 1;
				if (i_wb_we && (i_wb_addr == ADDR_CONFIG))
					divider <= i_wb_data[15:0];
			end
			else
				o_wb_err <= 1;
	end
	always @(*) begin
		o_wb_data = 0;
		if (uart_rx_fifo_valid)
			o_wb_data = {23'b0, 1'b1, uart_rx_fifo_data};
		else if (last_addr == ADDR_CONFIG)
			o_wb_data = {16'b0, divider};
		else if (last_addr == ADDR_STATUS)
			o_wb_data = {28'b0, uart_tx_fifo_full, uart_tx_fifo_empty, uart_rx_fifo_full, uart_rx_fifo_empty};
		else
			o_wb_data = 0;
	end
endmodule
`default_nettype none
module sync_2ff (
	o_out,
	i_in,
	i_clk,
	i_rst
);
	parameter DEFAULT = 0;
	parameter WIDTH = 1;
	output reg [WIDTH - 1:0] o_out = DEFAULT;
	input wire [WIDTH - 1:0] i_in;
	input wire i_clk;
	input wire i_rst;
	reg [WIDTH - 1:0] sync = DEFAULT;
	always @(posedge i_clk)
		if (i_rst) begin
			sync <= DEFAULT;
			o_out <= DEFAULT;
		end
		else begin
			sync <= i_in;
			o_out <= sync;
		end
endmodule
`default_nettype none
module wbdbgbus (
	o_tx,
	i_rx,
	o_wb_cyc,
	o_wb_stb,
	o_wb_we,
	o_wb_addr,
	o_wb_data,
	i_wb_ack,
	i_wb_err,
	i_wb_stall,
	i_wb_data,
	i_interrupt_1,
	i_interrupt_2,
	i_interrupt_3,
	i_interrupt_4,
	i_clk
);
	parameter CLK_FREQ = 25000000;
	parameter UART_BAUD = 9600;
	parameter DROP_CLKS = 2500000;
	parameter FIFO_DEPTH = 128;
	output wire o_tx;
	input wire i_rx;
	output wire o_wb_cyc;
	output wire o_wb_stb;
	output wire o_wb_we;
	output wire [31:0] o_wb_addr;
	output wire [31:0] o_wb_data;
	input wire i_wb_ack;
	input wire i_wb_err;
	input wire i_wb_stall;
	input wire [31:0] i_wb_data;
	input wire i_interrupt_1;
	input wire i_interrupt_2;
	input wire i_interrupt_3;
	input wire i_interrupt_4;
	input wire i_clk;
	localparam RESP_INT_1 = 4'b1000;
	localparam RESP_INT_2 = 4'b1001;
	localparam RESP_INT_3 = 4'b1010;
	localparam RESP_INT_4 = 4'b1011;
	wire [7:0] uart_rx_data;
	wire uart_rx_valid;
	reg [7:0] uart_tx_data;
	wire uart_tx_ready;
	reg uart_tx_valid = 0;
	wbdbgbus_uart_rx #(
		.CLK_FREQ(CLK_FREQ),
		.BAUD(UART_BAUD)
	) uart_rx(
		.o_data(uart_rx_data),
		.o_valid(uart_rx_valid),
		.i_in(i_rx),
		.i_clk(i_clk)
	);
	wbdbgbus_uart_tx #(
		.CLK_FREQ(CLK_FREQ),
		.BAUD(UART_BAUD)
	) uart_tx(
		.o_ready(uart_tx_ready),
		.o_out(o_tx),
		.i_data(uart_tx_data),
		.i_valid(uart_tx_valid),
		.i_clk(i_clk)
	);
	reg cmd_reset = 0;
	reg cmd_valid = 0;
	wire cmd_ready;
	reg [35:0] cmd_data;
	wire resp_valid;
	wire [35:0] resp_data;
	wbdbgbusmaster #(.TIMEOUT_CLKS(DROP_CLKS)) wbdbgbusmaster(
		.i_cmd_reset(cmd_reset),
		.i_cmd_valid(cmd_valid),
		.o_cmd_ready(cmd_ready),
		.i_cmd_data(cmd_data),
		.o_resp_valid(resp_valid),
		.o_resp_data(resp_data),
		.o_wb_cyc(o_wb_cyc),
		.o_wb_stb(o_wb_stb),
		.o_wb_we(o_wb_we),
		.o_wb_addr(o_wb_addr),
		.o_wb_data(o_wb_data),
		.i_wb_ack(i_wb_ack),
		.i_wb_err(i_wb_err),
		.i_wb_stall(i_wb_stall),
		.i_wb_data(i_wb_data),
		.i_clk(i_clk)
	);
	reg cmd_fifo_rd_en = 0;
	wire [35:0] cmd_fifo_rd_data;
	wire cmd_fifo_rd_valid;
	reg cmd_fifo_wr_en = 0;
	reg [35:0] cmd_fifo_wr_data = 0;
	wire cmd_fifo_empty;
	wire cmd_fifo_full;
	wbdbgbus_fifo #(
		.WIDTH(36),
		.DEPTH(FIFO_DEPTH)
	) cmd_fifo(
		.i_rd_en(cmd_fifo_rd_en),
		.o_rd_data(cmd_fifo_rd_data),
		.o_rd_valid(cmd_fifo_rd_valid),
		.i_wr_en(cmd_fifo_wr_en),
		.i_wr_data(cmd_fifo_wr_data),
		.o_empty(cmd_fifo_empty),
		.o_full(cmd_fifo_full),
		.i_clk(i_clk),
		.i_rst(cmd_reset)
	);
	reg resp_fifo_rd_en = 0;
	wire [35:0] resp_fifo_rd_data;
	wire resp_fifo_rd_valid;
	reg resp_fifo_wr_en = 0;
	reg [35:0] resp_fifo_wr_data = 0;
	wire resp_fifo_empty;
	wire resp_fifo_full;
	wbdbgbus_fifo #(
		.WIDTH(36),
		.DEPTH(FIFO_DEPTH)
	) resp_fifo(
		.i_rd_en(resp_fifo_rd_en),
		.o_rd_data(resp_fifo_rd_data),
		.o_rd_valid(resp_fifo_rd_valid),
		.i_wr_en(resp_fifo_wr_en),
		.i_wr_data(resp_fifo_wr_data),
		.o_empty(resp_fifo_empty),
		.o_full(resp_fifo_full),
		.i_clk(i_clk),
		.i_rst(cmd_reset)
	);
	reg [39:0] transmit_data = 0;
	reg [2:0] transmit_state = 0;
	reg interrupt_1_last = 0;
	reg interrupt_2_last = 0;
	reg interrupt_3_last = 0;
	reg interrupt_4_last = 0;
	reg interrupt_1_rising = 0;
	reg interrupt_2_rising = 0;
	reg interrupt_3_rising = 0;
	reg interrupt_4_rising = 0;
	always @(posedge i_clk) begin
		interrupt_1_last <= i_interrupt_1;
		interrupt_2_last <= i_interrupt_2;
		interrupt_3_last <= i_interrupt_3;
		interrupt_4_last <= i_interrupt_4;
	end
	always @(posedge i_clk) begin
		resp_fifo_wr_en <= 0;
		if (resp_valid && ~resp_fifo_full) begin
			resp_fifo_wr_data <= resp_data;
			resp_fifo_wr_en <= 1;
		end
	end
	always @(posedge i_clk) begin
		uart_tx_valid <= 0;
		resp_fifo_rd_en <= 0;
		if (i_interrupt_1 && ~interrupt_1_last)
			interrupt_1_rising <= 1;
		if (i_interrupt_2 && ~interrupt_2_last)
			interrupt_2_rising <= 1;
		if (i_interrupt_3 && ~interrupt_3_last)
			interrupt_3_rising <= 1;
		if (i_interrupt_4 && ~interrupt_4_last)
			interrupt_4_rising <= 1;
		if ((((((((transmit_state == 0) && ~resp_fifo_empty) && ~resp_fifo_rd_valid) && ~resp_fifo_rd_en) && ~interrupt_1_rising) && ~interrupt_2_rising) && ~interrupt_3_rising) && ~interrupt_4_rising)
			resp_fifo_rd_en <= 1;
		if (transmit_state == 0) begin
			if (resp_fifo_rd_valid) begin
				transmit_data <= {4'b0000, resp_fifo_rd_data};
				transmit_state <= 1;
			end
			else if (resp_fifo_rd_en)
				;
			else if (interrupt_1_rising) begin
				transmit_data <= {4'b0000, RESP_INT_1, 32'b0};
				transmit_state <= 1;
				interrupt_1_rising <= 0;
			end
			else if (interrupt_2_rising) begin
				transmit_data <= {4'b0000, RESP_INT_2, 32'b0};
				transmit_state <= 1;
				interrupt_2_rising <= 0;
			end
			else if (interrupt_3_rising) begin
				transmit_data <= {4'b0000, RESP_INT_3, 32'b0};
				transmit_state <= 1;
				interrupt_3_rising <= 0;
			end
			else if (interrupt_4_rising) begin
				transmit_data <= {4'b0000, RESP_INT_4, 32'b0};
				transmit_state <= 1;
				interrupt_4_rising <= 0;
			end
		end
		else if (uart_tx_ready && ~uart_tx_valid) begin
			case (transmit_state)
				1: uart_tx_data <= transmit_data[39:32];
				2: uart_tx_data <= transmit_data[31:24];
				3: uart_tx_data <= transmit_data[23:16];
				4: uart_tx_data <= transmit_data[15:8];
				5: uart_tx_data <= transmit_data[7:0];
				default: uart_tx_data <= 0;
			endcase
			uart_tx_valid <= 1;
			transmit_state <= transmit_state + 1;
			if (transmit_state == 5)
				transmit_state <= 0;
		end
	end
	reg [39:0] recieve_data = 0;
	reg [2:0] recieve_state = 0;
	reg [$clog2(DROP_CLKS):0] drop_timer = DROP_CLKS;
	always @(posedge i_clk) begin
		cmd_reset <= 0;
		cmd_fifo_wr_en <= 0;
		if (uart_rx_valid) begin
			case (recieve_state)
				0: recieve_data[39:32] <= uart_rx_data;
				1: recieve_data[31:24] <= uart_rx_data;
				2: recieve_data[23:16] <= uart_rx_data;
				3: recieve_data[15:8] <= uart_rx_data;
				4: recieve_data[7:0] <= uart_rx_data;
			endcase
			recieve_state <= recieve_state + 1;
			drop_timer <= DROP_CLKS;
			if (recieve_state == 4)
				if (recieve_data[35:32] == 4'b1111) begin
					cmd_reset <= 1;
					recieve_state <= 0;
				end
				else begin
					if (~cmd_fifo_full) begin
						cmd_fifo_wr_en <= 1;
						cmd_fifo_wr_data <= {recieve_data[35:8], uart_rx_data};
					end
					recieve_state <= 0;
				end
		end
		else if (recieve_state > 0) begin
			drop_timer <= drop_timer - 1;
			if (drop_timer == 1)
				recieve_state <= 0;
		end
	end
	always @(posedge i_clk) begin
		cmd_valid <= 0;
		cmd_fifo_rd_en <= 0;
		if (((((~cmd_reset && cmd_ready) && ~cmd_fifo_empty) && ~cmd_fifo_rd_en) && ~cmd_fifo_rd_valid) && ~cmd_valid)
			cmd_fifo_rd_en <= 1;
		if ((cmd_ready && cmd_fifo_rd_valid) && ~cmd_reset) begin
			cmd_valid <= 1;
			cmd_data <= cmd_fifo_rd_data;
		end
	end
endmodule
module wbdbgbusmaster (
	i_cmd_reset,
	i_cmd_valid,
	o_cmd_ready,
	i_cmd_data,
	o_resp_valid,
	o_resp_data,
	o_wb_cyc,
	o_wb_stb,
	o_wb_we,
	o_wb_addr,
	o_wb_data,
	i_wb_ack,
	i_wb_err,
	i_wb_stall,
	i_wb_data,
	i_clk
);
	parameter TIMEOUT_CLKS = 100000;
	input wire i_cmd_reset;
	input wire i_cmd_valid;
	output wire o_cmd_ready;
	input wire [35:0] i_cmd_data;
	output reg o_resp_valid = 0;
	output reg [35:0] o_resp_data;
	output reg o_wb_cyc = 0;
	output reg o_wb_stb = 0;
	output reg o_wb_we = 0;
	output reg [31:0] o_wb_addr = 0;
	output reg [31:0] o_wb_data = 0;
	input wire i_wb_ack;
	input wire i_wb_err;
	input wire i_wb_stall;
	input wire [31:0] i_wb_data;
	input wire i_clk;
	localparam CMD_READ_REQ = 4'b0001;
	localparam CMD_WRITE_REQ = 4'b0010;
	localparam CMD_SET_ADDR = 4'b0011;
	localparam CMD_SET_ADDR_INC = 4'b0111;
	localparam RESP_READ_RESP = 4'b0001;
	localparam RESP_WRITE_ACK = 4'b0010;
	localparam RESP_ADDR_ACK = 4'b0011;
	localparam RESP_BUS_ERROR = 4'b0100;
	localparam RESP_BUS_RESET = 4'b0101;
	reg [$clog2(TIMEOUT_CLKS):0] timeout_ctr = TIMEOUT_CLKS;
	reg addr_inc = 0;
	assign o_cmd_ready = ~o_wb_cyc;
	wire cmd_recv = i_cmd_valid && o_cmd_ready;
	wire [3:0] cmd_inst = i_cmd_data[35:32];
	wire [31:0] cmd_data = i_cmd_data[31:0];
	always @(posedge i_clk)
		if ((i_wb_err || i_cmd_reset) || (timeout_ctr == 1)) begin
			timeout_ctr <= TIMEOUT_CLKS;
			o_wb_cyc <= 0;
			o_wb_stb <= 0;
		end
		else if (o_wb_cyc) begin
			timeout_ctr <= timeout_ctr - 1;
			if (i_wb_ack) begin
				o_wb_cyc <= 0;
				o_wb_stb <= 0;
			end
		end
		else begin
			timeout_ctr <= TIMEOUT_CLKS;
			if (cmd_recv && ((cmd_inst == CMD_READ_REQ) || (cmd_inst == CMD_WRITE_REQ))) begin
				o_wb_cyc <= 1;
				o_wb_stb <= 1;
			end
		end
	reg last_stb;
	always @(posedge i_clk) begin
		last_stb <= o_wb_stb;
		if (cmd_recv) begin
			if ((cmd_inst == CMD_SET_ADDR) || (cmd_inst == CMD_SET_ADDR_INC)) begin
				o_wb_addr <= cmd_data;
				addr_inc <= cmd_inst == CMD_SET_ADDR_INC;
			end
		end
		else if (~o_wb_stb && last_stb)
			o_wb_addr <= o_wb_addr + addr_inc;
	end
	always @(posedge i_clk)
		if (~o_wb_cyc)
			o_wb_we <= cmd_recv && (cmd_inst == CMD_WRITE_REQ);
	always @(posedge i_clk)
		if (~o_wb_cyc)
			o_wb_data <= cmd_data;
	always @(posedge i_clk) begin
		o_resp_valid <= 0;
		if (i_cmd_reset) begin
			o_resp_valid <= 1;
			o_resp_data <= {RESP_BUS_RESET, 32'b0};
		end
		else if (i_wb_err || (timeout_ctr == 1)) begin
			o_resp_valid <= 1;
			o_resp_data <= {RESP_BUS_ERROR, 32'b0};
		end
		else if (o_wb_cyc && i_wb_ack) begin
			o_resp_valid <= 1;
			if (o_wb_we)
				o_resp_data <= {RESP_WRITE_ACK, 32'b0};
			else
				o_resp_data <= {RESP_READ_RESP, i_wb_data};
		end
		else if (cmd_recv && ((cmd_inst == CMD_SET_ADDR) || (cmd_inst == CMD_SET_ADDR_INC))) begin
			o_resp_valid <= 1;
			o_resp_data <= {RESP_ADDR_ACK, 32'b0};
		end
	end
endmodule
module wbdbgbus_fifo (
	i_rd_en,
	o_rd_data,
	o_rd_valid,
	i_wr_en,
	i_wr_data,
	o_empty,
	o_full,
	i_clk,
	i_rst
);
	parameter WIDTH = 36;
	parameter DEPTH = 128;
	input wire i_rd_en;
	output reg [WIDTH - 1:0] o_rd_data;
	output reg o_rd_valid = 0;
	input wire i_wr_en;
	input wire [WIDTH - 1:0] i_wr_data;
	output wire o_empty;
	output wire o_full;
	input wire i_clk;
	input wire i_rst;
	localparam ADDR_WIDTH = $clog2(DEPTH);
	reg [ADDR_WIDTH - 1:0] wr_ptr = 0;
	reg [ADDR_WIDTH - 1:0] rd_ptr = 0;
	reg [ADDR_WIDTH:0] len = 0;
	reg [WIDTH - 1:0] ram [0:DEPTH - 1];
	assign o_empty = len == 0;
	assign o_full = len == DEPTH;
	always @(posedge i_clk)
		if (i_rst)
			wr_ptr <= 0;
		else if (i_wr_en) begin
			wr_ptr <= wr_ptr + 1;
			ram[wr_ptr] <= i_wr_data;
			if (o_full)
				$display("ERROR: WROTE TO FULL FIFO");
		end
	always @(posedge i_clk) begin
		o_rd_valid <= 0;
		if (i_rst)
			rd_ptr <= 0;
		else if (i_rd_en) begin
			rd_ptr <= rd_ptr + 1;
			o_rd_data <= ram[rd_ptr];
			o_rd_valid <= ~o_empty;
			if (o_empty)
				$display("ERROR: READ FROM EMPTY FIFO");
		end
	end
	always @(posedge i_clk)
		if (i_rst)
			len <= 0;
		else if ((i_rd_en && ~i_wr_en) && ~o_empty)
			len <= len - 1;
		else if ((i_wr_en && ~i_rd_en) && ~o_full)
			len <= len + 1;
endmodule
module wbdbgbus_uart_rx (
	o_data,
	o_valid,
	i_in,
	i_clk
);
	parameter CLK_FREQ = 250000;
	parameter BAUD = 9600;
	output reg [7:0] o_data;
	output reg o_valid;
	input wire i_in;
	input wire i_clk;
	parameter CLKS_PER_BIT = CLK_FREQ / BAUD;
	parameter CLKS_PER_1_5_BIT = (3 * CLKS_PER_BIT) / 2;
	reg [$clog2(CLKS_PER_BIT * 2):0] counter;
	reg [3:0] state = 0;
	always @(posedge i_clk) begin
		o_valid <= 0;
		counter <= 10;
		if (state == 0) begin
			if (i_in == 0) begin
				state <= 1;
				counter <= CLKS_PER_1_5_BIT;
			end
		end
		else if (counter == 0) begin
			if (state == 9) begin
				if (i_in == 1)
					o_valid <= 1;
				state <= 0;
			end
			else begin
				state <= state + 1;
				o_data[state - 1] <= i_in;
				counter <= CLKS_PER_BIT;
			end
		end
		else
			counter <= counter - 1;
	end
endmodule
module wbdbgbus_uart_tx (
	o_ready,
	o_out,
	i_data,
	i_valid,
	i_clk
);
	parameter CLK_FREQ = 250000;
	parameter BAUD = 9600;
	output wire o_ready;
	output reg o_out;
	input wire [7:0] i_data;
	input wire i_valid;
	input wire i_clk;
	parameter CLKS_PER_BIT = CLK_FREQ / BAUD;
	reg [$clog2(CLKS_PER_BIT) + 1:0] counter;
	reg [3:0] state = 0;
	reg [7:0] data_send;
	assign o_ready = state == 0;
	always @(posedge i_clk) begin
		counter <= 10;
		if (state == 0) begin
			if (i_valid) begin
				state <= 1;
				data_send <= i_data;
				counter <= CLKS_PER_BIT;
			end
		end
		else if (counter == 0) begin
			if (state == 10)
				state <= 0;
			else begin
				state <= state + 1;
				if (state == 10)
					counter <= CLKS_PER_BIT - 1;
				else
					counter <= CLKS_PER_BIT;
			end
		end
		else
			counter <= counter - 1;
	end
	always @(*)
		if (state == 0)
			o_out = 1;
		else if (state == 1)
			o_out = 0;
		else if (state == 10)
			o_out = 1;
		else
			o_out = data_send[state - 2];
endmodule
module i2c_master (
	clk,
	rst,
	cmd_address,
	cmd_start,
	cmd_read,
	cmd_write,
	cmd_write_multiple,
	cmd_stop,
	cmd_valid,
	cmd_ready,
	data_in,
	data_in_valid,
	data_in_ready,
	data_in_last,
	data_out,
	data_out_valid,
	data_out_ready,
	data_out_last,
	scl_i,
	scl_o,
	scl_t,
	sda_i,
	sda_o,
	sda_t,
	busy,
	bus_control,
	bus_active,
	missed_ack,
	prescale,
	stop_on_idle
);
	input wire clk;
	input wire rst;
	input wire [6:0] cmd_address;
	input wire cmd_start;
	input wire cmd_read;
	input wire cmd_write;
	input wire cmd_write_multiple;
	input wire cmd_stop;
	input wire cmd_valid;
	output wire cmd_ready;
	input wire [7:0] data_in;
	input wire data_in_valid;
	output wire data_in_ready;
	input wire data_in_last;
	output wire [7:0] data_out;
	output wire data_out_valid;
	input wire data_out_ready;
	output wire data_out_last;
	input wire scl_i;
	output wire scl_o;
	output wire scl_t;
	input wire sda_i;
	output wire sda_o;
	output wire sda_t;
	output wire busy;
	output wire bus_control;
	output wire bus_active;
	output wire missed_ack;
	input wire [15:0] prescale;
	input wire stop_on_idle;
	localparam [4:0] STATE_IDLE = 4'd0;
	localparam [4:0] STATE_ACTIVE_WRITE = 4'd1;
	localparam [4:0] STATE_ACTIVE_READ = 4'd2;
	localparam [4:0] STATE_START_WAIT = 4'd3;
	localparam [4:0] STATE_START = 4'd4;
	localparam [4:0] STATE_ADDRESS_1 = 4'd5;
	localparam [4:0] STATE_ADDRESS_2 = 4'd6;
	localparam [4:0] STATE_WRITE_1 = 4'd7;
	localparam [4:0] STATE_WRITE_2 = 4'd8;
	localparam [4:0] STATE_WRITE_3 = 4'd9;
	localparam [4:0] STATE_READ = 4'd10;
	localparam [4:0] STATE_STOP = 4'd11;
	reg [4:0] state_reg = STATE_IDLE;
	reg [4:0] state_next;
	localparam [4:0] PHY_STATE_IDLE = 5'd0;
	localparam [4:0] PHY_STATE_ACTIVE = 5'd1;
	localparam [4:0] PHY_STATE_REPEATED_START_1 = 5'd2;
	localparam [4:0] PHY_STATE_REPEATED_START_2 = 5'd3;
	localparam [4:0] PHY_STATE_START_1 = 5'd4;
	localparam [4:0] PHY_STATE_START_2 = 5'd5;
	localparam [4:0] PHY_STATE_WRITE_BIT_1 = 5'd6;
	localparam [4:0] PHY_STATE_WRITE_BIT_2 = 5'd7;
	localparam [4:0] PHY_STATE_WRITE_BIT_3 = 5'd8;
	localparam [4:0] PHY_STATE_READ_BIT_1 = 5'd9;
	localparam [4:0] PHY_STATE_READ_BIT_2 = 5'd10;
	localparam [4:0] PHY_STATE_READ_BIT_3 = 5'd11;
	localparam [4:0] PHY_STATE_READ_BIT_4 = 5'd12;
	localparam [4:0] PHY_STATE_STOP_1 = 5'd13;
	localparam [4:0] PHY_STATE_STOP_2 = 5'd14;
	localparam [4:0] PHY_STATE_STOP_3 = 5'd15;
	reg [4:0] phy_state_reg = STATE_IDLE;
	reg [4:0] phy_state_next;
	reg phy_start_bit;
	reg phy_stop_bit;
	reg phy_write_bit;
	reg phy_read_bit;
	reg phy_release_bus;
	reg phy_tx_data;
	reg phy_rx_data_reg = 1'b0;
	reg phy_rx_data_next;
	reg [6:0] addr_reg = 7'd0;
	reg [6:0] addr_next;
	reg [7:0] data_reg = 8'd0;
	reg [7:0] data_next;
	reg last_reg = 1'b0;
	reg last_next;
	reg mode_read_reg = 1'b0;
	reg mode_read_next;
	reg mode_write_multiple_reg = 1'b0;
	reg mode_write_multiple_next;
	reg mode_stop_reg = 1'b0;
	reg mode_stop_next;
	reg [16:0] delay_reg = 16'd0;
	reg [16:0] delay_next;
	reg delay_scl_reg = 1'b0;
	reg delay_scl_next;
	reg delay_sda_reg = 1'b0;
	reg delay_sda_next;
	reg [3:0] bit_count_reg = 4'd0;
	reg [3:0] bit_count_next;
	reg cmd_ready_reg = 1'b0;
	reg cmd_ready_next;
	reg data_in_ready_reg = 1'b0;
	reg data_in_ready_next;
	reg [7:0] data_out_reg = 8'd0;
	reg [7:0] data_out_next;
	reg data_out_valid_reg = 1'b0;
	reg data_out_valid_next;
	reg data_out_last_reg = 1'b0;
	reg data_out_last_next;
	reg scl_i_reg = 1'b1;
	reg sda_i_reg = 1'b1;
	reg scl_o_reg = 1'b1;
	reg scl_o_next;
	reg sda_o_reg = 1'b1;
	reg sda_o_next;
	reg last_scl_i_reg = 1'b1;
	reg last_sda_i_reg = 1'b1;
	reg busy_reg = 1'b0;
	reg bus_active_reg = 1'b0;
	reg bus_control_reg = 1'b0;
	reg bus_control_next;
	reg missed_ack_reg = 1'b0;
	reg missed_ack_next;
	assign cmd_ready = cmd_ready_reg;
	assign data_in_ready = data_in_ready_reg;
	assign data_out = data_out_reg;
	assign data_out_valid = data_out_valid_reg;
	assign data_out_last = data_out_last_reg;
	assign scl_o = scl_o_reg;
	assign scl_t = scl_o_reg;
	assign sda_o = sda_o_reg;
	assign sda_t = sda_o_reg;
	assign busy = busy_reg;
	assign bus_active = bus_active_reg;
	assign bus_control = bus_control_reg;
	assign missed_ack = missed_ack_reg;
	wire scl_posedge = scl_i_reg & ~last_scl_i_reg;
	wire scl_negedge = ~scl_i_reg & last_scl_i_reg;
	wire sda_posedge = sda_i_reg & ~last_sda_i_reg;
	wire sda_negedge = ~sda_i_reg & last_sda_i_reg;
	wire start_bit = sda_negedge & scl_i_reg;
	wire stop_bit = sda_posedge & scl_i_reg;
	always @(*) begin
		state_next = STATE_IDLE;
		phy_start_bit = 1'b0;
		phy_stop_bit = 1'b0;
		phy_write_bit = 1'b0;
		phy_read_bit = 1'b0;
		phy_tx_data = 1'b0;
		phy_release_bus = 1'b0;
		addr_next = addr_reg;
		data_next = data_reg;
		last_next = last_reg;
		mode_read_next = mode_read_reg;
		mode_write_multiple_next = mode_write_multiple_reg;
		mode_stop_next = mode_stop_reg;
		bit_count_next = bit_count_reg;
		cmd_ready_next = 1'b0;
		data_in_ready_next = 1'b0;
		data_out_next = data_out_reg;
		data_out_valid_next = data_out_valid_reg & ~data_out_ready;
		data_out_last_next = data_out_last_reg;
		missed_ack_next = 1'b0;
		if ((phy_state_reg != PHY_STATE_IDLE) && (phy_state_reg != PHY_STATE_ACTIVE))
			state_next = state_reg;
		else
			case (state_reg)
				STATE_IDLE: begin
					cmd_ready_next = 1'b1;
					if (cmd_ready & cmd_valid) begin
						if (cmd_read ^ (cmd_write | cmd_write_multiple)) begin
							addr_next = cmd_address;
							mode_read_next = cmd_read;
							mode_write_multiple_next = cmd_write_multiple;
							mode_stop_next = cmd_stop;
							cmd_ready_next = 1'b0;
							if (bus_active)
								state_next = STATE_START_WAIT;
							else begin
								phy_start_bit = 1'b1;
								bit_count_next = 4'd8;
								state_next = STATE_ADDRESS_1;
							end
						end
						else
							state_next = STATE_IDLE;
					end
					else
						state_next = STATE_IDLE;
				end
				STATE_ACTIVE_WRITE: begin
					cmd_ready_next = 1'b1;
					if (cmd_ready & cmd_valid) begin
						if (cmd_read ^ (cmd_write | cmd_write_multiple)) begin
							addr_next = cmd_address;
							mode_read_next = cmd_read;
							mode_write_multiple_next = cmd_write_multiple;
							mode_stop_next = cmd_stop;
							cmd_ready_next = 1'b0;
							if ((cmd_start || (cmd_address != addr_reg)) || cmd_read) begin
								phy_start_bit = 1'b1;
								bit_count_next = 4'd8;
								state_next = STATE_ADDRESS_1;
							end
							else begin
								data_in_ready_next = 1'b1;
								state_next = STATE_WRITE_1;
							end
						end
						else if (cmd_stop && !((cmd_read || cmd_write) || cmd_write_multiple)) begin
							phy_stop_bit = 1'b1;
							state_next = STATE_IDLE;
						end
						else
							state_next = STATE_ACTIVE_WRITE;
					end
					else if ((stop_on_idle & cmd_ready) & ~cmd_valid) begin
						phy_stop_bit = 1'b1;
						state_next = STATE_IDLE;
					end
					else
						state_next = STATE_ACTIVE_WRITE;
				end
				STATE_ACTIVE_READ: begin
					cmd_ready_next = ~data_out_valid;
					if (cmd_ready & cmd_valid) begin
						if (cmd_read ^ (cmd_write | cmd_write_multiple)) begin
							addr_next = cmd_address;
							mode_read_next = cmd_read;
							mode_write_multiple_next = cmd_write_multiple;
							mode_stop_next = cmd_stop;
							cmd_ready_next = 1'b0;
							if ((cmd_start || (cmd_address != addr_reg)) || cmd_write) begin
								phy_write_bit = 1'b1;
								phy_tx_data = 1'b1;
								state_next = STATE_START;
							end
							else begin
								phy_write_bit = 1'b1;
								phy_tx_data = 1'b0;
								bit_count_next = 4'd8;
								data_next = 8'd0;
								state_next = STATE_READ;
							end
						end
						else if (cmd_stop && !((cmd_read || cmd_write) || cmd_write_multiple)) begin
							phy_write_bit = 1'b1;
							phy_tx_data = 1'b1;
							state_next = STATE_STOP;
						end
						else
							state_next = STATE_ACTIVE_READ;
					end
					else if ((stop_on_idle & cmd_ready) & ~cmd_valid) begin
						phy_write_bit = 1'b1;
						phy_tx_data = 1'b1;
						state_next = STATE_STOP;
					end
					else
						state_next = STATE_ACTIVE_READ;
				end
				STATE_START_WAIT:
					if (bus_active)
						state_next = STATE_START_WAIT;
					else begin
						phy_start_bit = 1'b1;
						bit_count_next = 4'd8;
						state_next = STATE_ADDRESS_1;
					end
				STATE_START: begin
					phy_start_bit = 1'b1;
					bit_count_next = 4'd8;
					state_next = STATE_ADDRESS_1;
				end
				STATE_ADDRESS_1: begin
					bit_count_next = bit_count_reg - 1;
					if (bit_count_reg > 1) begin
						phy_write_bit = 1'b1;
						phy_tx_data = addr_reg[bit_count_reg - 2];
						state_next = STATE_ADDRESS_1;
					end
					else if (bit_count_reg > 0) begin
						phy_write_bit = 1'b1;
						phy_tx_data = mode_read_reg;
						state_next = STATE_ADDRESS_1;
					end
					else begin
						phy_read_bit = 1'b1;
						state_next = STATE_ADDRESS_2;
					end
				end
				STATE_ADDRESS_2: begin
					missed_ack_next = phy_rx_data_reg;
					if (mode_read_reg) begin
						bit_count_next = 4'd8;
						data_next = 1'b0;
						state_next = STATE_READ;
					end
					else begin
						data_in_ready_next = 1'b1;
						state_next = STATE_WRITE_1;
					end
				end
				STATE_WRITE_1: begin
					data_in_ready_next = 1'b1;
					if (data_in_ready & data_in_valid) begin
						data_next = data_in;
						last_next = data_in_last;
						bit_count_next = 4'd8;
						data_in_ready_next = 1'b0;
						state_next = STATE_WRITE_2;
					end
					else
						state_next = STATE_WRITE_1;
				end
				STATE_WRITE_2: begin
					bit_count_next = bit_count_reg - 1;
					if (bit_count_reg > 0) begin
						phy_write_bit = 1'b1;
						phy_tx_data = data_reg[bit_count_reg - 1];
						state_next = STATE_WRITE_2;
					end
					else begin
						phy_read_bit = 1'b1;
						state_next = STATE_WRITE_3;
					end
				end
				STATE_WRITE_3: begin
					missed_ack_next = phy_rx_data_reg;
					if (mode_write_multiple_reg && !last_reg)
						state_next = STATE_WRITE_1;
					else if (mode_stop_reg) begin
						phy_stop_bit = 1'b1;
						state_next = STATE_IDLE;
					end
					else
						state_next = STATE_ACTIVE_WRITE;
				end
				STATE_READ: begin
					bit_count_next = bit_count_reg - 1;
					data_next = {data_reg[6:0], phy_rx_data_reg};
					if (bit_count_reg > 0) begin
						phy_read_bit = 1'b1;
						state_next = STATE_READ;
					end
					else begin
						data_out_next = data_next;
						data_out_valid_next = 1'b1;
						data_out_last_next = 1'b0;
						if (mode_stop_reg) begin
							data_out_last_next = 1'b1;
							phy_write_bit = 1'b1;
							phy_tx_data = 1'b1;
							state_next = STATE_STOP;
						end
						else
							state_next = STATE_ACTIVE_READ;
					end
				end
				STATE_STOP: begin
					phy_stop_bit = 1'b1;
					state_next = STATE_IDLE;
				end
			endcase
	end
	always @(*) begin
		phy_state_next = PHY_STATE_IDLE;
		phy_rx_data_next = phy_rx_data_reg;
		delay_next = delay_reg;
		delay_scl_next = delay_scl_reg;
		delay_sda_next = delay_sda_reg;
		scl_o_next = scl_o_reg;
		sda_o_next = sda_o_reg;
		bus_control_next = bus_control_reg;
		if (phy_release_bus) begin
			sda_o_next = 1'b1;
			scl_o_next = 1'b1;
			delay_scl_next = 1'b0;
			delay_sda_next = 1'b0;
			delay_next = 1'b0;
			phy_state_next = PHY_STATE_IDLE;
		end
		else if (delay_scl_reg) begin
			delay_scl_next = scl_o_reg & ~scl_i_reg;
			phy_state_next = phy_state_reg;
		end
		else if (delay_sda_reg) begin
			delay_sda_next = sda_o_reg & ~sda_i_reg;
			phy_state_next = phy_state_reg;
		end
		else if (delay_reg > 0) begin
			delay_next = delay_reg - 1;
			phy_state_next = phy_state_reg;
		end
		else
			case (phy_state_reg)
				PHY_STATE_IDLE: begin
					sda_o_next = 1'b1;
					scl_o_next = 1'b1;
					if (phy_start_bit) begin
						sda_o_next = 1'b0;
						delay_next = prescale;
						phy_state_next = PHY_STATE_START_1;
					end
					else
						phy_state_next = PHY_STATE_IDLE;
				end
				PHY_STATE_ACTIVE:
					if (phy_start_bit) begin
						sda_o_next = 1'b1;
						delay_next = prescale;
						phy_state_next = PHY_STATE_REPEATED_START_1;
					end
					else if (phy_write_bit) begin
						sda_o_next = phy_tx_data;
						delay_next = prescale;
						phy_state_next = PHY_STATE_WRITE_BIT_1;
					end
					else if (phy_read_bit) begin
						sda_o_next = 1'b1;
						delay_next = prescale;
						phy_state_next = PHY_STATE_READ_BIT_1;
					end
					else if (phy_stop_bit) begin
						sda_o_next = 1'b0;
						delay_next = prescale;
						phy_state_next = PHY_STATE_STOP_1;
					end
					else
						phy_state_next = PHY_STATE_ACTIVE;
				PHY_STATE_REPEATED_START_1: begin
					scl_o_next = 1'b1;
					delay_scl_next = 1'b1;
					delay_next = prescale;
					phy_state_next = PHY_STATE_REPEATED_START_2;
				end
				PHY_STATE_REPEATED_START_2: begin
					sda_o_next = 1'b0;
					delay_next = prescale;
					phy_state_next = PHY_STATE_START_1;
				end
				PHY_STATE_START_1: begin
					scl_o_next = 1'b0;
					delay_next = prescale;
					phy_state_next = PHY_STATE_START_2;
				end
				PHY_STATE_START_2: begin
					bus_control_next = 1'b1;
					phy_state_next = PHY_STATE_ACTIVE;
				end
				PHY_STATE_WRITE_BIT_1: begin
					scl_o_next = 1'b1;
					delay_scl_next = 1'b1;
					delay_next = prescale << 1;
					phy_state_next = PHY_STATE_WRITE_BIT_2;
				end
				PHY_STATE_WRITE_BIT_2: begin
					scl_o_next = 1'b0;
					delay_next = prescale;
					phy_state_next = PHY_STATE_WRITE_BIT_3;
				end
				PHY_STATE_WRITE_BIT_3: phy_state_next = PHY_STATE_ACTIVE;
				PHY_STATE_READ_BIT_1: begin
					scl_o_next = 1'b1;
					delay_scl_next = 1'b1;
					delay_next = prescale;
					phy_state_next = PHY_STATE_READ_BIT_2;
				end
				PHY_STATE_READ_BIT_2: begin
					phy_rx_data_next = sda_i_reg;
					delay_next = prescale;
					phy_state_next = PHY_STATE_READ_BIT_3;
				end
				PHY_STATE_READ_BIT_3: begin
					scl_o_next = 1'b0;
					delay_next = prescale;
					phy_state_next = PHY_STATE_READ_BIT_4;
				end
				PHY_STATE_READ_BIT_4: phy_state_next = PHY_STATE_ACTIVE;
				PHY_STATE_STOP_1: begin
					scl_o_next = 1'b1;
					delay_scl_next = 1'b1;
					delay_next = prescale;
					phy_state_next = PHY_STATE_STOP_2;
				end
				PHY_STATE_STOP_2: begin
					sda_o_next = 1'b1;
					delay_next = prescale;
					phy_state_next = PHY_STATE_STOP_3;
				end
				PHY_STATE_STOP_3: begin
					bus_control_next = 1'b0;
					phy_state_next = PHY_STATE_IDLE;
				end
			endcase
	end
	always @(posedge clk) begin
		if (rst) begin
			state_reg <= STATE_IDLE;
			phy_state_reg <= PHY_STATE_IDLE;
			delay_reg <= 16'd0;
			delay_scl_reg <= 1'b0;
			delay_sda_reg <= 1'b0;
			cmd_ready_reg <= 1'b0;
			data_in_ready_reg <= 1'b0;
			data_out_valid_reg <= 1'b0;
			scl_o_reg <= 1'b1;
			sda_o_reg <= 1'b1;
			busy_reg <= 1'b0;
			bus_active_reg <= 1'b0;
			bus_control_reg <= 1'b0;
			missed_ack_reg <= 1'b0;
		end
		else begin
			state_reg <= state_next;
			phy_state_reg <= phy_state_next;
			delay_reg <= delay_next;
			delay_scl_reg <= delay_scl_next;
			delay_sda_reg <= delay_sda_next;
			cmd_ready_reg <= cmd_ready_next;
			data_in_ready_reg <= data_in_ready_next;
			data_out_valid_reg <= data_out_valid_next;
			scl_o_reg <= scl_o_next;
			sda_o_reg <= sda_o_next;
			busy_reg <= !(((state_reg == STATE_IDLE) || (state_reg == STATE_ACTIVE_WRITE)) || (state_reg == STATE_ACTIVE_READ)) || !((phy_state_reg == PHY_STATE_IDLE) || (phy_state_reg == PHY_STATE_ACTIVE));
			if (start_bit)
				bus_active_reg <= 1'b1;
			else if (stop_bit)
				bus_active_reg <= 1'b0;
			else
				bus_active_reg <= bus_active_reg;
			bus_control_reg <= bus_control_next;
			missed_ack_reg <= missed_ack_next;
		end
		phy_rx_data_reg <= phy_rx_data_next;
		addr_reg <= addr_next;
		data_reg <= data_next;
		last_reg <= last_next;
		mode_read_reg <= mode_read_next;
		mode_write_multiple_reg <= mode_write_multiple_next;
		mode_stop_reg <= mode_stop_next;
		bit_count_reg <= bit_count_next;
		data_out_reg <= data_out_next;
		data_out_last_reg <= data_out_last_next;
		scl_i_reg <= scl_i;
		sda_i_reg <= sda_i;
		last_scl_i_reg <= scl_i_reg;
		last_sda_i_reg <= sda_i_reg;
	end
endmodule
module axis_fifo (
	clk,
	rst,
	s_axis_tdata,
	s_axis_tkeep,
	s_axis_tvalid,
	s_axis_tready,
	s_axis_tlast,
	s_axis_tid,
	s_axis_tdest,
	s_axis_tuser,
	m_axis_tdata,
	m_axis_tkeep,
	m_axis_tvalid,
	m_axis_tready,
	m_axis_tlast,
	m_axis_tid,
	m_axis_tdest,
	m_axis_tuser,
	status_overflow,
	status_bad_frame,
	status_good_frame
);
	parameter ADDR_WIDTH = 12;
	parameter DATA_WIDTH = 8;
	parameter KEEP_ENABLE = DATA_WIDTH > 8;
	parameter KEEP_WIDTH = DATA_WIDTH / 8;
	parameter LAST_ENABLE = 1;
	parameter ID_ENABLE = 0;
	parameter ID_WIDTH = 8;
	parameter DEST_ENABLE = 0;
	parameter DEST_WIDTH = 8;
	parameter USER_ENABLE = 1;
	parameter USER_WIDTH = 1;
	parameter PIPELINE_OUTPUT = 1;
	parameter FRAME_FIFO = 0;
	parameter USER_BAD_FRAME_VALUE = 1'b1;
	parameter USER_BAD_FRAME_MASK = 1'b1;
	parameter DROP_BAD_FRAME = 0;
	parameter DROP_WHEN_FULL = 0;
	input wire clk;
	input wire rst;
	input wire [DATA_WIDTH - 1:0] s_axis_tdata;
	input wire [KEEP_WIDTH - 1:0] s_axis_tkeep;
	input wire s_axis_tvalid;
	output wire s_axis_tready;
	input wire s_axis_tlast;
	input wire [ID_WIDTH - 1:0] s_axis_tid;
	input wire [DEST_WIDTH - 1:0] s_axis_tdest;
	input wire [USER_WIDTH - 1:0] s_axis_tuser;
	output wire [DATA_WIDTH - 1:0] m_axis_tdata;
	output wire [KEEP_WIDTH - 1:0] m_axis_tkeep;
	output wire m_axis_tvalid;
	input wire m_axis_tready;
	output wire m_axis_tlast;
	output wire [ID_WIDTH - 1:0] m_axis_tid;
	output wire [DEST_WIDTH - 1:0] m_axis_tdest;
	output wire [USER_WIDTH - 1:0] m_axis_tuser;
	output wire status_overflow;
	output wire status_bad_frame;
	output wire status_good_frame;
	initial begin
		if (FRAME_FIFO && !LAST_ENABLE) begin
			$error("Error: FRAME_FIFO set requires LAST_ENABLE set");
			$finish;
		end
		if (DROP_BAD_FRAME && !FRAME_FIFO) begin
			$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set");
			$finish;
		end
		if (DROP_WHEN_FULL && !FRAME_FIFO) begin
			$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set");
			$finish;
		end
		if (DROP_BAD_FRAME && ((USER_BAD_FRAME_MASK & {USER_WIDTH {1'b1}}) == 0)) begin
			$error("Error: Invalid USER_BAD_FRAME_MASK value");
			$finish;
		end
	end
	localparam KEEP_OFFSET = DATA_WIDTH;
	localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
	localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
	localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
	localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
	localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
	reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH + 1 {1'b0}};
	reg [ADDR_WIDTH:0] wr_ptr_next;
	reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH + 1 {1'b0}};
	reg [ADDR_WIDTH:0] wr_ptr_cur_next;
	reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH + 1 {1'b0}};
	reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH + 1 {1'b0}};
	reg [ADDR_WIDTH:0] rd_ptr_next;
	reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH + 1 {1'b0}};
	reg [WIDTH - 1:0] mem [(2 ** ADDR_WIDTH) - 1:0];
	reg [WIDTH - 1:0] mem_read_data_reg;
	reg mem_read_data_valid_reg = 1'b0;
	reg mem_read_data_valid_next;
	wire [WIDTH - 1:0] s_axis;
	reg [WIDTH - 1:0] m_axis_reg;
	reg m_axis_tvalid_reg = 1'b0;
	reg m_axis_tvalid_next;
	wire full = (wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) && (wr_ptr_reg[ADDR_WIDTH - 1:0] == rd_ptr_reg[ADDR_WIDTH - 1:0]);
	wire full_cur = (wr_ptr_cur_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) && (wr_ptr_cur_reg[ADDR_WIDTH - 1:0] == rd_ptr_reg[ADDR_WIDTH - 1:0]);
	wire empty = wr_ptr_reg == rd_ptr_reg;
	wire full_wr = (wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) && (wr_ptr_reg[ADDR_WIDTH - 1:0] == wr_ptr_cur_reg[ADDR_WIDTH - 1:0]);
	reg write;
	reg read;
	reg store_output;
	reg drop_frame_reg = 1'b0;
	reg drop_frame_next;
	reg overflow_reg = 1'b0;
	reg overflow_next;
	reg bad_frame_reg = 1'b0;
	reg bad_frame_next;
	reg good_frame_reg = 1'b0;
	reg good_frame_next;
	assign s_axis_tready = (FRAME_FIFO ? (!full_cur || full_wr) || DROP_WHEN_FULL : !full);
	generate
		assign s_axis[DATA_WIDTH - 1:0] = s_axis_tdata;
		if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET+:KEEP_WIDTH] = s_axis_tkeep;
		if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
		if (ID_ENABLE) assign s_axis[ID_OFFSET+:ID_WIDTH] = s_axis_tid;
		if (DEST_ENABLE) assign s_axis[DEST_OFFSET+:DEST_WIDTH] = s_axis_tdest;
		if (USER_ENABLE) assign s_axis[USER_OFFSET+:USER_WIDTH] = s_axis_tuser;
	endgenerate
	assign m_axis_tvalid = m_axis_tvalid_reg;
	assign m_axis_tdata = m_axis_reg[DATA_WIDTH - 1:0];
	assign m_axis_tkeep = (KEEP_ENABLE ? m_axis_reg[KEEP_OFFSET+:KEEP_WIDTH] : {KEEP_WIDTH {1'b1}});
	assign m_axis_tlast = (LAST_ENABLE ? m_axis_reg[LAST_OFFSET] : 1'b1);
	assign m_axis_tid = (ID_ENABLE ? m_axis_reg[ID_OFFSET+:ID_WIDTH] : {ID_WIDTH {1'b0}});
	assign m_axis_tdest = (DEST_ENABLE ? m_axis_reg[DEST_OFFSET+:DEST_WIDTH] : {DEST_WIDTH {1'b0}});
	assign m_axis_tuser = (USER_ENABLE ? m_axis_reg[USER_OFFSET+:USER_WIDTH] : {USER_WIDTH {1'b0}});
	assign status_overflow = overflow_reg;
	assign status_bad_frame = bad_frame_reg;
	assign status_good_frame = good_frame_reg;
	always @(*) begin
		write = 1'b0;
		drop_frame_next = 1'b0;
		overflow_next = 1'b0;
		bad_frame_next = 1'b0;
		good_frame_next = 1'b0;
		wr_ptr_next = wr_ptr_reg;
		wr_ptr_cur_next = wr_ptr_cur_reg;
		if (s_axis_tready && s_axis_tvalid)
			if (!FRAME_FIFO) begin
				write = 1'b1;
				wr_ptr_next = wr_ptr_reg + 1;
			end
			else if ((full_cur || full_wr) || drop_frame_reg) begin
				drop_frame_next = 1'b1;
				if (s_axis_tlast) begin
					wr_ptr_cur_next = wr_ptr_reg;
					drop_frame_next = 1'b0;
					overflow_next = 1'b1;
				end
			end
			else begin
				write = 1'b1;
				wr_ptr_cur_next = wr_ptr_cur_reg + 1;
				if (s_axis_tlast)
					if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & (s_axis_tuser == USER_BAD_FRAME_VALUE))) begin
						wr_ptr_cur_next = wr_ptr_reg;
						bad_frame_next = 1'b1;
					end
					else begin
						wr_ptr_next = wr_ptr_cur_reg + 1;
						good_frame_next = 1'b1;
					end
			end
	end
	always @(posedge clk) begin
		if (rst) begin
			wr_ptr_reg <= {ADDR_WIDTH + 1 {1'b0}};
			wr_ptr_cur_reg <= {ADDR_WIDTH + 1 {1'b0}};
			drop_frame_reg <= 1'b0;
			overflow_reg <= 1'b0;
			bad_frame_reg <= 1'b0;
			good_frame_reg <= 1'b0;
		end
		else begin
			wr_ptr_reg <= wr_ptr_next;
			wr_ptr_cur_reg <= wr_ptr_cur_next;
			drop_frame_reg <= drop_frame_next;
			overflow_reg <= overflow_next;
			bad_frame_reg <= bad_frame_next;
			good_frame_reg <= good_frame_next;
		end
		if (FRAME_FIFO)
			wr_addr_reg <= wr_ptr_cur_next;
		else
			wr_addr_reg <= wr_ptr_next;
		if (write)
			mem[wr_addr_reg[ADDR_WIDTH - 1:0]] <= s_axis;
	end
	always @(*) begin
		read = 1'b0;
		rd_ptr_next = rd_ptr_reg;
		mem_read_data_valid_next = mem_read_data_valid_reg;
		if (store_output || !mem_read_data_valid_reg)
			if (!empty) begin
				read = 1'b1;
				mem_read_data_valid_next = 1'b1;
				rd_ptr_next = rd_ptr_reg + 1;
			end
			else
				mem_read_data_valid_next = 1'b0;
	end
	always @(posedge clk) begin
		if (rst) begin
			rd_ptr_reg <= {ADDR_WIDTH + 1 {1'b0}};
			mem_read_data_valid_reg <= 1'b0;
		end
		else begin
			rd_ptr_reg <= rd_ptr_next;
			mem_read_data_valid_reg <= mem_read_data_valid_next;
		end
		rd_addr_reg <= rd_ptr_next;
		if (read)
			mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH - 1:0]];
	end
	always @(*) begin
		store_output = 1'b0;
		m_axis_tvalid_next = m_axis_tvalid_reg;
		if (m_axis_tready || !m_axis_tvalid) begin
			store_output = 1'b1;
			m_axis_tvalid_next = mem_read_data_valid_reg;
		end
	end
	always @(posedge clk) begin
		if (rst)
			m_axis_tvalid_reg <= 1'b0;
		else
			m_axis_tvalid_reg <= m_axis_tvalid_next;
		if (store_output)
			m_axis_reg <= mem_read_data_reg;
	end
endmodule
module i2c_master_wbs_16 (
	clk,
	rst,
	wbs_adr_i,
	wbs_dat_i,
	wbs_dat_o,
	wbs_we_i,
	wbs_sel_i,
	wbs_stb_i,
	wbs_ack_o,
	wbs_cyc_i,
	i2c_scl_i,
	i2c_scl_o,
	i2c_scl_t,
	i2c_sda_i,
	i2c_sda_o,
	i2c_sda_t
);
	parameter DEFAULT_PRESCALE = 1;
	parameter FIXED_PRESCALE = 0;
	parameter CMD_FIFO = 1;
	parameter CMD_FIFO_ADDR_WIDTH = 5;
	parameter WRITE_FIFO = 1;
	parameter WRITE_FIFO_ADDR_WIDTH = 5;
	parameter READ_FIFO = 1;
	parameter READ_FIFO_ADDR_WIDTH = 5;
	input wire clk;
	input wire rst;
	input wire [2:0] wbs_adr_i;
	input wire [15:0] wbs_dat_i;
	output wire [15:0] wbs_dat_o;
	input wire wbs_we_i;
	input wire [1:0] wbs_sel_i;
	input wire wbs_stb_i;
	output wire wbs_ack_o;
	input wire wbs_cyc_i;
	input wire i2c_scl_i;
	output wire i2c_scl_o;
	output wire i2c_scl_t;
	input wire i2c_sda_i;
	output wire i2c_sda_o;
	output wire i2c_sda_t;
	reg [15:0] wbs_dat_o_reg = 16'd0;
	reg [15:0] wbs_dat_o_next;
	reg wbs_ack_o_reg = 1'b0;
	reg wbs_ack_o_next;
	reg [6:0] cmd_address_reg = 7'd0;
	reg [6:0] cmd_address_next;
	reg cmd_start_reg = 1'b0;
	reg cmd_start_next;
	reg cmd_read_reg = 1'b0;
	reg cmd_read_next;
	reg cmd_write_reg = 1'b0;
	reg cmd_write_next;
	reg cmd_write_multiple_reg = 1'b0;
	reg cmd_write_multiple_next;
	reg cmd_stop_reg = 1'b0;
	reg cmd_stop_next;
	reg cmd_valid_reg = 1'b0;
	reg cmd_valid_next;
	wire cmd_ready;
	reg [7:0] data_in_reg = 8'd0;
	reg [7:0] data_in_next;
	reg data_in_valid_reg = 1'b0;
	reg data_in_valid_next;
	wire data_in_ready;
	reg data_in_last_reg = 1'b0;
	reg data_in_last_next;
	wire [7:0] data_out;
	wire data_out_valid;
	reg data_out_ready_reg = 1'b0;
	reg data_out_ready_next;
	wire data_out_last;
	reg [15:0] prescale_reg = DEFAULT_PRESCALE;
	reg [15:0] prescale_next;
	reg missed_ack_reg = 1'b0;
	reg missed_ack_next;
	assign wbs_dat_o = wbs_dat_o_reg;
	assign wbs_ack_o = wbs_ack_o_reg;
	wire [6:0] cmd_address_int;
	wire cmd_start_int;
	wire cmd_read_int;
	wire cmd_write_int;
	wire cmd_write_multiple_int;
	wire cmd_stop_int;
	wire cmd_valid_int;
	wire cmd_ready_int;
	wire [7:0] data_in_int;
	wire data_in_valid_int;
	wire data_in_ready_int;
	wire data_in_last_int;
	wire [7:0] data_out_int;
	wire data_out_valid_int;
	wire data_out_ready_int;
	wire data_out_last_int;
	wire busy_int;
	wire bus_control_int;
	wire bus_active_int;
	wire missed_ack_int;
	wire cmd_fifo_empty = ~cmd_valid_int;
	wire cmd_fifo_full = ~cmd_ready;
	wire write_fifo_empty = ~data_in_valid_int;
	wire write_fifo_full = ~data_in_ready;
	wire read_fifo_empty = ~data_out_valid;
	wire read_fifo_full = ~data_out_ready_int;
	reg cmd_fifo_overflow_reg = 1'b0;
	reg cmd_fifo_overflow_next;
	reg write_fifo_overflow_reg = 1'b0;
	reg write_fifo_overflow_next;
	generate
		if (CMD_FIFO) axis_fifo #(
			.ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
			.DATA_WIDTH(12),
			.KEEP_ENABLE(0),
			.LAST_ENABLE(0),
			.ID_ENABLE(0),
			.DEST_ENABLE(0),
			.USER_ENABLE(0),
			.FRAME_FIFO(0)
		) cmd_fifo_inst(
			.clk(clk),
			.rst(rst),
			.s_axis_tdata({cmd_address_reg, cmd_start_reg, cmd_read_reg, cmd_write_reg, cmd_write_multiple_reg, cmd_stop_reg}),
			.s_axis_tkeep(0),
			.s_axis_tvalid(cmd_valid_reg),
			.s_axis_tready(cmd_ready),
			.s_axis_tlast(1'b0),
			.s_axis_tid(0),
			.s_axis_tdest(0),
			.s_axis_tuser(1'b0),
			.m_axis_tdata({cmd_address_int, cmd_start_int, cmd_read_int, cmd_write_int, cmd_write_multiple_int, cmd_stop_int}),
			.m_axis_tkeep(),
			.m_axis_tvalid(cmd_valid_int),
			.m_axis_tready(cmd_ready_int),
			.m_axis_tlast(),
			.m_axis_tid(),
			.m_axis_tdest(),
			.m_axis_tuser()
		);
		else begin
			assign cmd_address_int = cmd_address_reg;
			assign cmd_start_int = cmd_start_reg;
			assign cmd_read_int = cmd_read_reg;
			assign cmd_write_int = cmd_write_reg;
			assign cmd_write_multiple_int = cmd_write_multiple_reg;
			assign cmd_stop_int = cmd_stop_reg;
			assign cmd_valid_int = cmd_valid_reg;
			assign cmd_ready = cmd_ready_int;
		end
		if (WRITE_FIFO) axis_fifo #(
			.ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
			.DATA_WIDTH(8),
			.KEEP_ENABLE(0),
			.LAST_ENABLE(1),
			.ID_ENABLE(0),
			.DEST_ENABLE(0),
			.USER_ENABLE(0),
			.FRAME_FIFO(0)
		) write_fifo_inst(
			.clk(clk),
			.rst(rst),
			.s_axis_tdata(data_in_reg),
			.s_axis_tkeep(0),
			.s_axis_tvalid(data_in_valid_reg),
			.s_axis_tready(data_in_ready),
			.s_axis_tlast(data_in_last_reg),
			.s_axis_tid(0),
			.s_axis_tdest(0),
			.s_axis_tuser(1'b0),
			.m_axis_tdata(data_in_int),
			.m_axis_tkeep(),
			.m_axis_tvalid(data_in_valid_int),
			.m_axis_tready(data_in_ready_int),
			.m_axis_tlast(data_in_last_int),
			.m_axis_tid(),
			.m_axis_tdest(),
			.m_axis_tuser()
		);
		else begin
			assign data_in_int = data_in_reg;
			assign data_in_valid = data_in_valid_reg;
			assign data_in_ready = data_in_ready_int;
			assign data_in_last = data_in_last_reg;
		end
		if (READ_FIFO) axis_fifo #(
			.ADDR_WIDTH(READ_FIFO_ADDR_WIDTH),
			.DATA_WIDTH(8),
			.KEEP_ENABLE(0),
			.LAST_ENABLE(1),
			.ID_ENABLE(0),
			.DEST_ENABLE(0),
			.USER_ENABLE(0),
			.FRAME_FIFO(0)
		) read_fifo_inst(
			.clk(clk),
			.rst(rst),
			.s_axis_tdata(data_out_int),
			.s_axis_tkeep(0),
			.s_axis_tvalid(data_out_valid_int),
			.s_axis_tready(data_out_ready_int),
			.s_axis_tlast(data_out_last_int),
			.s_axis_tid(0),
			.s_axis_tdest(0),
			.s_axis_tuser(0),
			.m_axis_tdata(data_out),
			.m_axis_tkeep(),
			.m_axis_tvalid(data_out_valid),
			.m_axis_tready(data_out_ready_reg),
			.m_axis_tlast(data_out_last),
			.m_axis_tid(),
			.m_axis_tdest(),
			.m_axis_tuser()
		);
		else begin
			assign data_out = data_out_int;
			assign data_out_valid = data_out_valid_int;
			assign data_out_ready_int = data_out_ready_reg;
			assign data_out_last = data_out_last_int;
		end
	endgenerate
	always @(*) begin
		wbs_dat_o_next = 8'd0;
		wbs_ack_o_next = 1'b0;
		cmd_address_next = cmd_address_reg;
		cmd_start_next = cmd_start_reg;
		cmd_read_next = cmd_read_reg;
		cmd_write_next = cmd_write_reg;
		cmd_write_multiple_next = cmd_write_multiple_reg;
		cmd_stop_next = cmd_stop_reg;
		cmd_valid_next = cmd_valid_reg & ~cmd_ready;
		data_in_next = data_in_reg;
		data_in_valid_next = data_in_valid_reg & ~data_in_ready;
		data_in_last_next = data_in_last_reg;
		data_out_ready_next = 1'b0;
		prescale_next = prescale_reg;
		missed_ack_next = missed_ack_reg | missed_ack_int;
		cmd_fifo_overflow_next = cmd_fifo_overflow_reg;
		write_fifo_overflow_next = write_fifo_overflow_reg;
		if (wbs_cyc_i & wbs_stb_i)
			if (wbs_we_i) begin
				case (wbs_adr_i)
					3'h0:
						;
					3'h2: begin
						if (wbs_sel_i[0])
							cmd_address_next = wbs_dat_i[6:0];
						if (wbs_sel_i[1]) begin
							cmd_start_next = wbs_dat_i[8];
							cmd_read_next = wbs_dat_i[9];
							cmd_write_next = wbs_dat_i[10];
							cmd_write_multiple_next = wbs_dat_i[11];
							cmd_stop_next = wbs_dat_i[12];
							cmd_valid_next = ~wbs_ack_o_reg & ((((cmd_start_next | cmd_read_next) | cmd_write_next) | cmd_write_multiple_next) | cmd_stop_next);
							cmd_fifo_overflow_next = cmd_fifo_overflow_next | (cmd_valid_next & ~cmd_ready);
						end
					end
					3'h4:
						if (wbs_sel_i[0]) begin
							data_in_next = wbs_dat_i[7:0];
							if (wbs_sel_i[1])
								data_in_last_next = wbs_dat_i[9];
							else
								data_in_last_next = 1'b0;
							data_in_valid_next = ~wbs_ack_o_reg;
							write_fifo_overflow_next = write_fifo_overflow_next | ~data_in_ready;
						end
					3'h6: begin
						if (!FIXED_PRESCALE && wbs_sel_i[0])
							prescale_next[7:0] = wbs_dat_i[7:0];
						if (!FIXED_PRESCALE && wbs_sel_i[1])
							prescale_next[15:0] = wbs_dat_i[15:0];
					end
				endcase
				wbs_ack_o_next = ~wbs_ack_o_reg;
			end
			else begin
				case (wbs_adr_i)
					3'h0: begin
						wbs_dat_o_next[0] = busy_int;
						wbs_dat_o_next[1] = bus_control_int;
						wbs_dat_o_next[2] = bus_active_int;
						wbs_dat_o_next[3] = missed_ack_reg;
						wbs_dat_o_next[4] = 1'b0;
						wbs_dat_o_next[5] = 1'b0;
						wbs_dat_o_next[6] = 1'b0;
						wbs_dat_o_next[7] = 1'b0;
						wbs_dat_o_next[8] = cmd_fifo_empty;
						wbs_dat_o_next[9] = cmd_fifo_full;
						wbs_dat_o_next[10] = cmd_fifo_overflow_reg;
						wbs_dat_o_next[11] = write_fifo_empty;
						wbs_dat_o_next[12] = write_fifo_full;
						wbs_dat_o_next[13] = write_fifo_overflow_reg;
						wbs_dat_o_next[14] = read_fifo_empty;
						wbs_dat_o_next[15] = read_fifo_full;
						if (wbs_sel_i[0])
							missed_ack_next = missed_ack_int;
						if (wbs_sel_i[1]) begin
							cmd_fifo_overflow_next = 1'b0;
							write_fifo_overflow_next = 1'b0;
						end
					end
					3'h2: begin
						wbs_dat_o_next[6:0] = cmd_address_reg;
						wbs_dat_o_next[7] = 1'b0;
						wbs_dat_o_next[8] = cmd_start_reg;
						wbs_dat_o_next[9] = cmd_read_reg;
						wbs_dat_o_next[10] = cmd_write_reg;
						wbs_dat_o_next[11] = cmd_write_multiple_reg;
						wbs_dat_o_next[12] = cmd_stop_reg;
						wbs_dat_o_next[13] = 1'b0;
						wbs_dat_o_next[14] = 1'b0;
						wbs_dat_o_next[15] = 1'b0;
					end
					3'h4: begin
						wbs_dat_o_next[7:0] = data_out;
						wbs_dat_o_next[8] = data_out_valid;
						wbs_dat_o_next[9] = data_out_last;
						wbs_dat_o_next[15:10] = 6'd0;
						if (wbs_sel_i[0])
							data_out_ready_next = !wbs_ack_o_reg && data_out_valid;
					end
					3'h6: wbs_dat_o_next = prescale_reg;
				endcase
				wbs_ack_o_next = ~wbs_ack_o_reg;
			end
	end
	always @(posedge clk) begin
		if (rst) begin
			wbs_ack_o_reg <= 1'b0;
			cmd_valid_reg <= 1'b0;
			data_in_valid_reg <= 1'b0;
			data_out_ready_reg <= 1'b0;
			prescale_reg <= DEFAULT_PRESCALE;
			missed_ack_reg <= 1'b0;
			cmd_fifo_overflow_reg <= 0;
			write_fifo_overflow_reg <= 0;
		end
		else begin
			wbs_ack_o_reg <= wbs_ack_o_next;
			cmd_valid_reg <= cmd_valid_next;
			data_in_valid_reg <= data_in_valid_next;
			data_out_ready_reg <= data_out_ready_next;
			prescale_reg <= prescale_next;
			missed_ack_reg <= missed_ack_next;
			cmd_fifo_overflow_reg <= cmd_fifo_overflow_next;
			write_fifo_overflow_reg <= write_fifo_overflow_next;
		end
		wbs_dat_o_reg <= wbs_dat_o_next;
		cmd_address_reg <= cmd_address_next;
		cmd_start_reg <= cmd_start_next;
		cmd_read_reg <= cmd_read_next;
		cmd_write_reg <= cmd_write_next;
		cmd_write_multiple_reg <= cmd_write_multiple_next;
		cmd_stop_reg <= cmd_stop_next;
		data_in_reg <= data_in_next;
		data_in_last_reg <= data_in_last_next;
	end
	i2c_master i2c_master_inst(
		.clk(clk),
		.rst(rst),
		.cmd_address(cmd_address_int),
		.cmd_start(cmd_start_int),
		.cmd_read(cmd_read_int),
		.cmd_write(cmd_write_int),
		.cmd_write_multiple(cmd_write_multiple_int),
		.cmd_stop(cmd_stop_int),
		.cmd_valid(cmd_valid_int),
		.cmd_ready(cmd_ready_int),
		.data_in(data_in_int),
		.data_in_valid(data_in_valid_int),
		.data_in_ready(data_in_ready_int),
		.data_in_last(data_in_last_int),
		.data_out(data_out_int),
		.data_out_valid(data_out_valid_int),
		.data_out_ready(data_out_ready_int),
		.data_out_last(data_out_last_int),
		.scl_i(i2c_scl_i),
		.scl_o(i2c_scl_o),
		.scl_t(i2c_scl_t),
		.sda_i(i2c_sda_i),
		.sda_o(i2c_sda_o),
		.sda_t(i2c_sda_t),
		.busy(busy_int),
		.bus_control(bus_control_int),
		.bus_active(bus_active_int),
		.missed_ack(missed_ack_int),
		.prescale(prescale_reg),
		.stop_on_idle(1'b0)
	);
endmodule
module spi_controller (
	i_Rst,
	i_Clk,
	i_TX_Byte,
	i_TX_DV,
	o_TX_Ready,
	o_RX_DV,
	o_RX_Byte,
	i_CPOL,
	i_CPHA,
	i_divider,
	o_SPI_Clk,
	i_SPI_MISO,
	o_SPI_MOSI
);
	input i_Rst;
	input i_Clk;
	input [7:0] i_TX_Byte;
	input i_TX_DV;
	output reg o_TX_Ready;
	output reg o_RX_DV;
	output reg [7:0] o_RX_Byte;
	input wire i_CPOL;
	input wire i_CPHA;
	input wire [15:0] i_divider;
	output reg o_SPI_Clk;
	input i_SPI_MISO;
	output reg o_SPI_MOSI;
	reg [18:0] r_SPI_Clk_Count;
	reg r_SPI_Clk;
	reg [4:0] r_SPI_Clk_Edges;
	reg r_Leading_Edge;
	reg r_Trailing_Edge;
	reg r_TX_DV;
	reg [7:0] r_TX_Byte;
	reg [2:0] r_RX_Bit_Count;
	reg [2:0] r_TX_Bit_Count;
	always @(posedge i_Clk)
		if (i_Rst) begin
			o_TX_Ready <= 1'b0;
			r_SPI_Clk_Edges <= 0;
			r_Leading_Edge <= 1'b0;
			r_Trailing_Edge <= 1'b0;
			r_SPI_Clk <= i_CPOL;
			r_SPI_Clk_Count <= 0;
		end
		else begin
			r_Leading_Edge <= 1'b0;
			r_Trailing_Edge <= 1'b0;
			if (i_TX_DV) begin
				o_TX_Ready <= 1'b0;
				r_SPI_Clk_Edges <= 16;
			end
			else if (r_SPI_Clk_Edges > 0) begin
				o_TX_Ready <= 1'b0;
				if (r_SPI_Clk_Count == ((i_divider * 2) - 1)) begin
					r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1;
					r_Trailing_Edge <= 1'b1;
					r_SPI_Clk_Count <= 0;
					r_SPI_Clk <= ~r_SPI_Clk;
				end
				else if (r_SPI_Clk_Count == (i_divider - 1)) begin
					r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1;
					r_Leading_Edge <= 1'b1;
					r_SPI_Clk_Count <= r_SPI_Clk_Count + 1;
					r_SPI_Clk <= ~r_SPI_Clk;
				end
				else
					r_SPI_Clk_Count <= r_SPI_Clk_Count + 1;
			end
			else begin
				o_TX_Ready <= 1'b1;
				r_SPI_Clk_Edges <= 0;
				r_Leading_Edge <= 1'b0;
				r_Trailing_Edge <= 1'b0;
				r_SPI_Clk <= i_CPOL;
				r_SPI_Clk_Count <= 0;
			end
		end
	always @(posedge i_Clk)
		if (i_Rst) begin
			r_TX_Byte <= 8'h00;
			r_TX_DV <= 1'b0;
		end
		else begin
			r_TX_DV <= i_TX_DV;
			if (i_TX_DV)
				r_TX_Byte <= i_TX_Byte;
		end
	always @(posedge i_Clk)
		if (i_Rst) begin
			o_SPI_MOSI <= 1'b0;
			r_TX_Bit_Count <= 3'b111;
		end
		else if (o_TX_Ready)
			r_TX_Bit_Count <= 3'b111;
		else if (r_TX_DV & ~i_CPHA) begin
			o_SPI_MOSI <= r_TX_Byte[3'b111];
			r_TX_Bit_Count <= 3'b110;
		end
		else if ((r_Leading_Edge & i_CPHA) | (r_Trailing_Edge & ~i_CPHA)) begin
			r_TX_Bit_Count <= r_TX_Bit_Count - 1;
			o_SPI_MOSI <= r_TX_Byte[r_TX_Bit_Count];
		end
	always @(posedge i_Clk)
		if (i_Rst) begin
			o_RX_Byte <= 8'h00;
			o_RX_DV <= 1'b0;
			r_RX_Bit_Count <= 3'b111;
		end
		else begin
			o_RX_DV <= 1'b0;
			if (o_TX_Ready)
				r_RX_Bit_Count <= 3'b111;
			else if ((r_Leading_Edge & ~i_CPHA) | (r_Trailing_Edge & i_CPHA)) begin
				o_RX_Byte[r_RX_Bit_Count] <= i_SPI_MISO;
				r_RX_Bit_Count <= r_RX_Bit_Count - 1;
				if (r_RX_Bit_Count == 3'b000)
					o_RX_DV <= 1'b1;
			end
		end
	always @(posedge i_Clk)
		if (i_Rst)
			o_SPI_Clk <= i_CPOL;
		else
			o_SPI_Clk <= r_SPI_Clk;
endmodule
`default_nettype none
module hyper_xface (
	reset,
	clk,
	rd_req,
	wr_req,
	mem_or_reg,
	wr_byte_en,
	rd_num_dwords,
	addr,
	wr_d,
	rd_d,
	rd_rdy,
	busy,
	burst_wr_rdy,
	latency_1x,
	latency_2x,
	dram_dq_in,
	dram_dq_out,
	dram_dq_oe_l,
	dram_rwds_in,
	dram_rwds_out,
	dram_rwds_oe_l,
	dram_ck,
	dram_rst_l,
	dram_cs_l,
	sump_dbg
);
	input wire reset;
	input wire clk;
	input wire rd_req;
	input wire wr_req;
	input wire mem_or_reg;
	input wire [3:0] wr_byte_en;
	input wire [5:0] rd_num_dwords;
	input wire [31:0] addr;
	input wire [31:0] wr_d;
	output reg [31:0] rd_d;
	output reg rd_rdy;
	output reg busy;
	output reg burst_wr_rdy;
	input wire [7:0] latency_1x;
	input wire [7:0] latency_2x;
	input wire [7:0] dram_dq_in;
	output reg [7:0] dram_dq_out;
	output reg dram_dq_oe_l;
	input wire dram_rwds_in;
	output reg dram_rwds_out;
	output reg dram_rwds_oe_l;
	output reg dram_ck;
	output wire dram_rst_l;
	output wire dram_cs_l;
	output wire [7:0] sump_dbg;
	reg [47:0] addr_sr;
	reg [31:0] data_sr;
	reg [31:0] rd_sr;
	reg [1:0] ck_phs;
	reg [2:0] fsm_addr;
	reg [3:0] fsm_data;
	reg [5:0] fsm_wait;
	reg run_rd_jk;
	reg run_jk;
	reg [3:0] run_jk_sr;
	reg go_bit;
	reg rw_bit;
	reg reg_bit;
	reg rwds_in_loc;
	reg rwds_in_loc_p1;
	reg byte_wr_en;
	reg [7:0] sr_data;
	reg [3:0] sr_byte_en;
	reg [7:0] dram_rd_d;
	reg addr_shift;
	reg data_shift;
	reg wait_shift;
	reg cs_loc;
	reg cs_l_reg;
	reg dram_ck_loc;
	reg rd_done;
	reg [3:0] rd_cnt;
	reg [2:0] rd_fsm;
	reg [5:0] rd_dwords_cnt;
	reg sample_now;
	reg burst_wr_jk;
	reg burst_wr_jk_clr;
	reg [4:0] burst_wr_sr;
	reg [35:0] burst_wr_d;
	assign dram_rst_l = ~reset;
	always @(posedge clk) begin : proc_ck
		if (run_jk == 1)
			ck_phs <= ck_phs + 1;
		else
			ck_phs <= 2'd0;
	end
	always @(posedge clk) begin : proc_lb_regs
		rd_d <= 32'd0;
		rd_rdy <= 0;
		go_bit <= 0;
		busy <= run_jk | go_bit;
		if (addr_shift == 1)
			addr_sr[47:0] <= {addr_sr[39:0], 8'd0};
		if (data_shift == 1) begin
			data_sr[31:0] <= {data_sr[23:0], 8'd0};
			sr_byte_en[3:0] <= {sr_byte_en[2:0], 1'b0};
		end
		if (burst_wr_jk_clr == 1) begin
			data_sr[31:0] <= burst_wr_d[31:0];
			sr_byte_en[3:0] <= burst_wr_d[35:32];
		end
		if ((run_jk == 0) && ((wr_req == 1) || (rd_req == 1))) begin
			burst_wr_jk <= 0;
			busy <= 1;
			go_bit <= 1;
			sr_byte_en <= wr_byte_en[3:0];
			rw_bit <= rd_req;
			reg_bit <= mem_or_reg;
			addr_sr[47] <= rd_req;
			addr_sr[46] <= mem_or_reg;
			addr_sr[45] <= 1'b1;
			addr_sr[15:3] <= 13'd0;
			if (mem_or_reg == 0) begin
				addr_sr[44:16] <= addr[30:2];
				addr_sr[2:0] <= {addr[1:0], 1'b0};
			end
			else begin
				addr_sr[44:16] <= addr[31:3];
				addr_sr[2:0] <= addr[2:0];
			end
			data_sr[31:0] <= wr_d[31:0];
		end
		if (burst_wr_jk_clr == 1)
			burst_wr_jk <= 0;
		if (((run_jk == 1) && (wr_req == 1)) && (burst_wr_sr[4:0] != 5'd0)) begin
			burst_wr_jk <= 1;
			burst_wr_d[31:0] <= wr_d[31:0];
			burst_wr_d[35:32] <= wr_byte_en[3:0];
		end
		if (rd_done == 1) begin
			rd_d <= rd_sr[31:0];
			rd_rdy <= 1;
		end
		if (reset == 1) begin
			go_bit <= 0;
			burst_wr_jk <= 0;
		end
	end
	always @(posedge clk) begin : proc_fsm
		addr_shift <= 0;
		data_shift <= 0;
		wait_shift <= 0;
		burst_wr_jk_clr <= 0;
		if (rd_req == 1)
			rd_dwords_cnt <= rd_num_dwords[5:0];
		if (ck_phs[0] == 1) begin
			if (fsm_addr != 3'd0) begin
				dram_dq_oe_l <= 0;
				dram_rwds_oe_l <= 1;
				fsm_addr <= fsm_addr - 1;
				if (fsm_addr == 3'd1) begin
					if ((reg_bit == 1) && (rw_bit == 0)) begin
						fsm_wait <= 6'd0;
						fsm_data <= 4'd2;
					end
					else if (rwds_in_loc == 0)
						fsm_wait <= latency_1x[5:0];
					else
						fsm_wait <= latency_2x[5:0];
					if (rw_bit == 1) begin
						fsm_wait <= 6'd63;
						run_rd_jk <= 1;
					end
				end
				else begin
					fsm_wait <= 6'd0;
					fsm_data <= 4'd0;
				end
				sr_data <= addr_sr[47:40];
				addr_shift <= 1;
			end
			if (fsm_wait != 6'd0) begin
				byte_wr_en <= 0;
				wait_shift <= 1;
				fsm_wait <= fsm_wait - 1;
				if (fsm_wait == 6'd1)
					fsm_data <= 4'd4;
			end
			if (fsm_data != 4'd0) begin
				fsm_data <= fsm_data - 1;
				sr_data <= data_sr[31:24];
				byte_wr_en <= sr_byte_en[3];
				data_shift <= 1;
				if (fsm_data == 4'd1) begin
					run_jk <= 0;
					if (burst_wr_jk == 1) begin
						run_jk <= 1;
						burst_wr_jk_clr <= 1;
						fsm_data <= 4'd4;
					end
				end
			end
			if ((fsm_wait != 6'd0) || (fsm_data != 4'd0))
				if (rw_bit == 1) begin
					dram_dq_oe_l <= 1;
					dram_rwds_oe_l <= 1;
				end
				else begin
					dram_dq_oe_l <= 0;
					dram_rwds_oe_l <= 0;
				end
		end
		if (rd_done == 1)
			if (rd_dwords_cnt == 6'd1) begin
				run_jk <= 0;
				run_rd_jk <= 0;
				fsm_wait <= 6'd0;
			end
			else begin
				rd_dwords_cnt <= rd_dwords_cnt - 1;
				fsm_wait <= 6'd63;
			end
		if (go_bit == 1) begin
			fsm_addr <= 3'd6;
			fsm_wait <= 6'd0;
			fsm_data <= 4'd0;
			run_jk <= 1;
			dram_dq_oe_l <= 1;
			dram_rwds_oe_l <= 1;
		end
		run_jk_sr <= {run_jk_sr[2:0], run_jk};
		if (run_jk == 1)
			cs_loc <= 1;
		else if (run_jk_sr[1:0] == 2'd0) begin
			cs_loc <= 0;
			dram_dq_oe_l <= 1;
			dram_rwds_oe_l <= 1;
		end
		if (reset == 1) begin
			fsm_addr <= 3'd0;
			fsm_data <= 4'd0;
			fsm_wait <= 6'd0;
			run_jk <= 0;
			run_rd_jk <= 0;
			byte_wr_en <= 0;
			cs_loc <= 0;
		end
		burst_wr_rdy <= 0;
		if ((fsm_data == 4'd4) && (burst_wr_rdy == 0))
			burst_wr_rdy <= 1;
		burst_wr_sr[4:0] <= {burst_wr_sr[3:0], burst_wr_rdy};
	end
	always @(posedge clk) begin : proc_rd_sr
		rwds_in_loc_p1 <= rwds_in_loc;
		rd_done <= 0;
		sample_now <= 0;
		if (run_rd_jk == 0) begin
			rd_fsm <= 3'd4;
			rd_cnt <= 4'd0;
		end
		else if (rd_fsm == 3'd4) begin
			if ((rwds_in_loc == 1) && (rwds_in_loc_p1 == 0)) begin
				rd_fsm <= 3'd0;
				sample_now <= 1;
			end
		end
		else begin
			rd_fsm <= rd_fsm + 1;
			if (rd_fsm == 3'd1) begin
				rd_fsm <= 3'd4;
				sample_now <= 1;
			end
		end
		if (sample_now == 1) begin
			rd_sr[31:0] <= {rd_sr[23:0], dram_rd_d[7:0]};
			rd_cnt <= rd_cnt + 1;
			if (rd_cnt == 4'd3) begin
				rd_done <= 1;
				rd_cnt <= 4'd0;
			end
		end
	end
	assign sump_dbg[0] = busy;
	assign sump_dbg[1] = run_rd_jk;
	assign sump_dbg[2] = sample_now;
	assign sump_dbg[3] = rd_done;
	assign sump_dbg[7:4] = rd_cnt[3:0];
	always @(posedge clk) begin : proc_out
		dram_ck_loc <= ck_phs[1];
		dram_ck <= dram_ck_loc;
		rwds_in_loc <= dram_rwds_in;
		dram_rd_d <= dram_dq_in[7:0];
		dram_dq_out <= sr_data[7:0];
		dram_rwds_out <= ~byte_wr_en;
		cs_l_reg <= ~cs_loc;
		if (reset == 1)
			cs_l_reg <= 1;
	end
	assign dram_cs_l = cs_l_reg;
endmodule