verilog/rtl/user_proj_example.v

// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//      http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0

`default_nettype none

`include "soc.v"

module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,	// User area 1 1.8V supply
    inout vssd1,	// User area 1 digital ground
`endif

    // Wishbone Slave ports (WB MI A)
    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,

    // Logic Analyzer Signals
    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,

    // IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

    // IRQ
    output [2:0] irq
);
    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

soc soc (
    .sys_clk(wb_clk_i),
	.sys_rst(wb_rst_i),
    .io0_i(la_data_in[0]),
    .io0_o(la_data_out[0]),
    .io0_oe(la_data_out[1]),
    .io1_i(la_data_in[2]),
    .io1_o(la_data_out[2]),
    .io1_oe(la_data_out[3]),
    .io2_i(la_data_in[4]),
    .io2_o(la_data_out[4]),
    .io2_oe(la_data_out[5]),
    .io3_i(la_data_in[6]),
    .io3_o(la_data_out[6]),
    .io3_oe(la_data_out[7]),
    .io4_i(la_data_in[8]),
    .io4_o(la_data_out[8]),
    .io4_oe(la_data_out[9]),
    .io5_i(la_data_in[10]),
    .io5_o(la_data_out[10]),
    .io5_oe(la_data_out[11]),
    .io6_i(la_data_in[12]),
    .io6_o(la_data_out[12]),
    .io6_oe(la_data_out[13]),
    .io7_i(la_data_in[14]),
    .io7_o(la_data_out[14]),
    .io7_oe(la_data_out[15]),
    .io8_i(la_data_in[16]),
    .io8_o(la_data_out[16]),
    .io8_oe(la_data_out[17]),
    .io9_i(la_data_in[18]),
    .io9_o(la_data_out[18]),
    .io9_oe(la_data_out[19]),
    .io10_i(la_data_in[20]),
    .io10_o(la_data_out[20]),
    .io10_oe(la_data_out[21]),
    .io11_i(la_data_in[22]),
    .io11_o(la_data_out[22]),
    .io11_oe(la_data_out[23]),
    .io12_i(la_data_in[24]),
    .io12_o(la_data_out[24]),
    .io12_oe(la_data_out[25]),
    .io13_i(la_data_in[26]),
    .io13_o(la_data_out[26]),
    .io13_oe(la_data_out[27]),
    .io14_i(la_data_in[28]),
    .io14_o(la_data_out[28]),
    .io14_oe(la_data_out[29]),
    .io15_i(la_data_in[30]),
    .io15_o(la_data_out[30]),
    .io15_oe(la_data_out[31]),
    .io16_i(la_data_in[32]),
    .io16_o(la_data_out[32]),
    .io16_oe(la_data_out[33]),
    .io17_i(la_data_in[34]),
    .io17_o(la_data_out[34]),
    .io17_oe(la_data_out[35]),
    .io18_i(la_data_in[36]),
    .io18_o(la_data_out[36]),
    .io18_oe(la_data_out[37]),
    .io19_i(la_data_in[38]),
    .io19_o(la_data_out[38]),
    .io19_oe(la_data_out[39]),
	.uart_main_dbg_tx(io_in[0]),
	.uart_main_dbg_rx(io_in[1])
);

endmodule

`default_nettype wire