Updated version of wb_openram_wrapper used.

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index c41fc64..e37987f 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -109,15 +109,9 @@
 wb_openram_wrapper wb_openram_wrapper
 (
 `ifdef USE_POWER_PINS
-    .vdda1 (vdda1),	    // User area 1 3.3V supply
-    .vdda2 (vdda2),	    // User area 2 3.3V supply
-    .vssa1 (vssa1),	    // User area 1 analog ground
-    .vssa2 (vssa2),	    // User area 2 analog ground
     .vccd1 (vccd1),	    // User area 1 1.8V supply
-    .vccd2 (vccd2),	    // User area 2 1.8v supply
     .vssd1 (vssd1),	    // User area 1 digital ground
-    .vssd2 (vssd2),	    // User area 2 digital ground
-`endif
+ `endif
 
     // Wishbone port A
     .wb_clk_i (wb_clk_i),

wb_openram_wrapper

diff --git a/wb_openram_wrapper b/wb_openram_wrapper
index df3a712..31cf2a2 160000
--- a/wb_openram_wrapper
+++ b/wb_openram_wrapper
@@ -1 +1 @@
-Subproject commit df3a7127d07e7144f4846da67b4fbe72457ab505
+Subproject commit 31cf2a272cf7d00c509513abf53c993007e6b3dc