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@@ -5,7 +5,12 @@
| :exclamation: Important Note |
|-----------------------------------------|
-## Please fill in your project documentation in this README.md file
+## Additional memory (internal 1kB of OpenRAM and HyperRAM driver for external memory chip) connected through Wishbone to Caravel SoC for MPW submission
+| Memory block | Space| Address | Size |
+| --- | --- | --- | --- |
+| HyperRAM ext. chip | RAM | 0x3000_0000 - 0x307f_ffff | 8MB |
+| HyperRAM ext. chip | Registers | 0x3080_0000 - 0x3080_ffff | max 64k registers, 16bit each |
+| HyperRAM driver | CSRs | 0x3081_0000 - 0x3081_ffff | max 64kB, 16k CSRs |
+| OpenRAM | RAM | 0x30c0_0000 - 0x30c0_ffff | max 64kB |
-Refer to [README](docs/source/index.rst) for this sample project documentation.
