commit	c9f9bb19f963023eb222739e0f8aae52a6c7233d	[log] [tgz]
author	embelon <78412338+embelon@users.noreply.github.com>	Thu Nov 11 09:21:27 2021 +0100
committer	GitHub <noreply@github.com>	Thu Nov 11 09:21:27 2021 +0100
tree	f8884556ce8e6f5a72a169e7b7bbfd4d40587f72
parent	5a7326c09a825001624d7b5e8abdef3c565041cc [diff]

Update README.md

README.md[diff]

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tree: f8884556ce8e6f5a72a169e7b7bbfd4d40587f72

README.md

Caravel User Project

:exclamation: Important Note

Additional memory (internal 1kB of OpenRAM and HyperRAM driver for external memory chip) connected through Wishbone to Caravel SoC for MPW submission

Memory block	Space	Address	Size
HyperRAM ext. chip	RAM	0x3000_0000 - 0x307f_ffff	8MB
HyperRAM ext. chip	Registers	0x3080_0000 - 0x3080_ffff	max 64k registers, 16bit each
HyperRAM driver	CSRs	0x3081_0000 - 0x3081_ffff	max 64kB, 16k CSRs
OpenRAM	RAM	0x30c0_0000 - 0x30c0_ffff	max 64kB