commit	fb9e4a742a8ae6a111d0c43bf30fd95eb1114657	[log] [tgz]
author	embelon <78412338+embelon@users.noreply.github.com>	Thu Oct 14 21:11:38 2021 +0200
committer	embelon <78412338+embelon@users.noreply.github.com>	Thu Oct 14 21:11:38 2021 +0200
tree	be4d418c6627fd9b21e3293d3ce9e80e35c8e049
parent	94fb87d7cb1eaefcd41dee105e2b4f4c3f7589eb [diff]

Removed unused dv tests. Added wb_openram test to dv.

verilog/dv/Makefile[diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_openram/Makefile[Renamed from verilog/dv/mprj_stimulus/Makefile - diff]
verilog/dv/wb_openram/wb_openram.c[Added - diff]
verilog/dv/wb_openram/wb_openram_tb.v[Renamed from verilog/dv/wb_port/wb_port_tb.v - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_proj_example.v[Deleted - diff]
verilog/rtl/user_project_wrapper.v[diff]

20 files changed

tree: be4d418c6627fd9b21e3293d3ce9e80e35c8e049

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.