Corrected the schematic for the proper orientation of the topmost
capacitor;  the circuit now passes LVS.
4 files changed
tree: a8daa2bef539b81d4dcd68725ac203fd681f8f4f
  1. mag/
  2. netgen/
  3. openlane/
  4. verilog/
  5. xschem/
  6. .gitmodules
  7. info.yaml
  8. LICENSE
  9. Makefile
  10. README.md
README.md

Caravel Analog User

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