commit | 6f3164727bb70f928db22526b75e6172093b7d16 | [log] [tgz] |
---|---|---|
author | chrische <christoph-weiser@gmx.de> | Tue Nov 16 22:57:34 2021 +0100 |
committer | chrische <christoph-weiser@gmx.de> | Tue Nov 16 22:57:34 2021 +0100 |
tree | e39e16a9fe6cfe34a686697365340cb08d38ce3a | |
parent | 7030c49a5cc894a0121ea2e30de9dc3259f11986 [diff] | |
parent | 4a8aa520cdad9a73528edca2e279659b83df3549 [diff] |
merged updates from readme
This is a mixed-mode project featuring a 8-bit SAR-ADC, with offset calibration. The logic section is synthesized using the openlane digital flow.
The adc is composed of a top-plate sampled CDAC, with a capacitor array of mimimum sized MIM caps.
The comparator is a single-stage regenerative comparator, with a MOM array for trimming ADC offset.
The layout is created using magic as a pcell generator and drc checker, while the connection of the design is done using klayout.
The simulation is carried out using ngspice using the mixed-mode xspice capabilities. The digital section is synthesized using yosys that can then be bridged to/from the analog section.
The Schematics are created using xschem, which also serves as the simulation framework.
The SAR schematic:
The simulation output can then be viewed in both analog and digital domain.
Digital waveforms displayed using GTKWave
Analog waveforms displayed using Gnuplot in interactive mode.