| commit | 2a2bc76880fa82af76ceb8aeb66f75a424bc12dc | [log] [tgz] |
|---|---|---|
| author | chrische <christoph-weiser@gmx.de> | Fri Nov 12 23:08:19 2021 +0100 |
| committer | chrische <christoph-weiser@gmx.de> | Fri Nov 12 23:08:19 2021 +0100 |
| tree | d2a6a12c16f1f079976985d5a1e1aa9e9712e890 | |
| parent | 3e86a67d8011a2d409ed5b69047864983b092ce4 [diff] |
added pictures for README.md
This is a mixed-mode project featuring a 8-bit SAR-ADC, with offset calibration. The logic section is synthesized using the openlane digital flow.
The adc is composed of a top-plate sampled CDAC, with a capacitor array of mimimum sized MIM caps.
The comparator is a single-stage regenerative comparator, with a MOM array for trimming ADC offset.
The simulation is carried out using ngspice using the mixed-mode xspice capabilities. The digital section is synthesized using yosys that can then be bridged to/from the analog section.
The layout is created using magic as a pcell generator and drc checker, while the connection of the design is done using klayout.
