| commit | 00ba5de3cee6b2af58e7667b611b7da1c8901263 | [log] [tgz] |
|---|---|---|
| author | chrische <christoph-weiser@gmx.de> | Fri Nov 12 21:12:44 2021 +0100 |
| committer | chrische <christoph-weiser@gmx.de> | Fri Nov 12 21:12:44 2021 +0100 |
| tree | 14421b2d671f39740b52aeea93b47a99cf682441 | |
| parent | a74e4d888683d5ecbbc5e1efe66e351591195be8 [diff] |
passing precheck
This is a mixed-mode project featuring a 8-bit SAR-ADC, with offset calibration. The logic section is synthesized using the openlane digital flow.
The adc is composed of a top-plate sampled CDAC, with a capacitor array of mimimum sized MIM caps.
The comparator is a single-stage regenerative comparator, with a MOM array for trimming ADC offset.
The simulation is carried out using ngspice using the mixed-mode xspice capabilities. The digital section is synthesized using yosys that can then be bridged to/from the analog section.
The layout is created using magic as a pcell generator and drc checker, while the connection of the design is done using klayout.