| commit | 77f1423f7033ad9edcb31e092deae702e4a9d5b1 | [log] [tgz] |
|---|---|---|
| author | Git bot <bot@noreply.github.com> | Sat Dec 18 00:53:20 2021 +0000 |
| committer | Git bot <bot@noreply.github.com> | Sat Dec 18 00:53:20 2021 +0000 |
| tree | d1f4e1c499cc16393a66e7023d81aad512eafda0 | |
| parent | 85978e7104c2441a096f55e3425f580b3472b255 [diff] |
Auto updated submodule references
This is a simple project connecting a 256x32 SRAM block to the wishbone interface for testing. The SRAM block is directly connected to the wishbone bus at address 0x3000000. An additional perpherial was made to write to the io ports when address 0x30008000 is written to.
Refer to README for this sample project documentation.