README.md and info.yaml added.
diff --git a/README.md b/README.md index 3706438..6b35e29 100644 --- a/README.md +++ b/README.md
@@ -1,11 +1,19 @@ -# Caravel User Project +# Introduction to the VSDMemSoC -[](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml) +VSDMemSoC is a small yet powerful RISCV-based SoC. The main purpose of designing such an SoC is to demonstrate the concept of separating the main core and memories of a processor. This would help to make the RISC-V more modular and portable. Here, the instruction memory will be separated -| :exclamation: Important Note | -|-----------------------------------------| +## Problem statement -## Please fill in your project documentation in this README.md file +This work discusses the different aspects of designing a small SoC based on RVMYTH (a RISCV-based processor). This SoC will leverage a 1KB external SRAM as the instruction memory where the program is loaded from. At the end of the day, it is possible to use this small fully open-source and well-documented SoC which has been fabricated under Sky130 technology, for educational purposes. +## What is SoC -Refer to [README](docs/source/index.rst) for this sample project documentation. +An SoC is a single-die chip that has some different IP cores on it. These IPs could vary from microprocessors (completely digital) to 5G broadband modems (completely analog). Here we have a RISC-V core and a 1KB SRAM instruction memory. + +## What is RVMYTH + +RVMYTH core is a simple RISCV-based CPU, introduced in a workshop by RedwoodEDA and VSD. During a 5-day workshop, students (including middle-schoolers) managed to create a processor from scratch. The workshop used the TLV for faster development. All of the present and future contributions to the IP will be done by students and under open-source licenses. + +## What is SRAM + +An SRAM is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. It is a volatile memory where data is lost when power is removed. It is typically used for the cache and internal registers of a CPU as it very fast but expensive. The SRAM here is a 1KB 6-transistor type with an 8-bit address bus and 32-bit data bus. We will leverage OpenRAM memory compiler to design such IP core using Sky130 technology. \ No newline at end of file
diff --git a/docs/source/_static/vsdmemsoc_layout.png b/docs/source/_static/vsdmemsoc_layout.png new file mode 100644 index 0000000..aa90e1d --- /dev/null +++ b/docs/source/_static/vsdmemsoc_layout.png Binary files differ
diff --git a/info.yaml b/info.yaml new file mode 100644 index 0000000..963e724 --- /dev/null +++ b/info.yaml
@@ -0,0 +1,22 @@ +--- +project: + description: "VSDMemSoC is a small SoC including a RISCV-based processor named RVMYTH and an external 1KB SRAM Instruction Memory." + foundry: "SkyWater" + git_url: "https://github.com/manili/vsdmemsoc_mpw3.git" + organization: "VLSI System Design" + organization_url: "https://www.vlsisystemdesign.com" + owner: "Mufutau Akuruyejo, Mohammad A. Nili" + process: "SKY130" + project_name: "VSDMemSoC" + project_id: "87654321" + tags: + - "MPW3" + - "VSD" + - "RVMYTH" + - "OpenRAM" + - "VSDMemSoC" + category: "Test Harness" + top_level_netlist: "caravel/verilog/gl/caravel.v" + user_level_netlist: "verilog/gl/user_project_wrapper.v" + version: "1.00" + cover_image: "docs/source/_static/vsdmemsoc_layout.png" \ No newline at end of file
