Ready for PD phase
diff --git a/gds/sram_32_256_sky130A.gds b/gds/sram_32_256_sky130A.gds new file mode 100644 index 0000000..17f5412 --- /dev/null +++ b/gds/sram_32_256_sky130A.gds Binary files differ
diff --git a/lef/sram_32_256_sky130A.lef b/lef/sram_32_256_sky130A.lef new file mode 100644 index 0000000..d829f87 --- /dev/null +++ b/lef/sram_32_256_sky130A.lef
@@ -0,0 +1,697 @@ +VERSION 5.7 ; + NOWIREEXTENSIONATPIN ON ; + DIVIDERCHAR "/" ; + BUSBITCHARS "[]" ; +MACRO sram_32_256_sky130A + CLASS BLOCK ; + FOREIGN sram_32_256_sky130A ; + ORIGIN 0.000 0.000 ; + SIZE 578.380 BY 355.340 ; + PIN csb0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 20.400 16.020 20.780 ; + END + END csb0 + PIN web0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 22.440 15.220 22.820 ; + END + END web0 + PIN clk0 + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 38.080 0.000 38.460 18.390 ; + END + END clk0 + PIN din0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 131.240 0.000 131.620 14.990 ; + END + END din0[0] + PIN din0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 143.480 0.000 143.860 14.990 ; + END + END din0[1] + PIN din0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 157.760 0.000 158.140 14.990 ; + END + END din0[2] + PIN din0[3] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 170.000 0.000 170.380 14.990 ; + END + END din0[3] + PIN din0[4] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 182.920 0.000 183.300 14.990 ; + END + END din0[4] + PIN din0[5] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 196.520 0.000 196.900 14.990 ; + END + END din0[5] + PIN din0[6] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 209.440 0.000 209.820 14.990 ; + END + END din0[6] + PIN din0[7] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 222.360 0.000 222.740 14.990 ; + END + END din0[7] + PIN din0[8] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 235.960 0.000 236.340 14.990 ; + END + END din0[8] + PIN din0[9] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 249.560 0.000 249.940 14.990 ; + END + END din0[9] + PIN din0[10] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 262.480 0.000 262.860 14.990 ; + END + END din0[10] + PIN din0[11] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 275.400 0.000 275.780 14.990 ; + END + END din0[11] + PIN din0[12] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 288.320 0.000 288.700 14.990 ; + END + END din0[12] + PIN din0[13] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 301.240 0.000 301.620 14.990 ; + END + END din0[13] + PIN din0[14] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 314.840 0.000 315.220 14.990 ; + END + END din0[14] + PIN din0[15] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 328.440 0.000 328.820 14.990 ; + END + END din0[15] + PIN din0[16] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 340.680 0.000 341.060 14.990 ; + END + END din0[16] + PIN din0[17] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 354.280 0.000 354.660 14.990 ; + END + END din0[17] + PIN din0[18] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 367.200 0.000 367.580 14.990 ; + END + END din0[18] + PIN din0[19] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 380.800 0.000 381.180 14.990 ; + END + END din0[19] + PIN din0[20] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 393.040 0.000 393.420 14.990 ; + END + END din0[20] + PIN din0[21] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 406.640 0.000 407.020 14.990 ; + END + END din0[21] + PIN din0[22] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 420.240 0.000 420.620 14.990 ; + END + END din0[22] + PIN din0[23] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 433.160 0.000 433.540 14.990 ; + END + END din0[23] + PIN din0[24] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 445.400 0.000 445.780 14.990 ; + END + END din0[24] + PIN din0[25] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 459.000 0.000 459.380 14.990 ; + END + END din0[25] + PIN din0[26] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 471.920 0.000 472.300 14.990 ; + END + END din0[26] + PIN din0[27] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 484.840 0.000 485.220 14.990 ; + END + END din0[27] + PIN din0[28] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 499.120 0.000 499.500 14.990 ; + END + END din0[28] + PIN din0[29] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 512.040 0.000 512.420 14.990 ; + END + END din0[29] + PIN din0[30] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 524.280 0.000 524.660 14.990 ; + END + END din0[30] + PIN din0[31] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 537.880 0.000 538.260 14.990 ; + END + END din0[31] + PIN dout0[0] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 140.760 0.000 141.140 32.670 ; + END + END dout0[0] + PIN dout0[1] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 153.680 0.000 154.060 32.670 ; + END + END dout0[1] + PIN dout0[2] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 166.600 0.000 166.980 32.670 ; + END + END dout0[2] + PIN dout0[3] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 179.520 0.000 179.900 32.670 ; + END + END dout0[3] + PIN dout0[4] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 193.120 0.000 193.500 32.670 ; + END + END dout0[4] + PIN dout0[5] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 206.040 0.000 206.420 32.670 ; + END + END dout0[5] + PIN dout0[6] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 218.960 0.000 219.340 32.670 ; + END + END dout0[6] + PIN dout0[7] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 232.560 0.000 232.940 32.670 ; + END + END dout0[7] + PIN dout0[8] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 245.480 0.000 245.860 32.670 ; + END + END dout0[8] + PIN dout0[9] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 258.400 0.000 258.780 32.670 ; + END + END dout0[9] + PIN dout0[10] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 272.000 0.000 272.380 32.670 ; + END + END dout0[10] + PIN dout0[11] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 284.920 0.000 285.300 32.670 ; + END + END dout0[11] + PIN dout0[12] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 297.840 0.000 298.220 32.670 ; + END + END dout0[12] + PIN dout0[13] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 311.440 0.000 311.820 32.670 ; + END + END dout0[13] + PIN dout0[14] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 324.360 0.000 324.740 32.670 ; + END + END dout0[14] + PIN dout0[15] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 337.280 0.000 337.660 32.670 ; + END + END dout0[15] + PIN dout0[16] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 350.880 0.000 351.260 32.670 ; + END + END dout0[16] + PIN dout0[17] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 363.800 0.000 364.180 32.670 ; + END + END dout0[17] + PIN dout0[18] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 377.400 0.000 377.780 32.670 ; + END + END dout0[18] + PIN dout0[19] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 391.000 0.000 391.380 32.670 ; + END + END dout0[19] + PIN dout0[20] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 403.240 0.000 403.620 32.670 ; + END + END dout0[20] + PIN dout0[21] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 417.520 0.000 417.900 32.670 ; + END + END dout0[21] + PIN dout0[22] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 430.440 0.000 430.820 32.670 ; + END + END dout0[22] + PIN dout0[23] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 443.360 0.000 443.740 32.670 ; + END + END dout0[23] + PIN dout0[24] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 456.280 0.000 456.660 32.670 ; + END + END dout0[24] + PIN dout0[25] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 469.200 0.000 469.580 32.670 ; + END + END dout0[25] + PIN dout0[26] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 482.800 0.000 483.180 32.670 ; + END + END dout0[26] + PIN dout0[27] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 495.720 0.000 496.100 32.670 ; + END + END dout0[27] + PIN dout0[28] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 509.320 0.000 509.700 32.670 ; + END + END dout0[28] + PIN dout0[29] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 522.240 0.000 522.620 32.670 ; + END + END dout0[29] + PIN dout0[30] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 535.160 0.000 535.540 32.670 ; + END + END dout0[30] + PIN dout0[31] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 549.260 33.320 578.380 33.700 ; + END + END dout0[31] + PIN addr0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 104.720 0.000 105.100 14.990 ; + END + END addr0[0] + PIN addr0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 117.640 0.000 118.020 14.990 ; + END + END addr0[1] + PIN addr0[2] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 132.600 78.430 132.980 ; + END + END addr0[2] + PIN addr0[3] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 135.320 78.430 135.700 ; + END + END addr0[3] + PIN addr0[4] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 141.440 78.430 141.820 ; + END + END addr0[4] + PIN addr0[5] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 143.480 79.260 143.860 ; + END + END addr0[5] + PIN addr0[6] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 150.280 79.260 150.660 ; + END + END addr0[6] + PIN addr0[7] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 151.640 9.900 152.020 ; + END + END addr0[7] + PIN vccd1 + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER met4 ; + RECT 4.760 4.760 6.500 351.940 ; + LAYER met3 ; + RECT 4.760 4.760 573.620 6.500 ; + LAYER met3 ; + RECT 4.760 350.200 573.620 351.940 ; + LAYER met4 ; + RECT 571.880 4.760 573.620 351.940 ; + END + END vccd1 + PIN vssd1 + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER met4 ; + RECT 575.280 1.360 577.020 355.340 ; + LAYER met3 ; + RECT 1.360 353.600 577.020 355.340 ; + LAYER met3 ; + RECT 1.360 1.360 577.020 3.100 ; + LAYER met4 ; + RECT 1.360 1.360 3.100 355.340 ; + END + END vssd1 + OBS + LAYER li1 ; + RECT 8.575 8.445 569.385 347.845 ; + LAYER met1 ; + RECT 8.100 8.050 569.860 348.240 ; + LAYER met2 ; + RECT 8.100 8.050 569.860 348.240 ; + LAYER met3 ; + RECT 2.720 152.420 575.660 348.540 ; + RECT 10.300 151.240 575.660 152.420 ; + RECT 2.720 151.060 575.660 151.240 ; + RECT 79.660 149.880 575.660 151.060 ; + RECT 2.720 144.260 575.660 149.880 ; + RECT 79.660 143.080 575.660 144.260 ; + RECT 2.720 142.220 575.660 143.080 ; + RECT 78.830 141.040 575.660 142.220 ; + RECT 2.720 136.100 575.660 141.040 ; + RECT 78.830 134.920 575.660 136.100 ; + RECT 2.720 133.380 575.660 134.920 ; + RECT 78.830 132.200 575.660 133.380 ; + RECT 2.720 34.100 575.660 132.200 ; + RECT 2.720 32.920 548.860 34.100 ; + RECT 2.720 23.220 575.660 32.920 ; + RECT 15.620 22.040 575.660 23.220 ; + RECT 2.720 21.180 575.660 22.040 ; + RECT 16.420 20.000 575.660 21.180 ; + RECT 2.720 8.160 575.660 20.000 ; + LAYER met4 ; + RECT 9.520 33.070 568.860 350.580 ; + RECT 9.520 18.790 140.360 33.070 ; + RECT 9.520 2.720 37.680 18.790 ; + RECT 38.860 15.390 140.360 18.790 ; + RECT 38.860 2.720 104.320 15.390 ; + RECT 105.500 2.720 117.240 15.390 ; + RECT 118.420 2.720 130.840 15.390 ; + RECT 132.020 2.720 140.360 15.390 ; + RECT 141.540 15.390 153.280 33.070 ; + RECT 141.540 2.720 143.080 15.390 ; + RECT 144.260 2.720 153.280 15.390 ; + RECT 154.460 15.390 166.200 33.070 ; + RECT 154.460 2.720 157.360 15.390 ; + RECT 158.540 2.720 166.200 15.390 ; + RECT 167.380 15.390 179.120 33.070 ; + RECT 167.380 2.720 169.600 15.390 ; + RECT 170.780 2.720 179.120 15.390 ; + RECT 180.300 15.390 192.720 33.070 ; + RECT 180.300 2.720 182.520 15.390 ; + RECT 183.700 2.720 192.720 15.390 ; + RECT 193.900 15.390 205.640 33.070 ; + RECT 193.900 2.720 196.120 15.390 ; + RECT 197.300 2.720 205.640 15.390 ; + RECT 206.820 15.390 218.560 33.070 ; + RECT 206.820 2.720 209.040 15.390 ; + RECT 210.220 2.720 218.560 15.390 ; + RECT 219.740 15.390 232.160 33.070 ; + RECT 219.740 2.720 221.960 15.390 ; + RECT 223.140 2.720 232.160 15.390 ; + RECT 233.340 15.390 245.080 33.070 ; + RECT 233.340 2.720 235.560 15.390 ; + RECT 236.740 2.720 245.080 15.390 ; + RECT 246.260 15.390 258.000 33.070 ; + RECT 246.260 2.720 249.160 15.390 ; + RECT 250.340 2.720 258.000 15.390 ; + RECT 259.180 15.390 271.600 33.070 ; + RECT 259.180 2.720 262.080 15.390 ; + RECT 263.260 2.720 271.600 15.390 ; + RECT 272.780 15.390 284.520 33.070 ; + RECT 272.780 2.720 275.000 15.390 ; + RECT 276.180 2.720 284.520 15.390 ; + RECT 285.700 15.390 297.440 33.070 ; + RECT 285.700 2.720 287.920 15.390 ; + RECT 289.100 2.720 297.440 15.390 ; + RECT 298.620 15.390 311.040 33.070 ; + RECT 298.620 2.720 300.840 15.390 ; + RECT 302.020 2.720 311.040 15.390 ; + RECT 312.220 15.390 323.960 33.070 ; + RECT 312.220 2.720 314.440 15.390 ; + RECT 315.620 2.720 323.960 15.390 ; + RECT 325.140 15.390 336.880 33.070 ; + RECT 325.140 2.720 328.040 15.390 ; + RECT 329.220 2.720 336.880 15.390 ; + RECT 338.060 15.390 350.480 33.070 ; + RECT 338.060 2.720 340.280 15.390 ; + RECT 341.460 2.720 350.480 15.390 ; + RECT 351.660 15.390 363.400 33.070 ; + RECT 351.660 2.720 353.880 15.390 ; + RECT 355.060 2.720 363.400 15.390 ; + RECT 364.580 15.390 377.000 33.070 ; + RECT 364.580 2.720 366.800 15.390 ; + RECT 367.980 2.720 377.000 15.390 ; + RECT 378.180 15.390 390.600 33.070 ; + RECT 378.180 2.720 380.400 15.390 ; + RECT 381.580 2.720 390.600 15.390 ; + RECT 391.780 15.390 402.840 33.070 ; + RECT 391.780 2.720 392.640 15.390 ; + RECT 393.820 2.720 402.840 15.390 ; + RECT 404.020 15.390 417.120 33.070 ; + RECT 404.020 2.720 406.240 15.390 ; + RECT 407.420 2.720 417.120 15.390 ; + RECT 418.300 15.390 430.040 33.070 ; + RECT 418.300 2.720 419.840 15.390 ; + RECT 421.020 2.720 430.040 15.390 ; + RECT 431.220 15.390 442.960 33.070 ; + RECT 431.220 2.720 432.760 15.390 ; + RECT 433.940 2.720 442.960 15.390 ; + RECT 444.140 15.390 455.880 33.070 ; + RECT 444.140 2.720 445.000 15.390 ; + RECT 446.180 2.720 455.880 15.390 ; + RECT 457.060 15.390 468.800 33.070 ; + RECT 457.060 2.720 458.600 15.390 ; + RECT 459.780 2.720 468.800 15.390 ; + RECT 469.980 15.390 482.400 33.070 ; + RECT 469.980 2.720 471.520 15.390 ; + RECT 472.700 2.720 482.400 15.390 ; + RECT 483.580 15.390 495.320 33.070 ; + RECT 483.580 2.720 484.440 15.390 ; + RECT 485.620 2.720 495.320 15.390 ; + RECT 496.500 15.390 508.920 33.070 ; + RECT 496.500 2.720 498.720 15.390 ; + RECT 499.900 2.720 508.920 15.390 ; + RECT 510.100 15.390 521.840 33.070 ; + RECT 510.100 2.720 511.640 15.390 ; + RECT 512.820 2.720 521.840 15.390 ; + RECT 523.020 15.390 534.760 33.070 ; + RECT 523.020 2.720 523.880 15.390 ; + RECT 525.060 2.720 534.760 15.390 ; + RECT 535.940 15.390 568.860 33.070 ; + RECT 535.940 2.720 537.480 15.390 ; + RECT 538.660 2.720 568.860 15.390 ; + END +END sram_32_256_sky130A +END LIBRARY +
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl index 94af8ba..71545ce 100755 --- a/openlane/user_proj_example/config.tcl +++ b/openlane/user_proj_example/config.tcl
@@ -22,21 +22,29 @@ set ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" + $script_dir/../../verilog/rtl/user_proj_example.v \ + $script_dir/../../verilog/rtl/clk_gate.v \ + $script_dir/../../verilog/rtl/rvmyth.v" +set ::env(VERILOG_INCLUDE_DIRS) "\ + $script_dir/../../verilog/include" set ::env(DESIGN_IS_CORE) 0 -set ::env(CLOCK_PORT) "wb_clk_i" -set ::env(CLOCK_NET) "counter.clk" -set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PORT) "CLK" +set ::env(CLOCK_NET) "CLK" +set ::env(CLOCK_PERIOD) "50" set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 900 600" +set ::env(DIE_AREA) "0 0 1500 1500" -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(PL_TARGET_DENSITY) 0.2 -set ::env(PL_BASIC_PLACEMENT) 1 -set ::env(PL_TARGET_DENSITY) 0.05 +# You can draw more power domains if you need to +set ::env(VDD_NETS) [list {vccd1}] +set ::env(GND_NETS) [list {vssd1}] + +set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8 +set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8 # Maximum layer used for routing is metal 4. # This is because this macro will be inserted in a top level (user_project_wrapper) @@ -44,10 +52,7 @@ # in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. set ::env(GLB_RT_MAXLAYER) 5 -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vccd1}] -set ::env(GND_NETS) [list {vssd1}] - set ::env(DIODE_INSERTION_STRATEGY) 4 + # If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1 +set ::env(RUN_CVC) 1 \ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 5006ced..7d2b8a4 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -38,10 +38,10 @@ $script_dir/../../verilog/rtl/user_project_wrapper.v" ## Clock configurations -set ::env(CLOCK_PORT) "user_clock2" -set ::env(CLOCK_NET) "mprj.clk" +set ::env(CLOCK_PORT) "wb_clk_i" +set ::env(CLOCK_NET) "wb_clk_i" -set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PERIOD) "50" ## Internal Macros ### Macro PDN Connections @@ -54,13 +54,16 @@ ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" + $script_dir/../../verilog/rtl/user_proj_example.v \ + $script_dir/../../verilog/rtl/sram_32_256_sky130A.v" set ::env(EXTRA_LEFS) "\ - $script_dir/../../lef/user_proj_example.lef" + $script_dir/../../lef/user_proj_example.lef \ + $script_dir/../../lef/sram_32_256_sky130A.lef" set ::env(EXTRA_GDS_FILES) "\ - $script_dir/../../gds/user_proj_example.gds" + $script_dir/../../gds/user_proj_example.gds \ + $script_dir/../../gds/sram_32_256_sky130A.gds" set ::env(GLB_RT_MAXLAYER) 5 @@ -82,4 +85,4 @@ set ::env(DIODE_INSERTION_STRATEGY) 0 set ::env(FILL_INSERTION) 0 set ::env(TAP_DECAP_INSERTION) 0 -set ::env(CLOCK_TREE_SYNTH) 0 +set ::env(CLOCK_TREE_SYNTH) 0 \ No newline at end of file
diff --git a/verilog/gl/clk_gate.v b/verilog/gl/clk_gate.v new file mode 100644 index 0000000..6df5b7d --- /dev/null +++ b/verilog/gl/clk_gate.v
@@ -0,0 +1,36 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +`include "sp_verilog.vh" + + +// Clock gate module used by SandPiper default project. + +module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override); + + assign gated_clk = free_clk; +endmodule
diff --git a/verilog/gl/rvmyth.v b/verilog/gl/rvmyth.v new file mode 100644 index 0000000..9e96890 --- /dev/null +++ b/verilog/gl/rvmyth.v
@@ -0,0 +1,269 @@ +//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta +`include "sp_verilog.vh" //_\SV + // Included URL: "https://raw.githubusercontent.com/shivanishah269/risc-v-core/master/FPGA_Implementation/riscv_shell_lib.tlv"// Included URL: "https://raw.githubusercontent.com/stevehoover/warp-v_includes/2d6d36baa4d2bc62321f982f78c8fe1456641a43/risc-v_defs.tlv" + + module rvmyth ( + output reg [9:0] OUT, + input CLK, + input reset, + + output [7:0] imem_addr, + input [31:0] imem_data + ); + + wire clk = CLK; + +`include "rvmyth_gen.v" +generate //_\TLV + //_|cpu + //_@0 + assign CPU_reset_a0 = reset; + + //Fetch + // Next PC + assign CPU_pc_a0[31:0] = (CPU_reset_a1) ? 32'd0 : + (CPU_valid_taken_br_a3) ? CPU_br_tgt_pc_a3 : + (CPU_valid_load_a3) ? CPU_inc_pc_a3 : + (CPU_valid_jump_a3 && CPU_is_jal_a3) ? CPU_br_tgt_pc_a3 : + (CPU_valid_jump_a3 && CPU_is_jalr_a3) ? CPU_jalr_tgt_pc_a3 : CPU_inc_pc_a1; + + //_@1 + assign imem_addr = CPU_pc_a0[9:2]; + assign CPU_instr_a1[31:0] = imem_data; + assign CPU_inc_pc_a1[31:0] = CPU_pc_a1 + 32'd4; + + // Decode + assign CPU_is_i_instr_a1 = CPU_instr_a1[6:2] == 5'b00000 || + CPU_instr_a1[6:2] == 5'b00001 || + CPU_instr_a1[6:2] == 5'b00100 || + CPU_instr_a1[6:2] == 5'b00110 || + CPU_instr_a1[6:2] == 5'b11001; + assign CPU_is_r_instr_a1 = CPU_instr_a1[6:2] == 5'b01011 || + CPU_instr_a1[6:2] == 5'b10100 || + CPU_instr_a1[6:2] == 5'b01100 || + CPU_instr_a1[6:2] == 5'b01101; + assign CPU_is_b_instr_a1 = CPU_instr_a1[6:2] == 5'b11000; + assign CPU_is_u_instr_a1 = CPU_instr_a1[6:2] == 5'b00101 || + CPU_instr_a1[6:2] == 5'b01101; + assign CPU_is_s_instr_a1 = CPU_instr_a1[6:2] == 5'b01000 || + CPU_instr_a1[6:2] == 5'b01001; + assign CPU_is_j_instr_a1 = CPU_instr_a1[6:2] == 5'b11011; + + assign CPU_imm_a1[31:0] = CPU_is_i_instr_a1 ? { {21{CPU_instr_a1[31]}} , CPU_instr_a1[30:20] } : + CPU_is_s_instr_a1 ? { {21{CPU_instr_a1[31]}} , CPU_instr_a1[30:25] , CPU_instr_a1[11:8] , CPU_instr_a1[7] } : + CPU_is_b_instr_a1 ? { {20{CPU_instr_a1[31]}} , CPU_instr_a1[7] , CPU_instr_a1[30:25] , CPU_instr_a1[11:8] , 1'b0} : + CPU_is_u_instr_a1 ? { CPU_instr_a1[31:12] , 12'b0} : + CPU_is_j_instr_a1 ? { {12{CPU_instr_a1[31]}} , CPU_instr_a1[19:12] , CPU_instr_a1[20] , CPU_instr_a1[30:21] , 1'b0} : 32'b0; + + assign CPU_rs2_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1; + assign CPU_rs1_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1 || CPU_is_i_instr_a1; + assign CPU_rd_valid_a1 = CPU_is_r_instr_a1 || CPU_is_i_instr_a1 || CPU_is_u_instr_a1 || CPU_is_j_instr_a1; + assign CPU_funct3_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1 || CPU_is_i_instr_a1; + assign CPU_funct7_valid_a1 = CPU_is_r_instr_a1; + + //_?$rs2_valid + assign CPU_rs2_a1[4:0] = CPU_instr_a1[24:20]; + //_?$rs1_valid + assign CPU_rs1_a1[4:0] = CPU_instr_a1[19:15]; + //_?$rd_valid + assign CPU_rd_a1[4:0] = CPU_instr_a1[11:7]; + //_?$funct3_valid + assign CPU_funct3_a1[2:0] = CPU_instr_a1[14:12]; + //_?$funct7_valid + assign CPU_funct7_a1[6:0] = CPU_instr_a1[31:25]; + + assign CPU_opcode_a1[6:0] = CPU_instr_a1[6:0]; + + assign CPU_dec_bits_a1[10:0] = {CPU_funct7_a1[5],CPU_funct3_a1,CPU_opcode_a1}; + + // Branch Instruction + assign CPU_is_beq_a1 = CPU_dec_bits_a1[9:0] == 10'b000_1100011; + assign CPU_is_bne_a1 = CPU_dec_bits_a1[9:0] == 10'b001_1100011; + assign CPU_is_blt_a1 = CPU_dec_bits_a1[9:0] == 10'b100_1100011; + assign CPU_is_bge_a1 = CPU_dec_bits_a1[9:0] == 10'b101_1100011; + assign CPU_is_bltu_a1 = CPU_dec_bits_a1[9:0] == 10'b110_1100011; + assign CPU_is_bgeu_a1 = CPU_dec_bits_a1[9:0] == 10'b111_1100011; + + // Arithmetic Instruction + assign CPU_is_add_a1 = CPU_dec_bits_a1 == 11'b0_000_0110011; + assign CPU_is_addi_a1 = CPU_dec_bits_a1[9:0] == 10'b000_0010011; + assign CPU_is_or_a1 = CPU_dec_bits_a1 == 11'b0_110_0110011; + assign CPU_is_ori_a1 = CPU_dec_bits_a1[9:0] == 10'b110_0010011; + assign CPU_is_xor_a1 = CPU_dec_bits_a1 == 11'b0_100_0110011; + assign CPU_is_xori_a1 = CPU_dec_bits_a1[9:0] == 10'b100_0010011; + assign CPU_is_and_a1 = CPU_dec_bits_a1 == 11'b0_111_0110011; + assign CPU_is_andi_a1 = CPU_dec_bits_a1[9:0] == 10'b111_0010011; + assign CPU_is_sub_a1 = CPU_dec_bits_a1 == 11'b1_000_0110011; + assign CPU_is_slti_a1 = CPU_dec_bits_a1[9:0] == 10'b010_0010011; + assign CPU_is_sltiu_a1 = CPU_dec_bits_a1[9:0] == 10'b011_0010011; + assign CPU_is_slli_a1 = CPU_dec_bits_a1 == 11'b0_001_0010011; + assign CPU_is_srli_a1 = CPU_dec_bits_a1 == 11'b0_101_0010011; + assign CPU_is_srai_a1 = CPU_dec_bits_a1 == 11'b1_101_0010011; + assign CPU_is_sll_a1 = CPU_dec_bits_a1 == 11'b0_001_0110011; + assign CPU_is_slt_a1 = CPU_dec_bits_a1 == 11'b0_010_0110011; + assign CPU_is_sltu_a1 = CPU_dec_bits_a1 == 11'b0_011_0110011; + assign CPU_is_srl_a1 = CPU_dec_bits_a1 == 11'b0_101_0110011; + assign CPU_is_sra_a1 = CPU_dec_bits_a1 == 11'b1_101_0110011; + + // Load Instruction + assign CPU_is_load_a1 = CPU_dec_bits_a1[6:0] == 7'b0000011; + + // Store Instruction + assign CPU_is_sb_a1 = CPU_dec_bits_a1[9:0] == 10'b000_0100011; + assign CPU_is_sh_a1 = CPU_dec_bits_a1[9:0] == 10'b001_0100011; + assign CPU_is_sw_a1 = CPU_dec_bits_a1[9:0] == 10'b010_0100011; + + // Jump Instruction + assign CPU_is_lui_a1 = CPU_dec_bits_a1[6:0] == 7'b0110111; + assign CPU_is_auipc_a1 = CPU_dec_bits_a1[6:0] == 7'b0010111; + assign CPU_is_jal_a1 = CPU_dec_bits_a1[6:0] == 7'b1101111; + assign CPU_is_jalr_a1 = CPU_dec_bits_a1[9:0] == 10'b000_1100111; + + assign CPU_is_jump_a1 = CPU_is_jal_a1 || CPU_is_jalr_a1; + + //_@2 + // Register File Read + assign CPU_rf_rd_en1_a2 = CPU_rs1_valid_a2; + //_?$rf_rd_en1 + assign CPU_rf_rd_index1_a2[4:0] = CPU_rs1_a2[4:0]; + + assign CPU_rf_rd_en2_a2 = CPU_rs2_valid_a2; + //_?$rf_rd_en2 + assign CPU_rf_rd_index2_a2[4:0] = CPU_rs2_a2[4:0]; + + // Branch Target PC + assign CPU_br_tgt_pc_a2[31:0] = CPU_pc_a2 + CPU_imm_a2; + + // Jump Target PC + assign CPU_jalr_tgt_pc_a2[31:0] = CPU_src1_value_a2 + CPU_imm_a2; + + // Input signals to ALU + assign CPU_src1_value_a2[31:0] = ((CPU_rd_a3 == CPU_rs1_a2) && CPU_rf_wr_en_a3) ? CPU_result_a3 : CPU_rf_rd_data1_a2[31:0]; + assign CPU_src2_value_a2[31:0] = ((CPU_rd_a3 == CPU_rs2_a2) && CPU_rf_wr_en_a3) ? CPU_result_a3 : CPU_rf_rd_data2_a2[31:0]; + + //_@3 + + // ALU + assign CPU_sltu_result_a3 = CPU_src1_value_a3 < CPU_src2_value_a3 ; + assign CPU_sltiu_result_a3 = CPU_src1_value_a3 < CPU_imm_a3 ; + + assign CPU_result_a3[31:0] = CPU_is_addi_a3 ? CPU_src1_value_a3 + CPU_imm_a3 : + CPU_is_add_a3 ? CPU_src1_value_a3 + CPU_src2_value_a3 : + CPU_is_or_a3 ? CPU_src1_value_a3 | CPU_src2_value_a3 : + CPU_is_ori_a3 ? CPU_src1_value_a3 | CPU_imm_a3 : + CPU_is_xor_a3 ? CPU_src1_value_a3 ^ CPU_src2_value_a3 : + CPU_is_xori_a3 ? CPU_src1_value_a3 ^ CPU_imm_a3 : + CPU_is_and_a3 ? CPU_src1_value_a3 & CPU_src2_value_a3 : + CPU_is_andi_a3 ? CPU_src1_value_a3 & CPU_imm_a3 : + CPU_is_sub_a3 ? CPU_src1_value_a3 - CPU_src2_value_a3 : + CPU_is_slti_a3 ? ((CPU_src1_value_a3[31] == CPU_imm_a3[31]) ? CPU_sltiu_result_a3 : {31'b0,CPU_src1_value_a3[31]}) : + CPU_is_sltiu_a3 ? CPU_sltiu_result_a3 : + CPU_is_slli_a3 ? CPU_src1_value_a3 << CPU_imm_a3[5:0] : + CPU_is_srli_a3 ? CPU_src1_value_a3 >> CPU_imm_a3[5:0] : + CPU_is_srai_a3 ? ({{32{CPU_src1_value_a3[31]}}, CPU_src1_value_a3} >> CPU_imm_a3[4:0]) : + CPU_is_sll_a3 ? CPU_src1_value_a3 << CPU_src2_value_a3[4:0] : + CPU_is_slt_a3 ? ((CPU_src1_value_a3[31] == CPU_src2_value_a3[31]) ? CPU_sltu_result_a3 : {31'b0,CPU_src1_value_a3[31]}) : + CPU_is_sltu_a3 ? CPU_sltu_result_a3 : + CPU_is_srl_a3 ? CPU_src1_value_a3 >> CPU_src2_value_a3[5:0] : + CPU_is_sra_a3 ? ({{32{CPU_src1_value_a3[31]}}, CPU_src1_value_a3} >> CPU_src2_value_a3[4:0]) : + CPU_is_lui_a3 ? ({CPU_imm_a3[31:12], 12'b0}) : + CPU_is_auipc_a3 ? CPU_pc_a3 + CPU_imm_a3 : + CPU_is_jal_a3 ? CPU_pc_a3 + 4 : + CPU_is_jalr_a3 ? CPU_pc_a3 + 4 : + (CPU_is_load_a3 || CPU_is_s_instr_a3) ? CPU_src1_value_a3 + CPU_imm_a3 : 32'bx; + + // Register File Write + assign CPU_rf_wr_en_a3 = (CPU_rd_valid_a3 && CPU_valid_a3 && CPU_rd_a3 != 5'b0) || CPU_valid_load_a5; + //_?$rf_wr_en + assign CPU_rf_wr_index_a3[4:0] = !CPU_valid_a3 ? CPU_rd_a5[4:0] : CPU_rd_a3[4:0]; + + assign CPU_rf_wr_data_a3[31:0] = !CPU_valid_a3 ? CPU_ld_data_a5[31:0] : CPU_result_a3[31:0]; + + // Branch + assign CPU_taken_br_a3 = CPU_is_beq_a3 ? (CPU_src1_value_a3 == CPU_src2_value_a3) : + CPU_is_bne_a3 ? (CPU_src1_value_a3 != CPU_src2_value_a3) : + CPU_is_blt_a3 ? ((CPU_src1_value_a3 < CPU_src2_value_a3) ^ (CPU_src1_value_a3[31] != CPU_src2_value_a3[31])) : + CPU_is_bge_a3 ? ((CPU_src1_value_a3 >= CPU_src2_value_a3) ^ (CPU_src1_value_a3[31] != CPU_src2_value_a3[31])) : + CPU_is_bltu_a3 ? (CPU_src1_value_a3 < CPU_src2_value_a3) : + CPU_is_bgeu_a3 ? (CPU_src1_value_a3 >= CPU_src2_value_a3) : 1'b0; + + assign CPU_valid_taken_br_a3 = CPU_valid_a3 && CPU_taken_br_a3; + + // Load + assign CPU_valid_load_a3 = CPU_valid_a3 && CPU_is_load_a3; + assign CPU_valid_a3 = !(CPU_valid_taken_br_a4 || CPU_valid_taken_br_a5 || CPU_valid_load_a4 || CPU_valid_load_a5 || CPU_valid_jump_a4 || CPU_valid_jump_a5); + + // Jump + assign CPU_valid_jump_a3 = CPU_valid_a3 && CPU_is_jump_a3; + + //_@4 + assign CPU_dmem_rd_en_a4 = CPU_valid_load_a4; + assign CPU_dmem_wr_en_a4 = CPU_valid_a4 && CPU_is_s_instr_a4; + assign CPU_dmem_addr_a4[3:0] = CPU_result_a4[5:2]; + assign CPU_dmem_wr_data_a4[31:0] = CPU_src2_value_a4[31:0]; + + //_@5 + assign CPU_ld_data_a5[31:0] = CPU_dmem_rd_data_a5[31:0]; + + // Note: Because of the magic we are using for visualisation, if visualisation is enabled below, + // be sure to avoid having unassigned signals (which you might be using for random inputs) + // other than those specifically expected in the labs. You'll get strange errors for these. + + `BOGUS_USE(CPU_is_beq_a5 CPU_is_bne_a5 CPU_is_blt_a5 CPU_is_bge_a5 CPU_is_bltu_a5 CPU_is_bgeu_a5) + `BOGUS_USE(CPU_is_sb_a5 CPU_is_sh_a5 CPU_is_sw_a5) + // Assert these to end simulation (before Makerchip cycle limit). + /*SV_plus*/ + always @ (posedge CLK) begin + OUT = CPU_Xreg_value_a5[17]; + end + + // Macro instantiations for: + // o instruction memory + // o register file + // o data memory + // o CPU visualization + //_|cpu + // m4+imem(@1) // Args: (read stage) + //_\source /raw.githubusercontent.com/shivanishah269/riscvcore/master/FPGAImplementation/riscvshelllib.tlv 31 // Instantiated from rvmyth.tlv, 226 as: m4+rf(@2, @3) + // Reg File + //_@3 + for (xreg = 0; xreg <= 31; xreg=xreg+1) begin : L1_CPU_Xreg //_/xreg + + // For $wr. + wire L1_wr_a3; + + assign L1_wr_a3 = CPU_rf_wr_en_a3 && (CPU_rf_wr_index_a3 != 5'b0) && (CPU_rf_wr_index_a3 == xreg); + assign CPU_Xreg_value_a3[xreg][31:0] = CPU_reset_a3 ? xreg : + L1_wr_a3 ? CPU_rf_wr_data_a3 : + CPU_Xreg_value_a4[xreg][31:0]; + end + //_@2 + //_?$rf_rd_en1 + assign CPU_rf_rd_data1_a2[31:0] = CPU_Xreg_value_a4[CPU_rf_rd_index1_a2]; + //_?$rf_rd_en2 + assign CPU_rf_rd_data2_a2[31:0] = CPU_Xreg_value_a4[CPU_rf_rd_index2_a2]; + `BOGUS_USE(CPU_rf_rd_data1_a2 CPU_rf_rd_data2_a2) + //_\end_source // Args: (read stage, write stage) - if equal, no register bypass is required + //_\source /raw.githubusercontent.com/shivanishah269/riscvcore/master/FPGAImplementation/riscvshelllib.tlv 48 // Instantiated from rvmyth.tlv, 227 as: m4+dmem(@4) + // Data Memory + //_@4 + for (dmem = 0; dmem <= 15; dmem=dmem+1) begin : L1_CPU_Dmem //_/dmem + + // For $wr. + wire L1_wr_a4; + + assign L1_wr_a4 = CPU_dmem_wr_en_a4 && (CPU_dmem_addr_a4 == dmem); + assign CPU_Dmem_value_a4[dmem][31:0] = CPU_reset_a4 ? dmem : + L1_wr_a4 ? CPU_dmem_wr_data_a4 : + CPU_Dmem_value_a5[dmem][31:0]; + + end + //_?$dmem_rd_en + assign CPU_dmem_rd_data_a4[31:0] = CPU_Dmem_value_a5[CPU_dmem_addr_a4]; + //`BOGUS_USE($dmem_rd_data) + //_\end_source // Args: (read/write stage) +endgenerate + +//_\SV + + endmodule
diff --git a/verilog/gl/sram_32_256_sky130A.v b/verilog/gl/sram_32_256_sky130A.v new file mode 100644 index 0000000..d45d17e --- /dev/null +++ b/verilog/gl/sram_32_256_sky130A.v
@@ -0,0 +1,72 @@ +// OpenRAM SRAM model +// Words: 256 +// Word size: 32 + +module sram_32_256_sky130A( +`ifdef USE_POWER_PINS + vccd1, + vssd1, +`endif +// Port 0: RW + clk0,csb0,web0,addr0,din0,dout0 + ); + + parameter DATA_WIDTH = 32 ; + parameter ADDR_WIDTH = 8 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. + parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary + +`ifdef USE_POWER_PINS + inout vccd1; + inout vssd1; +`endif + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [ADDR_WIDTH-1:0] addr0; + input [DATA_WIDTH-1:0] din0; + output [DATA_WIDTH-1:0] dout0; + + reg csb0_reg; + reg web0_reg; + reg [ADDR_WIDTH-1:0] addr0_reg; + reg [DATA_WIDTH-1:0] din0_reg; + reg [DATA_WIDTH-1:0] dout0; + + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + addr0_reg = addr0; + din0_reg = din0; + #(T_HOLD) dout0 = 32'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) + $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); + if ( !csb0_reg && !web0_reg && VERBOSE ) + $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); + end + +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) begin + mem[addr0_reg][31:0] = din0_reg[31:0]; + end + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + dout0 <= #(DELAY) mem[addr0_reg]; + end + +endmodule
diff --git a/verilog/include/rvmyth_gen.v b/verilog/include/rvmyth_gen.v new file mode 100644 index 0000000..0a70a27 --- /dev/null +++ b/verilog/include/rvmyth_gen.v
@@ -0,0 +1,706 @@ +// Generated by SandPiper(TM) 1.11-2021/01/28-beta from Redwood EDA. +// Redwood EDA does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality. + + +`include "sandpiper_gen.vh" + + +genvar dmem, xreg; + + +// +// Signals declared top-level. +// + +// For |cpu$br_tgt_pc. +wire [31:0] CPU_br_tgt_pc_a2; +reg [31:0] CPU_br_tgt_pc_a3; + +// For |cpu$dec_bits. +wire [10:0] CPU_dec_bits_a1; + +// For |cpu$dmem_addr. +wire [3:0] CPU_dmem_addr_a4; + +// For |cpu$dmem_rd_data. +wire [31:0] CPU_dmem_rd_data_a4; +reg [31:0] CPU_dmem_rd_data_a5; + +// For |cpu$dmem_rd_en. +wire CPU_dmem_rd_en_a4; + +// For |cpu$dmem_wr_data. +wire [31:0] CPU_dmem_wr_data_a4; + +// For |cpu$dmem_wr_en. +wire CPU_dmem_wr_en_a4; + +// For |cpu$funct3. +wire [2:0] CPU_funct3_a1; + +// For |cpu$funct3_valid. +wire CPU_funct3_valid_a1; + +// For |cpu$funct7. +wire [6:0] CPU_funct7_a1; + +// For |cpu$funct7_valid. +wire CPU_funct7_valid_a1; + +// For |cpu$imm. +wire [31:0] CPU_imm_a1; +reg [31:0] CPU_imm_a2, + CPU_imm_a3; + +// For |cpu$inc_pc. +wire [31:0] CPU_inc_pc_a1; +reg [31:0] CPU_inc_pc_a2, + CPU_inc_pc_a3; + +// For |cpu$instr. +wire [31:0] CPU_instr_a1; + +// For |cpu$is_add. +wire CPU_is_add_a1; +reg CPU_is_add_a2, + CPU_is_add_a3; + +// For |cpu$is_addi. +wire CPU_is_addi_a1; +reg CPU_is_addi_a2, + CPU_is_addi_a3; + +// For |cpu$is_and. +wire CPU_is_and_a1; +reg CPU_is_and_a2, + CPU_is_and_a3; + +// For |cpu$is_andi. +wire CPU_is_andi_a1; +reg CPU_is_andi_a2, + CPU_is_andi_a3; + +// For |cpu$is_auipc. +wire CPU_is_auipc_a1; +reg CPU_is_auipc_a2, + CPU_is_auipc_a3; + +// For |cpu$is_b_instr. +wire CPU_is_b_instr_a1; + +// For |cpu$is_beq. +wire CPU_is_beq_a1; +reg CPU_is_beq_a2, + CPU_is_beq_a3, + CPU_is_beq_a4, + CPU_is_beq_a5; + +// For |cpu$is_bge. +wire CPU_is_bge_a1; +reg CPU_is_bge_a2, + CPU_is_bge_a3, + CPU_is_bge_a4, + CPU_is_bge_a5; + +// For |cpu$is_bgeu. +wire CPU_is_bgeu_a1; +reg CPU_is_bgeu_a2, + CPU_is_bgeu_a3, + CPU_is_bgeu_a4, + CPU_is_bgeu_a5; + +// For |cpu$is_blt. +wire CPU_is_blt_a1; +reg CPU_is_blt_a2, + CPU_is_blt_a3, + CPU_is_blt_a4, + CPU_is_blt_a5; + +// For |cpu$is_bltu. +wire CPU_is_bltu_a1; +reg CPU_is_bltu_a2, + CPU_is_bltu_a3, + CPU_is_bltu_a4, + CPU_is_bltu_a5; + +// For |cpu$is_bne. +wire CPU_is_bne_a1; +reg CPU_is_bne_a2, + CPU_is_bne_a3, + CPU_is_bne_a4, + CPU_is_bne_a5; + +// For |cpu$is_i_instr. +wire CPU_is_i_instr_a1; + +// For |cpu$is_j_instr. +wire CPU_is_j_instr_a1; + +// For |cpu$is_jal. +wire CPU_is_jal_a1; +reg CPU_is_jal_a2, + CPU_is_jal_a3; + +// For |cpu$is_jalr. +wire CPU_is_jalr_a1; +reg CPU_is_jalr_a2, + CPU_is_jalr_a3; + +// For |cpu$is_jump. +wire CPU_is_jump_a1; +reg CPU_is_jump_a2, + CPU_is_jump_a3; + +// For |cpu$is_load. +wire CPU_is_load_a1; +reg CPU_is_load_a2, + CPU_is_load_a3; + +// For |cpu$is_lui. +wire CPU_is_lui_a1; +reg CPU_is_lui_a2, + CPU_is_lui_a3; + +// For |cpu$is_or. +wire CPU_is_or_a1; +reg CPU_is_or_a2, + CPU_is_or_a3; + +// For |cpu$is_ori. +wire CPU_is_ori_a1; +reg CPU_is_ori_a2, + CPU_is_ori_a3; + +// For |cpu$is_r_instr. +wire CPU_is_r_instr_a1; + +// For |cpu$is_s_instr. +wire CPU_is_s_instr_a1; +reg CPU_is_s_instr_a2, + CPU_is_s_instr_a3, + CPU_is_s_instr_a4; + +// For |cpu$is_sb. +wire CPU_is_sb_a1; +reg CPU_is_sb_a2, + CPU_is_sb_a3, + CPU_is_sb_a4, + CPU_is_sb_a5; + +// For |cpu$is_sh. +wire CPU_is_sh_a1; +reg CPU_is_sh_a2, + CPU_is_sh_a3, + CPU_is_sh_a4, + CPU_is_sh_a5; + +// For |cpu$is_sll. +wire CPU_is_sll_a1; +reg CPU_is_sll_a2, + CPU_is_sll_a3; + +// For |cpu$is_slli. +wire CPU_is_slli_a1; +reg CPU_is_slli_a2, + CPU_is_slli_a3; + +// For |cpu$is_slt. +wire CPU_is_slt_a1; +reg CPU_is_slt_a2, + CPU_is_slt_a3; + +// For |cpu$is_slti. +wire CPU_is_slti_a1; +reg CPU_is_slti_a2, + CPU_is_slti_a3; + +// For |cpu$is_sltiu. +wire CPU_is_sltiu_a1; +reg CPU_is_sltiu_a2, + CPU_is_sltiu_a3; + +// For |cpu$is_sltu. +wire CPU_is_sltu_a1; +reg CPU_is_sltu_a2, + CPU_is_sltu_a3; + +// For |cpu$is_sra. +wire CPU_is_sra_a1; +reg CPU_is_sra_a2, + CPU_is_sra_a3; + +// For |cpu$is_srai. +wire CPU_is_srai_a1; +reg CPU_is_srai_a2, + CPU_is_srai_a3; + +// For |cpu$is_srl. +wire CPU_is_srl_a1; +reg CPU_is_srl_a2, + CPU_is_srl_a3; + +// For |cpu$is_srli. +wire CPU_is_srli_a1; +reg CPU_is_srli_a2, + CPU_is_srli_a3; + +// For |cpu$is_sub. +wire CPU_is_sub_a1; +reg CPU_is_sub_a2, + CPU_is_sub_a3; + +// For |cpu$is_sw. +wire CPU_is_sw_a1; +reg CPU_is_sw_a2, + CPU_is_sw_a3, + CPU_is_sw_a4, + CPU_is_sw_a5; + +// For |cpu$is_u_instr. +wire CPU_is_u_instr_a1; + +// For |cpu$is_xor. +wire CPU_is_xor_a1; +reg CPU_is_xor_a2, + CPU_is_xor_a3; + +// For |cpu$is_xori. +wire CPU_is_xori_a1; +reg CPU_is_xori_a2, + CPU_is_xori_a3; + +// For |cpu$jalr_tgt_pc. +wire [31:0] CPU_jalr_tgt_pc_a2; +reg [31:0] CPU_jalr_tgt_pc_a3; + +// For |cpu$ld_data. +wire [31:0] CPU_ld_data_a5; + +// For |cpu$opcode. +wire [6:0] CPU_opcode_a1; + +// For |cpu$pc. +wire [31:0] CPU_pc_a0; +reg [31:0] CPU_pc_a1, + CPU_pc_a2, + CPU_pc_a3; + +// For |cpu$rd. +wire [4:0] CPU_rd_a1; +reg [4:0] CPU_rd_a2, + CPU_rd_a3, + CPU_rd_a4, + CPU_rd_a5; + +// For |cpu$rd_valid. +wire CPU_rd_valid_a1; +reg CPU_rd_valid_a2, + CPU_rd_valid_a3, + CPU_rd_valid_a4; + +// For |cpu$reset. +wire CPU_reset_a0; +reg CPU_reset_a1, + CPU_reset_a2, + CPU_reset_a3, + CPU_reset_a4; + +// For |cpu$result. +wire [31:0] CPU_result_a3; +reg [5:2] CPU_result_a4; + +// For |cpu$rf_rd_data1. +wire [31:0] CPU_rf_rd_data1_a2; + +// For |cpu$rf_rd_data2. +wire [31:0] CPU_rf_rd_data2_a2; + +// For |cpu$rf_rd_en1. +wire CPU_rf_rd_en1_a2; + +// For |cpu$rf_rd_en2. +wire CPU_rf_rd_en2_a2; + +// For |cpu$rf_rd_index1. +wire [4:0] CPU_rf_rd_index1_a2; + +// For |cpu$rf_rd_index2. +wire [4:0] CPU_rf_rd_index2_a2; + +// For |cpu$rf_wr_data. +wire [31:0] CPU_rf_wr_data_a3; + +// For |cpu$rf_wr_en. +wire CPU_rf_wr_en_a3; + +// For |cpu$rf_wr_index. +wire [4:0] CPU_rf_wr_index_a3; + +// For |cpu$rs1. +wire [4:0] CPU_rs1_a1; +reg [4:0] CPU_rs1_a2; + +// For |cpu$rs1_valid. +wire CPU_rs1_valid_a1; +reg CPU_rs1_valid_a2; + +// For |cpu$rs2. +wire [4:0] CPU_rs2_a1; +reg [4:0] CPU_rs2_a2; + +// For |cpu$rs2_valid. +wire CPU_rs2_valid_a1; +reg CPU_rs2_valid_a2; + +// For |cpu$sltiu_result. +wire CPU_sltiu_result_a3; + +// For |cpu$sltu_result. +wire CPU_sltu_result_a3; + +// For |cpu$src1_value. +wire [31:0] CPU_src1_value_a2; +reg [31:0] CPU_src1_value_a3; + +// For |cpu$src2_value. +wire [31:0] CPU_src2_value_a2; +reg [31:0] CPU_src2_value_a3, + CPU_src2_value_a4; + +// For |cpu$taken_br. +wire CPU_taken_br_a3; + +// For |cpu$valid. +wire CPU_valid_a3; +reg CPU_valid_a4; + +// For |cpu$valid_jump. +wire CPU_valid_jump_a3; +reg CPU_valid_jump_a4, + CPU_valid_jump_a5; + +// For |cpu$valid_load. +wire CPU_valid_load_a3; +reg CPU_valid_load_a4, + CPU_valid_load_a5; + +// For |cpu$valid_taken_br. +wire CPU_valid_taken_br_a3; +reg CPU_valid_taken_br_a4, + CPU_valid_taken_br_a5; + +// For |cpu/dmem$value. +wire [31:0] CPU_Dmem_value_a4 [15:0]; +reg [31:0] CPU_Dmem_value_a5 [15:0]; + +// For |cpu/xreg$value. +wire [31:0] CPU_Xreg_value_a3 [31:0]; +reg [31:0] CPU_Xreg_value_a4 [31:0], + CPU_Xreg_value_a5 [31:0]; + + +// +// Scope: |cpu +// + +// Clock signals. +wire clkP_CPU_dmem_rd_en_a5 ; +wire clkP_CPU_rd_valid_a2 ; +wire clkP_CPU_rd_valid_a3 ; +wire clkP_CPU_rd_valid_a4 ; +wire clkP_CPU_rd_valid_a5 ; +wire clkP_CPU_rs1_valid_a2 ; +wire clkP_CPU_rs2_valid_a2 ; + + +generate + + + // + // Scope: |cpu + // + + // For $br_tgt_pc. + always @(posedge clk) CPU_br_tgt_pc_a3[31:0] <= CPU_br_tgt_pc_a2[31:0]; + + // For $dmem_rd_data. + always @(posedge clkP_CPU_dmem_rd_en_a5) CPU_dmem_rd_data_a5[31:0] <= CPU_dmem_rd_data_a4[31:0]; + + // For $imm. + always @(posedge clk) CPU_imm_a2[31:0] <= CPU_imm_a1[31:0]; + always @(posedge clk) CPU_imm_a3[31:0] <= CPU_imm_a2[31:0]; + + // For $inc_pc. + always @(posedge clk) CPU_inc_pc_a2[31:0] <= CPU_inc_pc_a1[31:0]; + always @(posedge clk) CPU_inc_pc_a3[31:0] <= CPU_inc_pc_a2[31:0]; + + // For $is_add. + always @(posedge clk) CPU_is_add_a2 <= CPU_is_add_a1; + always @(posedge clk) CPU_is_add_a3 <= CPU_is_add_a2; + + // For $is_addi. + always @(posedge clk) CPU_is_addi_a2 <= CPU_is_addi_a1; + always @(posedge clk) CPU_is_addi_a3 <= CPU_is_addi_a2; + + // For $is_and. + always @(posedge clk) CPU_is_and_a2 <= CPU_is_and_a1; + always @(posedge clk) CPU_is_and_a3 <= CPU_is_and_a2; + + // For $is_andi. + always @(posedge clk) CPU_is_andi_a2 <= CPU_is_andi_a1; + always @(posedge clk) CPU_is_andi_a3 <= CPU_is_andi_a2; + + // For $is_auipc. + always @(posedge clk) CPU_is_auipc_a2 <= CPU_is_auipc_a1; + always @(posedge clk) CPU_is_auipc_a3 <= CPU_is_auipc_a2; + + // For $is_beq. + always @(posedge clk) CPU_is_beq_a2 <= CPU_is_beq_a1; + always @(posedge clk) CPU_is_beq_a3 <= CPU_is_beq_a2; + always @(posedge clk) CPU_is_beq_a4 <= CPU_is_beq_a3; + always @(posedge clk) CPU_is_beq_a5 <= CPU_is_beq_a4; + + // For $is_bge. + always @(posedge clk) CPU_is_bge_a2 <= CPU_is_bge_a1; + always @(posedge clk) CPU_is_bge_a3 <= CPU_is_bge_a2; + always @(posedge clk) CPU_is_bge_a4 <= CPU_is_bge_a3; + always @(posedge clk) CPU_is_bge_a5 <= CPU_is_bge_a4; + + // For $is_bgeu. + always @(posedge clk) CPU_is_bgeu_a2 <= CPU_is_bgeu_a1; + always @(posedge clk) CPU_is_bgeu_a3 <= CPU_is_bgeu_a2; + always @(posedge clk) CPU_is_bgeu_a4 <= CPU_is_bgeu_a3; + always @(posedge clk) CPU_is_bgeu_a5 <= CPU_is_bgeu_a4; + + // For $is_blt. + always @(posedge clk) CPU_is_blt_a2 <= CPU_is_blt_a1; + always @(posedge clk) CPU_is_blt_a3 <= CPU_is_blt_a2; + always @(posedge clk) CPU_is_blt_a4 <= CPU_is_blt_a3; + always @(posedge clk) CPU_is_blt_a5 <= CPU_is_blt_a4; + + // For $is_bltu. + always @(posedge clk) CPU_is_bltu_a2 <= CPU_is_bltu_a1; + always @(posedge clk) CPU_is_bltu_a3 <= CPU_is_bltu_a2; + always @(posedge clk) CPU_is_bltu_a4 <= CPU_is_bltu_a3; + always @(posedge clk) CPU_is_bltu_a5 <= CPU_is_bltu_a4; + + // For $is_bne. + always @(posedge clk) CPU_is_bne_a2 <= CPU_is_bne_a1; + always @(posedge clk) CPU_is_bne_a3 <= CPU_is_bne_a2; + always @(posedge clk) CPU_is_bne_a4 <= CPU_is_bne_a3; + always @(posedge clk) CPU_is_bne_a5 <= CPU_is_bne_a4; + + // For $is_jal. + always @(posedge clk) CPU_is_jal_a2 <= CPU_is_jal_a1; + always @(posedge clk) CPU_is_jal_a3 <= CPU_is_jal_a2; + + // For $is_jalr. + always @(posedge clk) CPU_is_jalr_a2 <= CPU_is_jalr_a1; + always @(posedge clk) CPU_is_jalr_a3 <= CPU_is_jalr_a2; + + // For $is_jump. + always @(posedge clk) CPU_is_jump_a2 <= CPU_is_jump_a1; + always @(posedge clk) CPU_is_jump_a3 <= CPU_is_jump_a2; + + // For $is_load. + always @(posedge clk) CPU_is_load_a2 <= CPU_is_load_a1; + always @(posedge clk) CPU_is_load_a3 <= CPU_is_load_a2; + + // For $is_lui. + always @(posedge clk) CPU_is_lui_a2 <= CPU_is_lui_a1; + always @(posedge clk) CPU_is_lui_a3 <= CPU_is_lui_a2; + + // For $is_or. + always @(posedge clk) CPU_is_or_a2 <= CPU_is_or_a1; + always @(posedge clk) CPU_is_or_a3 <= CPU_is_or_a2; + + // For $is_ori. + always @(posedge clk) CPU_is_ori_a2 <= CPU_is_ori_a1; + always @(posedge clk) CPU_is_ori_a3 <= CPU_is_ori_a2; + + // For $is_s_instr. + always @(posedge clk) CPU_is_s_instr_a2 <= CPU_is_s_instr_a1; + always @(posedge clk) CPU_is_s_instr_a3 <= CPU_is_s_instr_a2; + always @(posedge clk) CPU_is_s_instr_a4 <= CPU_is_s_instr_a3; + + // For $is_sb. + always @(posedge clk) CPU_is_sb_a2 <= CPU_is_sb_a1; + always @(posedge clk) CPU_is_sb_a3 <= CPU_is_sb_a2; + always @(posedge clk) CPU_is_sb_a4 <= CPU_is_sb_a3; + always @(posedge clk) CPU_is_sb_a5 <= CPU_is_sb_a4; + + // For $is_sh. + always @(posedge clk) CPU_is_sh_a2 <= CPU_is_sh_a1; + always @(posedge clk) CPU_is_sh_a3 <= CPU_is_sh_a2; + always @(posedge clk) CPU_is_sh_a4 <= CPU_is_sh_a3; + always @(posedge clk) CPU_is_sh_a5 <= CPU_is_sh_a4; + + // For $is_sll. + always @(posedge clk) CPU_is_sll_a2 <= CPU_is_sll_a1; + always @(posedge clk) CPU_is_sll_a3 <= CPU_is_sll_a2; + + // For $is_slli. + always @(posedge clk) CPU_is_slli_a2 <= CPU_is_slli_a1; + always @(posedge clk) CPU_is_slli_a3 <= CPU_is_slli_a2; + + // For $is_slt. + always @(posedge clk) CPU_is_slt_a2 <= CPU_is_slt_a1; + always @(posedge clk) CPU_is_slt_a3 <= CPU_is_slt_a2; + + // For $is_slti. + always @(posedge clk) CPU_is_slti_a2 <= CPU_is_slti_a1; + always @(posedge clk) CPU_is_slti_a3 <= CPU_is_slti_a2; + + // For $is_sltiu. + always @(posedge clk) CPU_is_sltiu_a2 <= CPU_is_sltiu_a1; + always @(posedge clk) CPU_is_sltiu_a3 <= CPU_is_sltiu_a2; + + // For $is_sltu. + always @(posedge clk) CPU_is_sltu_a2 <= CPU_is_sltu_a1; + always @(posedge clk) CPU_is_sltu_a3 <= CPU_is_sltu_a2; + + // For $is_sra. + always @(posedge clk) CPU_is_sra_a2 <= CPU_is_sra_a1; + always @(posedge clk) CPU_is_sra_a3 <= CPU_is_sra_a2; + + // For $is_srai. + always @(posedge clk) CPU_is_srai_a2 <= CPU_is_srai_a1; + always @(posedge clk) CPU_is_srai_a3 <= CPU_is_srai_a2; + + // For $is_srl. + always @(posedge clk) CPU_is_srl_a2 <= CPU_is_srl_a1; + always @(posedge clk) CPU_is_srl_a3 <= CPU_is_srl_a2; + + // For $is_srli. + always @(posedge clk) CPU_is_srli_a2 <= CPU_is_srli_a1; + always @(posedge clk) CPU_is_srli_a3 <= CPU_is_srli_a2; + + // For $is_sub. + always @(posedge clk) CPU_is_sub_a2 <= CPU_is_sub_a1; + always @(posedge clk) CPU_is_sub_a3 <= CPU_is_sub_a2; + + // For $is_sw. + always @(posedge clk) CPU_is_sw_a2 <= CPU_is_sw_a1; + always @(posedge clk) CPU_is_sw_a3 <= CPU_is_sw_a2; + always @(posedge clk) CPU_is_sw_a4 <= CPU_is_sw_a3; + always @(posedge clk) CPU_is_sw_a5 <= CPU_is_sw_a4; + + // For $is_xor. + always @(posedge clk) CPU_is_xor_a2 <= CPU_is_xor_a1; + always @(posedge clk) CPU_is_xor_a3 <= CPU_is_xor_a2; + + // For $is_xori. + always @(posedge clk) CPU_is_xori_a2 <= CPU_is_xori_a1; + always @(posedge clk) CPU_is_xori_a3 <= CPU_is_xori_a2; + + // For $jalr_tgt_pc. + always @(posedge clk) CPU_jalr_tgt_pc_a3[31:0] <= CPU_jalr_tgt_pc_a2[31:0]; + + // For $pc. + always @(posedge clk) CPU_pc_a1[31:0] <= CPU_pc_a0[31:0]; + always @(posedge clk) CPU_pc_a2[31:0] <= CPU_pc_a1[31:0]; + always @(posedge clk) CPU_pc_a3[31:0] <= CPU_pc_a2[31:0]; + + // For $rd. + always @(posedge clkP_CPU_rd_valid_a2) CPU_rd_a2[4:0] <= CPU_rd_a1[4:0]; + always @(posedge clkP_CPU_rd_valid_a3) CPU_rd_a3[4:0] <= CPU_rd_a2[4:0]; + always @(posedge clkP_CPU_rd_valid_a4) CPU_rd_a4[4:0] <= CPU_rd_a3[4:0]; + always @(posedge clkP_CPU_rd_valid_a5) CPU_rd_a5[4:0] <= CPU_rd_a4[4:0]; + + // For $rd_valid. + always @(posedge clk) CPU_rd_valid_a2 <= CPU_rd_valid_a1; + always @(posedge clk) CPU_rd_valid_a3 <= CPU_rd_valid_a2; + always @(posedge clk) CPU_rd_valid_a4 <= CPU_rd_valid_a3; + + // For $reset. + always @(posedge clk) CPU_reset_a1 <= CPU_reset_a0; + always @(posedge clk) CPU_reset_a2 <= CPU_reset_a1; + always @(posedge clk) CPU_reset_a3 <= CPU_reset_a2; + always @(posedge clk) CPU_reset_a4 <= CPU_reset_a3; + + // For $result. + always @(posedge clk) CPU_result_a4[5:2] <= CPU_result_a3[5:2]; + + // For $rs1. + always @(posedge clkP_CPU_rs1_valid_a2) CPU_rs1_a2[4:0] <= CPU_rs1_a1[4:0]; + + // For $rs1_valid. + always @(posedge clk) CPU_rs1_valid_a2 <= CPU_rs1_valid_a1; + + // For $rs2. + always @(posedge clkP_CPU_rs2_valid_a2) CPU_rs2_a2[4:0] <= CPU_rs2_a1[4:0]; + + // For $rs2_valid. + always @(posedge clk) CPU_rs2_valid_a2 <= CPU_rs2_valid_a1; + + // For $src1_value. + always @(posedge clk) CPU_src1_value_a3[31:0] <= CPU_src1_value_a2[31:0]; + + // For $src2_value. + always @(posedge clk) CPU_src2_value_a3[31:0] <= CPU_src2_value_a2[31:0]; + always @(posedge clk) CPU_src2_value_a4[31:0] <= CPU_src2_value_a3[31:0]; + + // For $valid. + always @(posedge clk) CPU_valid_a4 <= CPU_valid_a3; + + // For $valid_jump. + always @(posedge clk) CPU_valid_jump_a4 <= CPU_valid_jump_a3; + always @(posedge clk) CPU_valid_jump_a5 <= CPU_valid_jump_a4; + + // For $valid_load. + always @(posedge clk) CPU_valid_load_a4 <= CPU_valid_load_a3; + always @(posedge clk) CPU_valid_load_a5 <= CPU_valid_load_a4; + + // For $valid_taken_br. + always @(posedge clk) CPU_valid_taken_br_a4 <= CPU_valid_taken_br_a3; + always @(posedge clk) CPU_valid_taken_br_a5 <= CPU_valid_taken_br_a4; + + + // + // Scope: /dmem[15:0] + // + for (dmem = 0; dmem <= 15; dmem=dmem+1) begin : L1gen_CPU_Dmem + // For $value. + always @(posedge clk) CPU_Dmem_value_a5[dmem][31:0] <= CPU_Dmem_value_a4[dmem][31:0]; + + end + + // + // Scope: /xreg[31:0] + // + for (xreg = 0; xreg <= 31; xreg=xreg+1) begin : L1gen_CPU_Xreg + // For $value. + always @(posedge clk) CPU_Xreg_value_a4[xreg][31:0] <= CPU_Xreg_value_a3[xreg][31:0]; + always @(posedge clk) CPU_Xreg_value_a5[xreg][31:0] <= CPU_Xreg_value_a4[xreg][31:0]; + + end + + + +endgenerate + + + +// +// Gated clocks. +// + +generate + + + + // + // Scope: |cpu + // + + clk_gate gen_clkP_CPU_dmem_rd_en_a5(clkP_CPU_dmem_rd_en_a5, clk, 1'b1, CPU_dmem_rd_en_a4, 1'b0); + clk_gate gen_clkP_CPU_rd_valid_a2(clkP_CPU_rd_valid_a2, clk, 1'b1, CPU_rd_valid_a1, 1'b0); + clk_gate gen_clkP_CPU_rd_valid_a3(clkP_CPU_rd_valid_a3, clk, 1'b1, CPU_rd_valid_a2, 1'b0); + clk_gate gen_clkP_CPU_rd_valid_a4(clkP_CPU_rd_valid_a4, clk, 1'b1, CPU_rd_valid_a3, 1'b0); + clk_gate gen_clkP_CPU_rd_valid_a5(clkP_CPU_rd_valid_a5, clk, 1'b1, CPU_rd_valid_a4, 1'b0); + clk_gate gen_clkP_CPU_rs1_valid_a2(clkP_CPU_rs1_valid_a2, clk, 1'b1, CPU_rs1_valid_a1, 1'b0); + clk_gate gen_clkP_CPU_rs2_valid_a2(clkP_CPU_rs2_valid_a2, clk, 1'b1, CPU_rs2_valid_a1, 1'b0); + + + +endgenerate
diff --git a/verilog/include/sandpiper.vh b/verilog/include/sandpiper.vh new file mode 100644 index 0000000..26d3f19 --- /dev/null +++ b/verilog/include/sandpiper.vh
@@ -0,0 +1,71 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Project-independent SandPiper header file. + +`ifndef SANDPIPER_VH +`define SANDPIPER_VH + + +// Note, these have no SP prefix, so collisions are possible. + + +`ifdef WHEN + // Make sure user definition does not collide. + !!!ERROR: WHEN macro already defined +`else + `ifdef SP_PHYS + // Phys compilation disabled X-injection. + `define WHEN(valid_sig) + `else + // Inject X. + `define WHEN(valid_sig) !valid_sig ? 'x : + `endif +`endif + + +// SandPiper does not generate set/reset flops. Reset is implemented as combinational +// logic, and it is up to synthesis to infer set/reset flops when possible. +//`ifdef RESET +// // Make sure user definition does not collide. +// !!!ERROR: RESET macro already defined +//`else +// `define RESET(i, reset) ((reset) ? '0 : i) +//`endif +// +//`ifdef SET +// // Make sure user definition does not collide. +// !!!ERROR: SET macro already defined +//`else +// `define SET(i, set) ((set) ? '1 : i) +//`endif + +// Since SandPiper required use of all signals, this is useful to create a +// bogus use and keep SandPiper happy when a signal, by intent, has no uses. +`define BOGUS_USE(ignore) + +`endif // SANDPIPER_VH
diff --git a/verilog/include/sandpiper_gen.vh b/verilog/include/sandpiper_gen.vh new file mode 100644 index 0000000..d063661 --- /dev/null +++ b/verilog/include/sandpiper_gen.vh
@@ -0,0 +1,4 @@ +// This just verifies that sandpiper.vh has been included. +`ifndef SANDPIPER_VH + !!!ERROR: SandPiper project's sp_<proj>.vh file must include sandpiper.vh. +`endif
diff --git a/verilog/include/sp_default.vh b/verilog/include/sp_default.vh new file mode 100644 index 0000000..a733969 --- /dev/null +++ b/verilog/include/sp_default.vh
@@ -0,0 +1,8 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +`endif // SP_DEFAULT
diff --git a/verilog/include/sp_verilog.vh b/verilog/include/sp_verilog.vh new file mode 100644 index 0000000..0c28412 --- /dev/null +++ b/verilog/include/sp_verilog.vh
@@ -0,0 +1,65 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +// Latch macros. Inject 'x in simulation for clk === 'x. + +// A-phase latch. +`ifdef SP_PHYS +`define TLV_LATCH(in, out, clk) \ +always @ (in, clk) begin \ + if (clk === 1'b1) \ + out <= in; \ + else if (clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_LATCH(in, out, clk) always @ (in, clk) if (clk == 1'b1) out <= in; +`endif // SP_PHYS + +// B-phase latch. +`ifdef SP_PHYS +`define TLV_BLATCH(out, in, clk) \ +always @ (in, clk) begin \ + if (!clk === 1'b1) \ + out <= in; \ + else if (!clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_BLATCH(out, in, clk) always @ (in, clk) if (!clk == 1'b1) out <= in; +`endif // SP_PHYS + + + +`endif // SP_DEFAULT
diff --git a/verilog/rtl/clk_gate.v b/verilog/rtl/clk_gate.v new file mode 100644 index 0000000..6df5b7d --- /dev/null +++ b/verilog/rtl/clk_gate.v
@@ -0,0 +1,36 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +`include "sp_verilog.vh" + + +// Clock gate module used by SandPiper default project. + +module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override); + + assign gated_clk = free_clk; +endmodule
diff --git a/verilog/rtl/rvmyth.v b/verilog/rtl/rvmyth.v new file mode 100644 index 0000000..9e96890 --- /dev/null +++ b/verilog/rtl/rvmyth.v
@@ -0,0 +1,269 @@ +//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta +`include "sp_verilog.vh" //_\SV + // Included URL: "https://raw.githubusercontent.com/shivanishah269/risc-v-core/master/FPGA_Implementation/riscv_shell_lib.tlv"// Included URL: "https://raw.githubusercontent.com/stevehoover/warp-v_includes/2d6d36baa4d2bc62321f982f78c8fe1456641a43/risc-v_defs.tlv" + + module rvmyth ( + output reg [9:0] OUT, + input CLK, + input reset, + + output [7:0] imem_addr, + input [31:0] imem_data + ); + + wire clk = CLK; + +`include "rvmyth_gen.v" +generate //_\TLV + //_|cpu + //_@0 + assign CPU_reset_a0 = reset; + + //Fetch + // Next PC + assign CPU_pc_a0[31:0] = (CPU_reset_a1) ? 32'd0 : + (CPU_valid_taken_br_a3) ? CPU_br_tgt_pc_a3 : + (CPU_valid_load_a3) ? CPU_inc_pc_a3 : + (CPU_valid_jump_a3 && CPU_is_jal_a3) ? CPU_br_tgt_pc_a3 : + (CPU_valid_jump_a3 && CPU_is_jalr_a3) ? CPU_jalr_tgt_pc_a3 : CPU_inc_pc_a1; + + //_@1 + assign imem_addr = CPU_pc_a0[9:2]; + assign CPU_instr_a1[31:0] = imem_data; + assign CPU_inc_pc_a1[31:0] = CPU_pc_a1 + 32'd4; + + // Decode + assign CPU_is_i_instr_a1 = CPU_instr_a1[6:2] == 5'b00000 || + CPU_instr_a1[6:2] == 5'b00001 || + CPU_instr_a1[6:2] == 5'b00100 || + CPU_instr_a1[6:2] == 5'b00110 || + CPU_instr_a1[6:2] == 5'b11001; + assign CPU_is_r_instr_a1 = CPU_instr_a1[6:2] == 5'b01011 || + CPU_instr_a1[6:2] == 5'b10100 || + CPU_instr_a1[6:2] == 5'b01100 || + CPU_instr_a1[6:2] == 5'b01101; + assign CPU_is_b_instr_a1 = CPU_instr_a1[6:2] == 5'b11000; + assign CPU_is_u_instr_a1 = CPU_instr_a1[6:2] == 5'b00101 || + CPU_instr_a1[6:2] == 5'b01101; + assign CPU_is_s_instr_a1 = CPU_instr_a1[6:2] == 5'b01000 || + CPU_instr_a1[6:2] == 5'b01001; + assign CPU_is_j_instr_a1 = CPU_instr_a1[6:2] == 5'b11011; + + assign CPU_imm_a1[31:0] = CPU_is_i_instr_a1 ? { {21{CPU_instr_a1[31]}} , CPU_instr_a1[30:20] } : + CPU_is_s_instr_a1 ? { {21{CPU_instr_a1[31]}} , CPU_instr_a1[30:25] , CPU_instr_a1[11:8] , CPU_instr_a1[7] } : + CPU_is_b_instr_a1 ? { {20{CPU_instr_a1[31]}} , CPU_instr_a1[7] , CPU_instr_a1[30:25] , CPU_instr_a1[11:8] , 1'b0} : + CPU_is_u_instr_a1 ? { CPU_instr_a1[31:12] , 12'b0} : + CPU_is_j_instr_a1 ? { {12{CPU_instr_a1[31]}} , CPU_instr_a1[19:12] , CPU_instr_a1[20] , CPU_instr_a1[30:21] , 1'b0} : 32'b0; + + assign CPU_rs2_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1; + assign CPU_rs1_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1 || CPU_is_i_instr_a1; + assign CPU_rd_valid_a1 = CPU_is_r_instr_a1 || CPU_is_i_instr_a1 || CPU_is_u_instr_a1 || CPU_is_j_instr_a1; + assign CPU_funct3_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1 || CPU_is_i_instr_a1; + assign CPU_funct7_valid_a1 = CPU_is_r_instr_a1; + + //_?$rs2_valid + assign CPU_rs2_a1[4:0] = CPU_instr_a1[24:20]; + //_?$rs1_valid + assign CPU_rs1_a1[4:0] = CPU_instr_a1[19:15]; + //_?$rd_valid + assign CPU_rd_a1[4:0] = CPU_instr_a1[11:7]; + //_?$funct3_valid + assign CPU_funct3_a1[2:0] = CPU_instr_a1[14:12]; + //_?$funct7_valid + assign CPU_funct7_a1[6:0] = CPU_instr_a1[31:25]; + + assign CPU_opcode_a1[6:0] = CPU_instr_a1[6:0]; + + assign CPU_dec_bits_a1[10:0] = {CPU_funct7_a1[5],CPU_funct3_a1,CPU_opcode_a1}; + + // Branch Instruction + assign CPU_is_beq_a1 = CPU_dec_bits_a1[9:0] == 10'b000_1100011; + assign CPU_is_bne_a1 = CPU_dec_bits_a1[9:0] == 10'b001_1100011; + assign CPU_is_blt_a1 = CPU_dec_bits_a1[9:0] == 10'b100_1100011; + assign CPU_is_bge_a1 = CPU_dec_bits_a1[9:0] == 10'b101_1100011; + assign CPU_is_bltu_a1 = CPU_dec_bits_a1[9:0] == 10'b110_1100011; + assign CPU_is_bgeu_a1 = CPU_dec_bits_a1[9:0] == 10'b111_1100011; + + // Arithmetic Instruction + assign CPU_is_add_a1 = CPU_dec_bits_a1 == 11'b0_000_0110011; + assign CPU_is_addi_a1 = CPU_dec_bits_a1[9:0] == 10'b000_0010011; + assign CPU_is_or_a1 = CPU_dec_bits_a1 == 11'b0_110_0110011; + assign CPU_is_ori_a1 = CPU_dec_bits_a1[9:0] == 10'b110_0010011; + assign CPU_is_xor_a1 = CPU_dec_bits_a1 == 11'b0_100_0110011; + assign CPU_is_xori_a1 = CPU_dec_bits_a1[9:0] == 10'b100_0010011; + assign CPU_is_and_a1 = CPU_dec_bits_a1 == 11'b0_111_0110011; + assign CPU_is_andi_a1 = CPU_dec_bits_a1[9:0] == 10'b111_0010011; + assign CPU_is_sub_a1 = CPU_dec_bits_a1 == 11'b1_000_0110011; + assign CPU_is_slti_a1 = CPU_dec_bits_a1[9:0] == 10'b010_0010011; + assign CPU_is_sltiu_a1 = CPU_dec_bits_a1[9:0] == 10'b011_0010011; + assign CPU_is_slli_a1 = CPU_dec_bits_a1 == 11'b0_001_0010011; + assign CPU_is_srli_a1 = CPU_dec_bits_a1 == 11'b0_101_0010011; + assign CPU_is_srai_a1 = CPU_dec_bits_a1 == 11'b1_101_0010011; + assign CPU_is_sll_a1 = CPU_dec_bits_a1 == 11'b0_001_0110011; + assign CPU_is_slt_a1 = CPU_dec_bits_a1 == 11'b0_010_0110011; + assign CPU_is_sltu_a1 = CPU_dec_bits_a1 == 11'b0_011_0110011; + assign CPU_is_srl_a1 = CPU_dec_bits_a1 == 11'b0_101_0110011; + assign CPU_is_sra_a1 = CPU_dec_bits_a1 == 11'b1_101_0110011; + + // Load Instruction + assign CPU_is_load_a1 = CPU_dec_bits_a1[6:0] == 7'b0000011; + + // Store Instruction + assign CPU_is_sb_a1 = CPU_dec_bits_a1[9:0] == 10'b000_0100011; + assign CPU_is_sh_a1 = CPU_dec_bits_a1[9:0] == 10'b001_0100011; + assign CPU_is_sw_a1 = CPU_dec_bits_a1[9:0] == 10'b010_0100011; + + // Jump Instruction + assign CPU_is_lui_a1 = CPU_dec_bits_a1[6:0] == 7'b0110111; + assign CPU_is_auipc_a1 = CPU_dec_bits_a1[6:0] == 7'b0010111; + assign CPU_is_jal_a1 = CPU_dec_bits_a1[6:0] == 7'b1101111; + assign CPU_is_jalr_a1 = CPU_dec_bits_a1[9:0] == 10'b000_1100111; + + assign CPU_is_jump_a1 = CPU_is_jal_a1 || CPU_is_jalr_a1; + + //_@2 + // Register File Read + assign CPU_rf_rd_en1_a2 = CPU_rs1_valid_a2; + //_?$rf_rd_en1 + assign CPU_rf_rd_index1_a2[4:0] = CPU_rs1_a2[4:0]; + + assign CPU_rf_rd_en2_a2 = CPU_rs2_valid_a2; + //_?$rf_rd_en2 + assign CPU_rf_rd_index2_a2[4:0] = CPU_rs2_a2[4:0]; + + // Branch Target PC + assign CPU_br_tgt_pc_a2[31:0] = CPU_pc_a2 + CPU_imm_a2; + + // Jump Target PC + assign CPU_jalr_tgt_pc_a2[31:0] = CPU_src1_value_a2 + CPU_imm_a2; + + // Input signals to ALU + assign CPU_src1_value_a2[31:0] = ((CPU_rd_a3 == CPU_rs1_a2) && CPU_rf_wr_en_a3) ? CPU_result_a3 : CPU_rf_rd_data1_a2[31:0]; + assign CPU_src2_value_a2[31:0] = ((CPU_rd_a3 == CPU_rs2_a2) && CPU_rf_wr_en_a3) ? CPU_result_a3 : CPU_rf_rd_data2_a2[31:0]; + + //_@3 + + // ALU + assign CPU_sltu_result_a3 = CPU_src1_value_a3 < CPU_src2_value_a3 ; + assign CPU_sltiu_result_a3 = CPU_src1_value_a3 < CPU_imm_a3 ; + + assign CPU_result_a3[31:0] = CPU_is_addi_a3 ? CPU_src1_value_a3 + CPU_imm_a3 : + CPU_is_add_a3 ? CPU_src1_value_a3 + CPU_src2_value_a3 : + CPU_is_or_a3 ? CPU_src1_value_a3 | CPU_src2_value_a3 : + CPU_is_ori_a3 ? CPU_src1_value_a3 | CPU_imm_a3 : + CPU_is_xor_a3 ? CPU_src1_value_a3 ^ CPU_src2_value_a3 : + CPU_is_xori_a3 ? CPU_src1_value_a3 ^ CPU_imm_a3 : + CPU_is_and_a3 ? CPU_src1_value_a3 & CPU_src2_value_a3 : + CPU_is_andi_a3 ? CPU_src1_value_a3 & CPU_imm_a3 : + CPU_is_sub_a3 ? CPU_src1_value_a3 - CPU_src2_value_a3 : + CPU_is_slti_a3 ? ((CPU_src1_value_a3[31] == CPU_imm_a3[31]) ? CPU_sltiu_result_a3 : {31'b0,CPU_src1_value_a3[31]}) : + CPU_is_sltiu_a3 ? CPU_sltiu_result_a3 : + CPU_is_slli_a3 ? CPU_src1_value_a3 << CPU_imm_a3[5:0] : + CPU_is_srli_a3 ? CPU_src1_value_a3 >> CPU_imm_a3[5:0] : + CPU_is_srai_a3 ? ({{32{CPU_src1_value_a3[31]}}, CPU_src1_value_a3} >> CPU_imm_a3[4:0]) : + CPU_is_sll_a3 ? CPU_src1_value_a3 << CPU_src2_value_a3[4:0] : + CPU_is_slt_a3 ? ((CPU_src1_value_a3[31] == CPU_src2_value_a3[31]) ? CPU_sltu_result_a3 : {31'b0,CPU_src1_value_a3[31]}) : + CPU_is_sltu_a3 ? CPU_sltu_result_a3 : + CPU_is_srl_a3 ? CPU_src1_value_a3 >> CPU_src2_value_a3[5:0] : + CPU_is_sra_a3 ? ({{32{CPU_src1_value_a3[31]}}, CPU_src1_value_a3} >> CPU_src2_value_a3[4:0]) : + CPU_is_lui_a3 ? ({CPU_imm_a3[31:12], 12'b0}) : + CPU_is_auipc_a3 ? CPU_pc_a3 + CPU_imm_a3 : + CPU_is_jal_a3 ? CPU_pc_a3 + 4 : + CPU_is_jalr_a3 ? CPU_pc_a3 + 4 : + (CPU_is_load_a3 || CPU_is_s_instr_a3) ? CPU_src1_value_a3 + CPU_imm_a3 : 32'bx; + + // Register File Write + assign CPU_rf_wr_en_a3 = (CPU_rd_valid_a3 && CPU_valid_a3 && CPU_rd_a3 != 5'b0) || CPU_valid_load_a5; + //_?$rf_wr_en + assign CPU_rf_wr_index_a3[4:0] = !CPU_valid_a3 ? CPU_rd_a5[4:0] : CPU_rd_a3[4:0]; + + assign CPU_rf_wr_data_a3[31:0] = !CPU_valid_a3 ? CPU_ld_data_a5[31:0] : CPU_result_a3[31:0]; + + // Branch + assign CPU_taken_br_a3 = CPU_is_beq_a3 ? (CPU_src1_value_a3 == CPU_src2_value_a3) : + CPU_is_bne_a3 ? (CPU_src1_value_a3 != CPU_src2_value_a3) : + CPU_is_blt_a3 ? ((CPU_src1_value_a3 < CPU_src2_value_a3) ^ (CPU_src1_value_a3[31] != CPU_src2_value_a3[31])) : + CPU_is_bge_a3 ? ((CPU_src1_value_a3 >= CPU_src2_value_a3) ^ (CPU_src1_value_a3[31] != CPU_src2_value_a3[31])) : + CPU_is_bltu_a3 ? (CPU_src1_value_a3 < CPU_src2_value_a3) : + CPU_is_bgeu_a3 ? (CPU_src1_value_a3 >= CPU_src2_value_a3) : 1'b0; + + assign CPU_valid_taken_br_a3 = CPU_valid_a3 && CPU_taken_br_a3; + + // Load + assign CPU_valid_load_a3 = CPU_valid_a3 && CPU_is_load_a3; + assign CPU_valid_a3 = !(CPU_valid_taken_br_a4 || CPU_valid_taken_br_a5 || CPU_valid_load_a4 || CPU_valid_load_a5 || CPU_valid_jump_a4 || CPU_valid_jump_a5); + + // Jump + assign CPU_valid_jump_a3 = CPU_valid_a3 && CPU_is_jump_a3; + + //_@4 + assign CPU_dmem_rd_en_a4 = CPU_valid_load_a4; + assign CPU_dmem_wr_en_a4 = CPU_valid_a4 && CPU_is_s_instr_a4; + assign CPU_dmem_addr_a4[3:0] = CPU_result_a4[5:2]; + assign CPU_dmem_wr_data_a4[31:0] = CPU_src2_value_a4[31:0]; + + //_@5 + assign CPU_ld_data_a5[31:0] = CPU_dmem_rd_data_a5[31:0]; + + // Note: Because of the magic we are using for visualisation, if visualisation is enabled below, + // be sure to avoid having unassigned signals (which you might be using for random inputs) + // other than those specifically expected in the labs. You'll get strange errors for these. + + `BOGUS_USE(CPU_is_beq_a5 CPU_is_bne_a5 CPU_is_blt_a5 CPU_is_bge_a5 CPU_is_bltu_a5 CPU_is_bgeu_a5) + `BOGUS_USE(CPU_is_sb_a5 CPU_is_sh_a5 CPU_is_sw_a5) + // Assert these to end simulation (before Makerchip cycle limit). + /*SV_plus*/ + always @ (posedge CLK) begin + OUT = CPU_Xreg_value_a5[17]; + end + + // Macro instantiations for: + // o instruction memory + // o register file + // o data memory + // o CPU visualization + //_|cpu + // m4+imem(@1) // Args: (read stage) + //_\source /raw.githubusercontent.com/shivanishah269/riscvcore/master/FPGAImplementation/riscvshelllib.tlv 31 // Instantiated from rvmyth.tlv, 226 as: m4+rf(@2, @3) + // Reg File + //_@3 + for (xreg = 0; xreg <= 31; xreg=xreg+1) begin : L1_CPU_Xreg //_/xreg + + // For $wr. + wire L1_wr_a3; + + assign L1_wr_a3 = CPU_rf_wr_en_a3 && (CPU_rf_wr_index_a3 != 5'b0) && (CPU_rf_wr_index_a3 == xreg); + assign CPU_Xreg_value_a3[xreg][31:0] = CPU_reset_a3 ? xreg : + L1_wr_a3 ? CPU_rf_wr_data_a3 : + CPU_Xreg_value_a4[xreg][31:0]; + end + //_@2 + //_?$rf_rd_en1 + assign CPU_rf_rd_data1_a2[31:0] = CPU_Xreg_value_a4[CPU_rf_rd_index1_a2]; + //_?$rf_rd_en2 + assign CPU_rf_rd_data2_a2[31:0] = CPU_Xreg_value_a4[CPU_rf_rd_index2_a2]; + `BOGUS_USE(CPU_rf_rd_data1_a2 CPU_rf_rd_data2_a2) + //_\end_source // Args: (read stage, write stage) - if equal, no register bypass is required + //_\source /raw.githubusercontent.com/shivanishah269/riscvcore/master/FPGAImplementation/riscvshelllib.tlv 48 // Instantiated from rvmyth.tlv, 227 as: m4+dmem(@4) + // Data Memory + //_@4 + for (dmem = 0; dmem <= 15; dmem=dmem+1) begin : L1_CPU_Dmem //_/dmem + + // For $wr. + wire L1_wr_a4; + + assign L1_wr_a4 = CPU_dmem_wr_en_a4 && (CPU_dmem_addr_a4 == dmem); + assign CPU_Dmem_value_a4[dmem][31:0] = CPU_reset_a4 ? dmem : + L1_wr_a4 ? CPU_dmem_wr_data_a4 : + CPU_Dmem_value_a5[dmem][31:0]; + + end + //_?$dmem_rd_en + assign CPU_dmem_rd_data_a4[31:0] = CPU_Dmem_value_a5[CPU_dmem_addr_a4]; + //`BOGUS_USE($dmem_rd_data) + //_\end_source // Args: (read/write stage) +endgenerate + +//_\SV + + endmodule
diff --git a/verilog/rtl/sram_32_256_sky130A.v b/verilog/rtl/sram_32_256_sky130A.v new file mode 100644 index 0000000..d45d17e --- /dev/null +++ b/verilog/rtl/sram_32_256_sky130A.v
@@ -0,0 +1,72 @@ +// OpenRAM SRAM model +// Words: 256 +// Word size: 32 + +module sram_32_256_sky130A( +`ifdef USE_POWER_PINS + vccd1, + vssd1, +`endif +// Port 0: RW + clk0,csb0,web0,addr0,din0,dout0 + ); + + parameter DATA_WIDTH = 32 ; + parameter ADDR_WIDTH = 8 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. + parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary + +`ifdef USE_POWER_PINS + inout vccd1; + inout vssd1; +`endif + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [ADDR_WIDTH-1:0] addr0; + input [DATA_WIDTH-1:0] din0; + output [DATA_WIDTH-1:0] dout0; + + reg csb0_reg; + reg web0_reg; + reg [ADDR_WIDTH-1:0] addr0_reg; + reg [DATA_WIDTH-1:0] din0_reg; + reg [DATA_WIDTH-1:0] dout0; + + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + addr0_reg = addr0; + din0_reg = din0; + #(T_HOLD) dout0 = 32'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) + $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); + if ( !csb0_reg && !web0_reg && VERBOSE ) + $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); + end + +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) begin + mem[addr0_reg][31:0] = din0_reg[31:0]; + end + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + dout0 <= #(DELAY) mem[addr0_reg]; + end + +endmodule
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 26081e9..a1dd5b8 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -14,152 +14,37 @@ // SPDX-License-Identifier: Apache-2.0 `default_nettype none -/* - *------------------------------------------------------------- - * - * user_proj_example - * - * This is an example of a (trivially simple) user project, - * showing how the user project can connect to the logic - * analyzer, the wishbone bus, and the I/O pads. - * - * This project generates an integer count, which is output - * on the user area GPIO pads (digital output only). The - * wishbone connection allows the project to be controlled - * (start and stop) from the management SoC program. - * - * See the testbenches in directory "mprj_counter" for the - * example programs that drive this user project. The three - * testbenches are "io_ports", "la_test1", and "la_test2". - * - *------------------------------------------------------------- - */ -module user_proj_example #( - parameter BITS = 32 -)( +module user_proj_example ( `ifdef USE_POWER_PINS inout vccd1, // User area 1 1.8V supply inout vssd1, // User area 1 digital ground `endif + output [9:0] OUT, + input CLK, + input reset, - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oenb, - - // IOs - input [`MPRJ_IO_PADS-1:0] io_in, - output [`MPRJ_IO_PADS-1:0] io_out, - output [`MPRJ_IO_PADS-1:0] io_oeb, - - // IRQ - output [2:0] irq + output mem_wr, + output [7:0] mem_addr, + input init_en, + input [7:0] init_addr, + input [31:0] imem_data ); - wire clk; - wire rst; - wire [`MPRJ_IO_PADS-1:0] io_in; - wire [`MPRJ_IO_PADS-1:0] io_out; - wire [`MPRJ_IO_PADS-1:0] io_oeb; + wire [7:0] imem_addr; - wire [31:0] rdata; - wire [31:0] wdata; - wire [BITS-1:0] count; + assign mem_wr = init_en ? 1'b0 : 1'b1; + assign mem_addr = init_en ? init_addr : imem_addr; - wire valid; - wire [3:0] wstrb; - wire [31:0] la_write; + rvmyth core ( + .OUT(OUT), + .CLK(CLK), + .reset(reset), - // WB MI A - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & {4{wbs_we_i}}; - assign wbs_dat_o = rdata; - assign wdata = wbs_dat_i; - - // IO - assign io_out = count; - assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; - - // IRQ - assign irq = 3'b000; // Unused - - // LA - assign la_data_out = {{(127-BITS){1'b0}}, count}; - // Assuming LA probes [63:32] are for controlling the count register - assign la_write = ~la_oenb[63:32] & ~{BITS{valid}}; - // Assuming LA probes [65:64] are for controlling the count clk & reset - assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i; - assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i; - - counter #( - .BITS(BITS) - ) counter( - .clk(clk), - .reset(rst), - .ready(wbs_ack_o), - .valid(valid), - .rdata(rdata), - .wdata(wbs_dat_i), - .wstrb(wstrb), - .la_write(la_write), - .la_input(la_data_in[63:32]), - .count(count) + .imem_addr(imem_addr), + .imem_data(imem_data) ); endmodule -module counter #( - parameter BITS = 32 -)( - input clk, - input reset, - input valid, - input [3:0] wstrb, - input [BITS-1:0] wdata, - input [BITS-1:0] la_write, - input [BITS-1:0] la_input, - output ready, - output [BITS-1:0] rdata, - output [BITS-1:0] count -); - reg ready; - reg [BITS-1:0] count; - reg [BITS-1:0] rdata; - - always @(posedge clk) begin - if (reset) begin - count <= 0; - ready <= 0; - end else begin - ready <= 1'b0; - if (~|la_write) begin - count <= count + 1; - end - if (valid && !ready) begin - ready <= 1'b1; - rdata <= count; - if (wstrb[0]) count[7:0] <= wdata[7:0]; - if (wstrb[1]) count[15:8] <= wdata[15:8]; - if (wstrb[2]) count[23:16] <= wdata[23:16]; - if (wstrb[3]) count[31:24] <= wdata[31:24]; - end else if (|la_write) begin - count <= la_write & la_input; - end - end - end - -endmodule -`default_nettype wire +`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 5ee1cee..c08f62d 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -22,10 +22,6 @@ * This wrapper enumerates all of the pins available to the * user for the user project. * - * An example user project is provided in this wrapper. The - * example should be removed and replaced with the actual - * user project. - * *------------------------------------------------------------- */ @@ -81,43 +77,40 @@ /*--------------------------------------*/ /* User project is instantiated here */ /*--------------------------------------*/ + wire mem_wr; + wire [7:0] mem_addr; + + wire [31:0] imem_data; -user_proj_example mprj ( + user_proj_example mprj ( `ifdef USE_POWER_PINS - .vccd1(vccd1), // User area 1 1.8V power - .vssd1(vssd1), // User area 1 digital ground + .vccd1(vccd1), // User area 1 1.8V supply + .vssd1(vssd1), // User area 1 digital ground `endif + .OUT(wbs_dat_o[9:0]), + .CLK(wb_clk_i), + .reset(wb_rst_i), - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), + .mem_wr(mem_wr), + .mem_addr(mem_addr), + .init_en(wbs_sel_i[0]), + .init_addr(wbs_adr_i[7:0]), + .imem_data(imem_data) + ); - // MGMT SoC Wishbone Slave - - .wbs_cyc_i(wbs_cyc_i), - .wbs_stb_i(wbs_stb_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_adr_i(wbs_adr_i), - .wbs_dat_i(wbs_dat_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), - - // Logic Analyzer - - .la_data_in(la_data_in), - .la_data_out(la_data_out), - .la_oenb (la_oenb), - - // IO Pads - - .io_in (io_in), - .io_out(io_out), - .io_oeb(io_oeb), - - // IRQ - .irq(user_irq) -); + sram_32_256_sky130A mem ( +`ifdef USE_POWER_PINS + .vccd1(vccd1), // User area 1 1.8V supply + .vssd1(vssd1), // User area 1 digital ground +`endif + .clk0(wb_clk_i), + .csb0(1'b0), + .web0(mem_wr), + .addr0(mem_addr), + .din0(wbs_dat_i), + .dout0(imem_data) + ); endmodule // user_project_wrapper -`default_nettype wire +`default_nettype wire \ No newline at end of file