simulation for LA ports added
diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def
index 1fd06f9..2e360ce 100644
--- a/def/user_project_wrapper.def
+++ b/def/user_project_wrapper.def
@@ -7407,7 +7407,7 @@
NEW met4 3100 + SHAPE STRIPE ( 1199120 -19070 ) ( 1199120 190000 )
NEW met4 3100 + SHAPE STRIPE ( 1019120 -19070 ) ( 1019120 190000 ) ;
END SPECIALNETS
-NETS 679 ;
+NETS 678 ;
- analog_io[0] ( PIN analog_io[0] ) + USE SIGNAL ;
- analog_io[10] ( PIN analog_io[10] ) + USE SIGNAL ;
- analog_io[11] ( PIN analog_io[11] ) + USE SIGNAL ;
@@ -7438,16 +7438,16 @@
- analog_io[8] ( PIN analog_io[8] ) + USE SIGNAL ;
- analog_io[9] ( PIN analog_io[9] ) + USE SIGNAL ;
- imem_data\[0\] ( mprj imem_data[0] ) ( mem dout0[0] ) + USE SIGNAL
- + ROUTED met3 ( 2499180 2759780 0 ) ( 2504930 * )
- NEW met2 ( 2504930 200430 ) ( * 2759780 )
+ + ROUTED met3 ( 2499180 2759780 0 ) ( 2505390 * )
+ NEW met2 ( 2505390 200430 ) ( * 2759780 )
NEW met2 ( 1143330 200260 ) ( * 200430 )
NEW met3 ( 1142180 200260 ) ( 1143330 * )
NEW met4 ( 1142180 198900 ) ( * 200260 )
NEW met4 ( 1140950 198900 ) ( 1142180 * )
NEW met4 ( 1140950 198900 ) ( * 202300 0 )
- NEW met1 ( 1143330 200430 ) ( 2504930 * )
- NEW met1 ( 2504930 200430 ) M1M2_PR
- NEW met2 ( 2504930 2759780 ) M2M3_PR_M
+ NEW met1 ( 1143330 200430 ) ( 2505390 * )
+ NEW met1 ( 2505390 200430 ) M1M2_PR
+ NEW met2 ( 2505390 2759780 ) M2M3_PR_M
NEW met1 ( 1143330 200430 ) M1M2_PR
NEW met2 ( 1143330 200260 ) M2M3_PR_M
NEW met3 ( 1142180 200260 ) M3M4_PR_M ;
@@ -7457,16 +7457,16 @@
NEW met4 ( 1272820 198900 ) ( * 199580 )
NEW met4 ( 1272190 198900 ) ( 1272820 * )
NEW met4 ( 1272190 198900 ) ( * 202300 0 )
- NEW met2 ( 1081230 1489370 ) ( * 1500420 0 )
+ NEW met2 ( 1081230 1487330 ) ( * 1500420 0 )
NEW met1 ( 1007170 202470 ) ( 1272590 * )
- NEW met2 ( 1007170 202470 ) ( * 1489370 )
- NEW met1 ( 1007170 1489370 ) ( 1081230 * )
+ NEW met2 ( 1007170 202470 ) ( * 1487330 )
+ NEW met1 ( 1007170 1487330 ) ( 1081230 * )
NEW met1 ( 1272590 202470 ) M1M2_PR
NEW met2 ( 1272590 199580 ) M2M3_PR_M
NEW met3 ( 1272820 199580 ) M3M4_PR_M
- NEW met1 ( 1081230 1489370 ) M1M2_PR
+ NEW met1 ( 1081230 1487330 ) M1M2_PR
NEW met1 ( 1007170 202470 ) M1M2_PR
- NEW met1 ( 1007170 1489370 ) M1M2_PR
+ NEW met1 ( 1007170 1487330 ) M1M2_PR
NEW met3 ( 1272590 199580 ) RECT ( -390 -150 0 150 ) ;
- imem_data\[11\] ( mprj imem_data[11] ) ( mem dout0[11] ) + USE SIGNAL
+ ROUTED met2 ( 1284550 198220 ) ( * 202130 )
@@ -7474,103 +7474,94 @@
NEW met4 ( 1284780 198220 ) ( * 198900 )
NEW met4 ( 1284780 198900 ) ( 1285110 * )
NEW met4 ( 1285110 198900 ) ( * 202300 0 )
- NEW met2 ( 996130 202130 ) ( * 2698580 )
- NEW met3 ( 996130 2698580 ) ( 1000500 * 0 )
- NEW met1 ( 996130 202130 ) ( 1284550 * )
- NEW met1 ( 996130 202130 ) M1M2_PR
- NEW met2 ( 996130 2698580 ) M2M3_PR_M
+ NEW met2 ( 997050 202130 ) ( * 2698580 )
+ NEW met3 ( 997050 2698580 ) ( 1000500 * 0 )
+ NEW met1 ( 997050 202130 ) ( 1284550 * )
+ NEW met1 ( 997050 202130 ) M1M2_PR
+ NEW met2 ( 997050 2698580 ) M2M3_PR_M
NEW met1 ( 1284550 202130 ) M1M2_PR
NEW met2 ( 1284550 198220 ) M2M3_PR_M
NEW met3 ( 1284780 198220 ) M3M4_PR_M
NEW met3 ( 1284550 198220 ) RECT ( -390 -150 0 150 ) ;
- imem_data\[12\] ( mprj imem_data[12] ) ( mem dout0[12] ) + USE SIGNAL
- + ROUTED met2 ( 1052710 576130 ) ( * 580890 )
- NEW met1 ( 1052710 580890 ) ( 1066970 * )
- NEW met1 ( 1083530 771290 ) ( 1090430 * )
- NEW met2 ( 1090430 771290 ) ( * 790330 )
- NEW met1 ( 1066970 620670 ) ( 1072950 * )
- NEW met2 ( 1066970 580890 ) ( * 620670 )
- NEW met1 ( 1072950 728110 ) ( 1083530 * )
- NEW met2 ( 1072950 620670 ) ( * 728110 )
- NEW met2 ( 1083530 728110 ) ( * 771290 )
+ + ROUTED met1 ( 1052250 703970 ) ( 1068350 * )
+ NEW met1 ( 1086750 770950 ) ( 1093650 * )
+ NEW met2 ( 1052250 634950 ) ( * 703970 )
+ NEW met1 ( 1068350 717570 ) ( 1086750 * )
+ NEW met2 ( 1068350 703970 ) ( * 717570 )
+ NEW met2 ( 1086750 717570 ) ( * 770950 )
+ NEW met2 ( 1093650 770950 ) ( * 941630 )
NEW met2 ( 1242230 1500420 ) ( 1243150 * 0 )
- NEW met2 ( 1242230 851870 ) ( * 1500420 )
+ NEW met2 ( 1242230 941630 ) ( * 1500420 )
NEW met1 ( 1006710 213690 ) ( 1007630 * )
NEW met2 ( 1007630 201110 ) ( * 213690 )
- NEW met1 ( 1006710 576130 ) ( 1052710 * )
- NEW met1 ( 1090430 790330 ) ( 1100550 * )
+ NEW met1 ( 1006710 586330 ) ( 1021430 * )
+ NEW met1 ( 1021430 586330 ) ( * 586670 )
+ NEW met1 ( 1021430 586670 ) ( 1028330 * )
+ NEW met2 ( 1028330 586670 ) ( * 607410 )
+ NEW met1 ( 1028330 607410 ) ( 1038450 * )
NEW met2 ( 1297890 198220 ) ( * 201110 )
NEW met3 ( 1297660 198220 ) ( 1297890 * )
NEW met4 ( 1297660 198220 ) ( * 198900 )
NEW met4 ( 1297660 198900 ) ( 1298030 * )
NEW met4 ( 1298030 198900 ) ( * 202300 0 )
NEW met1 ( 1007630 201110 ) ( 1297890 * )
- NEW met2 ( 1006710 213690 ) ( * 576130 )
- NEW met2 ( 1100550 790330 ) ( * 851870 )
- NEW met1 ( 1100550 851870 ) ( 1242230 * )
- NEW met1 ( 1052710 576130 ) M1M2_PR
- NEW met1 ( 1052710 580890 ) M1M2_PR
- NEW met1 ( 1066970 580890 ) M1M2_PR
- NEW met1 ( 1083530 771290 ) M1M2_PR
- NEW met1 ( 1090430 771290 ) M1M2_PR
- NEW met1 ( 1090430 790330 ) M1M2_PR
- NEW met1 ( 1066970 620670 ) M1M2_PR
- NEW met1 ( 1072950 620670 ) M1M2_PR
- NEW met1 ( 1072950 728110 ) M1M2_PR
- NEW met1 ( 1083530 728110 ) M1M2_PR
- NEW met1 ( 1242230 851870 ) M1M2_PR
+ NEW met2 ( 1006710 213690 ) ( * 586330 )
+ NEW met1 ( 1048800 634950 ) ( 1052250 * )
+ NEW met1 ( 1038450 634610 ) ( 1048800 * )
+ NEW met1 ( 1048800 634610 ) ( * 634950 )
+ NEW met2 ( 1038450 607410 ) ( * 634610 )
+ NEW met1 ( 1093650 941630 ) ( 1242230 * )
+ NEW met1 ( 1052250 703970 ) M1M2_PR
+ NEW met1 ( 1068350 703970 ) M1M2_PR
+ NEW met1 ( 1086750 770950 ) M1M2_PR
+ NEW met1 ( 1093650 770950 ) M1M2_PR
+ NEW met1 ( 1052250 634950 ) M1M2_PR
+ NEW met1 ( 1068350 717570 ) M1M2_PR
+ NEW met1 ( 1086750 717570 ) M1M2_PR
+ NEW met1 ( 1093650 941630 ) M1M2_PR
+ NEW met1 ( 1242230 941630 ) M1M2_PR
NEW met1 ( 1006710 213690 ) M1M2_PR
NEW met1 ( 1007630 213690 ) M1M2_PR
NEW met1 ( 1007630 201110 ) M1M2_PR
- NEW met1 ( 1006710 576130 ) M1M2_PR
- NEW met1 ( 1100550 790330 ) M1M2_PR
+ NEW met1 ( 1006710 586330 ) M1M2_PR
+ NEW met1 ( 1028330 586670 ) M1M2_PR
+ NEW met1 ( 1028330 607410 ) M1M2_PR
+ NEW met1 ( 1038450 607410 ) M1M2_PR
NEW met1 ( 1297890 201110 ) M1M2_PR
NEW met2 ( 1297890 198220 ) M2M3_PR_M
NEW met3 ( 1297660 198220 ) M3M4_PR_M
- NEW met1 ( 1100550 851870 ) M1M2_PR
+ NEW met1 ( 1038450 634610 ) M1M2_PR
NEW met3 ( 1297890 198220 ) RECT ( 0 -150 390 150 ) ;
- imem_data\[13\] ( mprj imem_data[13] ) ( mem dout0[13] ) + USE SIGNAL
- + ROUTED met2 ( 1532030 203660 ) ( 1532490 * )
- NEW met2 ( 1532490 200260 ) ( * 203660 )
- NEW met2 ( 1532490 200260 ) ( 1533410 * )
- NEW met3 ( 1533410 200260 ) ( 1535940 * )
- NEW met3 ( 1535940 199580 ) ( * 200260 )
- NEW met3 ( 1535940 199580 ) ( 1537780 * )
- NEW met3 ( 1537780 199580 ) ( * 200260 )
- NEW met3 ( 1537780 200260 ) ( 1578260 * )
- NEW met3 ( 1578260 200260 ) ( * 204340 )
- NEW met2 ( 1851270 2999820 0 ) ( * 3010700 )
+ + ROUTED met2 ( 1532030 200260 ) ( * 203660 )
+ NEW met2 ( 1532030 200260 ) ( 1533410 * )
+ NEW met3 ( 1533410 200260 ) ( 1577340 * )
+ NEW met3 ( 1577340 200260 ) ( * 200940 )
+ NEW met2 ( 1851270 2999820 0 ) ( * 3010020 )
NEW met2 ( 1312610 199580 ) ( * 204170 )
NEW met3 ( 1312380 199580 ) ( 1312610 * )
NEW met4 ( 1312380 198900 ) ( * 199580 )
NEW met4 ( 1311630 198900 ) ( 1312380 * )
NEW met4 ( 1311630 198900 ) ( * 202300 0 )
- NEW met3 ( 1578260 204340 ) ( 1582860 * )
- NEW met3 ( 1582860 3010700 ) ( 1851270 * )
- NEW met4 ( 1582860 204340 ) ( * 3010700 )
+ NEW met3 ( 1577340 200940 ) ( 1598500 * )
+ NEW met3 ( 1598500 3010020 ) ( 1851270 * )
+ NEW met4 ( 1598500 200940 ) ( * 3010020 )
NEW met2 ( 1318590 204170 ) ( * 205020 )
NEW met2 ( 1318590 205020 ) ( 1319510 * )
NEW met2 ( 1319510 203660 ) ( * 205020 )
- NEW met3 ( 1319510 203660 ) ( 1337910 * )
- NEW met2 ( 1337910 203150 ) ( * 203660 )
- NEW met1 ( 1337910 203150 ) ( 1365970 * )
- NEW met2 ( 1365970 203150 ) ( * 203660 )
NEW met1 ( 1312610 204170 ) ( 1318590 * )
- NEW met3 ( 1365970 203660 ) ( 1532030 * )
+ NEW met3 ( 1319510 203660 ) ( 1532030 * )
NEW met2 ( 1532030 203660 ) M2M3_PR_M
NEW met2 ( 1533410 200260 ) M2M3_PR_M
- NEW met2 ( 1851270 3010700 ) M2M3_PR_M
+ NEW met2 ( 1851270 3010020 ) M2M3_PR_M
NEW met1 ( 1312610 204170 ) M1M2_PR
NEW met2 ( 1312610 199580 ) M2M3_PR_M
NEW met3 ( 1312380 199580 ) M3M4_PR_M
- NEW met3 ( 1582860 204340 ) M3M4_PR_M
- NEW met3 ( 1582860 3010700 ) M3M4_PR_M
+ NEW met3 ( 1598500 200940 ) M3M4_PR_M
+ NEW met3 ( 1598500 3010020 ) M3M4_PR_M
NEW met1 ( 1318590 204170 ) M1M2_PR
NEW met2 ( 1319510 203660 ) M2M3_PR_M
- NEW met2 ( 1337910 203660 ) M2M3_PR_M
- NEW met1 ( 1337910 203150 ) M1M2_PR
- NEW met1 ( 1365970 203150 ) M1M2_PR
- NEW met2 ( 1365970 203660 ) M2M3_PR_M
NEW met3 ( 1312610 199580 ) RECT ( 0 -150 390 150 ) ;
- imem_data\[14\] ( mprj imem_data[14] ) ( mem dout0[14] ) + USE SIGNAL
+ ROUTED met2 ( 2297930 1500420 ) ( 2298390 * 0 )
@@ -7586,86 +7577,79 @@
NEW met3 ( 1324340 198900 ) M3M4_PR_M
NEW met3 ( 1324570 198900 ) RECT ( 0 -150 390 150 ) ;
- imem_data\[15\] ( mprj imem_data[15] ) ( mem dout0[15] ) + USE SIGNAL
- + ROUTED met2 ( 1532030 200090 ) ( * 200260 )
- NEW met1 ( 1532030 200090 ) ( 1578950 * )
- NEW met2 ( 1578950 200090 ) ( * 203660 )
- NEW met3 ( 1338370 207060 ) ( 1339290 * )
- NEW met3 ( 1578950 203660 ) ( 1598500 * )
- NEW met2 ( 2013190 2999820 0 ) ( * 3009340 )
- NEW met3 ( 1598500 3009340 ) ( 2013190 * )
- NEW met4 ( 1598500 203660 ) ( * 3009340 )
- NEW met3 ( 1339290 203660 ) ( 1365050 * )
- NEW met2 ( 1365050 203660 ) ( * 206890 )
+ + ROUTED met4 ( 1532260 197540 ) ( * 200260 )
+ NEW met3 ( 1532260 197540 ) ( 1576190 * )
+ NEW met2 ( 1576190 197540 ) ( * 205700 )
+ NEW met3 ( 1338370 207060 ) ( 1386670 * )
+ NEW met3 ( 1576190 205700 ) ( 1590220 * )
+ NEW met2 ( 2013190 2999820 0 ) ( * 3011380 )
+ NEW met3 ( 1590220 3011380 ) ( 2013190 * )
+ NEW met4 ( 1590220 205700 ) ( * 3011380 )
NEW met4 ( 1337470 198900 ) ( * 202300 0 )
NEW met4 ( 1337470 198900 ) ( 1338140 * )
NEW met3 ( 1338140 198900 ) ( 1338370 * )
NEW met2 ( 1338370 198900 ) ( * 207060 )
- NEW met2 ( 1339290 203660 ) ( * 207060 )
- NEW met3 ( 1414500 200260 ) ( 1532030 * )
- NEW met2 ( 1407370 198900 ) ( * 206890 )
- NEW met3 ( 1407370 198900 ) ( 1414500 * )
+ NEW met3 ( 1414500 200260 ) ( 1532260 * )
+ NEW met3 ( 1386670 197540 ) ( 1413580 * )
+ NEW met4 ( 1413580 197540 ) ( * 198900 )
+ NEW met4 ( 1413580 198900 ) ( 1414500 * )
NEW met4 ( 1414500 198900 ) ( * 200260 )
- NEW met1 ( 1365050 206890 ) ( 1407370 * )
- NEW met2 ( 1339290 207060 ) M2M3_PR_M
- NEW met2 ( 1532030 200260 ) M2M3_PR_M
- NEW met1 ( 1532030 200090 ) M1M2_PR
- NEW met1 ( 1578950 200090 ) M1M2_PR
- NEW met2 ( 1578950 203660 ) M2M3_PR_M
+ NEW met2 ( 1386670 197540 ) ( * 207060 )
+ NEW met2 ( 1386670 207060 ) M2M3_PR_M
+ NEW met3 ( 1532260 200260 ) M3M4_PR_M
+ NEW met3 ( 1532260 197540 ) M3M4_PR_M
+ NEW met2 ( 1576190 197540 ) M2M3_PR_M
+ NEW met2 ( 1576190 205700 ) M2M3_PR_M
NEW met2 ( 1338370 207060 ) M2M3_PR_M
- NEW met3 ( 1598500 203660 ) M3M4_PR_M
- NEW met3 ( 1598500 3009340 ) M3M4_PR_M
- NEW met2 ( 2013190 3009340 ) M2M3_PR_M
- NEW met2 ( 1339290 203660 ) M2M3_PR_M
- NEW met2 ( 1365050 203660 ) M2M3_PR_M
- NEW met1 ( 1365050 206890 ) M1M2_PR
+ NEW met3 ( 1590220 205700 ) M3M4_PR_M
+ NEW met3 ( 1590220 3011380 ) M3M4_PR_M
+ NEW met2 ( 2013190 3011380 ) M2M3_PR_M
NEW met3 ( 1338140 198900 ) M3M4_PR_M
NEW met2 ( 1338370 198900 ) M2M3_PR_M
- NEW met1 ( 1407370 206890 ) M1M2_PR
- NEW met2 ( 1407370 198900 ) M2M3_PR_M
- NEW met3 ( 1414500 198900 ) M3M4_PR_M
+ NEW met2 ( 1386670 197540 ) M2M3_PR_M
+ NEW met3 ( 1413580 197540 ) M3M4_PR_M
NEW met3 ( 1414500 200260 ) M3M4_PR_M
NEW met3 ( 1338140 198900 ) RECT ( -390 -150 0 150 ) ;
- imem_data\[16\] ( mprj imem_data[16] ) ( mem dout0[16] ) + USE SIGNAL
- + ROUTED met3 ( 2499180 2160020 0 ) ( 2505390 * )
- NEW met2 ( 2505390 201110 ) ( * 2160020 )
+ + ROUTED met3 ( 2499180 2160020 0 ) ( 2514130 * )
+ NEW met2 ( 2514130 201110 ) ( * 2160020 )
NEW met2 ( 1351250 198900 ) ( * 201110 )
NEW met3 ( 1351020 198900 ) ( 1351250 * )
NEW met4 ( 1351020 198900 ) ( 1351070 * )
NEW met4 ( 1351070 198900 ) ( * 202300 0 )
- NEW met1 ( 1351250 201110 ) ( 2505390 * )
- NEW met1 ( 2505390 201110 ) M1M2_PR
- NEW met2 ( 2505390 2160020 ) M2M3_PR_M
+ NEW met1 ( 1351250 201110 ) ( 2514130 * )
+ NEW met1 ( 2514130 201110 ) M1M2_PR
+ NEW met2 ( 2514130 2160020 ) M2M3_PR_M
NEW met1 ( 1351250 201110 ) M1M2_PR
NEW met2 ( 1351250 198900 ) M2M3_PR_M
NEW met3 ( 1351020 198900 ) M3M4_PR_M
NEW met3 ( 1351250 198900 ) RECT ( 0 -150 390 150 ) ;
- imem_data\[17\] ( mprj imem_data[17] ) ( mem dout0[17] ) + USE SIGNAL
- + ROUTED met2 ( 1532950 203660 ) ( * 207060 )
- NEW met3 ( 1532950 203660 ) ( 1574580 * )
- NEW met3 ( 1574580 203660 ) ( * 205020 )
- NEW met2 ( 1770310 2999820 0 ) ( * 3011380 )
- NEW met3 ( 1363990 207060 ) ( 1532950 * )
- NEW met3 ( 1574580 205020 ) ( 1590220 * )
- NEW met3 ( 1590220 3011380 ) ( 1770310 * )
- NEW met4 ( 1590220 205020 ) ( * 3011380 )
- NEW met4 ( 1363990 207000 ) ( * 207060 )
- NEW met4 ( 1363990 205700 0 ) ( * 207000 )
- NEW met3 ( 1363990 207060 ) M3M4_PR_M
- NEW met2 ( 1532950 207060 ) M2M3_PR_M
- NEW met2 ( 1532950 203660 ) M2M3_PR_M
- NEW met2 ( 1770310 3011380 ) M2M3_PR_M
- NEW met3 ( 1590220 205020 ) M3M4_PR_M
- NEW met3 ( 1590220 3011380 ) M3M4_PR_M ;
+ + ROUTED met2 ( 1770310 2999820 0 ) ( * 3010700 )
+ NEW met4 ( 1569980 199580 ) ( * 3010700 )
+ NEW met3 ( 1569980 3010700 ) ( 1770310 * )
+ NEW met4 ( 1363900 198220 ) ( * 198900 )
+ NEW met4 ( 1363900 198900 ) ( 1363990 * )
+ NEW met4 ( 1363990 198900 ) ( * 202300 0 )
+ NEW met2 ( 1369650 198220 ) ( * 199580 )
+ NEW met3 ( 1363900 198220 ) ( 1369650 * )
+ NEW met3 ( 1369650 199580 ) ( 1569980 * )
+ NEW met3 ( 1569980 199580 ) M3M4_PR_M
+ NEW met3 ( 1569980 3010700 ) M3M4_PR_M
+ NEW met2 ( 1770310 3010700 ) M2M3_PR_M
+ NEW met3 ( 1363900 198220 ) M3M4_PR_M
+ NEW met2 ( 1369650 198220 ) M2M3_PR_M
+ NEW met2 ( 1369650 199580 ) M2M3_PR_M ;
- imem_data\[18\] ( mprj imem_data[18] ) ( mem dout0[18] ) + USE SIGNAL
- + ROUTED met2 ( 992910 201790 ) ( * 2819620 )
- NEW met3 ( 992910 2819620 ) ( 1000500 * 0 )
+ + ROUTED met2 ( 996130 201790 ) ( * 2819620 )
+ NEW met3 ( 996130 2819620 ) ( 1000500 * 0 )
NEW met2 ( 1377470 198900 ) ( * 201790 )
NEW met3 ( 1377470 198900 ) ( 1377700 * )
NEW met4 ( 1377590 198900 ) ( 1377700 * )
NEW met4 ( 1377590 198900 ) ( * 202300 0 )
- NEW met1 ( 992910 201790 ) ( 1377470 * )
- NEW met1 ( 992910 201790 ) M1M2_PR
- NEW met2 ( 992910 2819620 ) M2M3_PR_M
+ NEW met1 ( 996130 201790 ) ( 1377470 * )
+ NEW met1 ( 996130 201790 ) M1M2_PR
+ NEW met2 ( 996130 2819620 ) M2M3_PR_M
NEW met1 ( 1377470 201790 ) M1M2_PR
NEW met2 ( 1377470 198900 ) M2M3_PR_M
NEW met3 ( 1377700 198900 ) M3M4_PR_M
@@ -7689,43 +7673,41 @@
NEW met4 ( 1155060 198900 ) ( * 200260 )
NEW met4 ( 1153870 198900 ) ( 1155060 * )
NEW met4 ( 1153870 198900 ) ( * 202300 0 )
- NEW met2 ( 1576650 276000 ) ( 1577110 * )
- NEW met2 ( 1577110 204510 ) ( * 276000 )
- NEW met2 ( 1576650 276000 ) ( * 341530 )
- NEW met1 ( 1576650 341530 ) ( 1973630 * )
+ NEW met2 ( 1583550 204510 ) ( * 341530 )
+ NEW met1 ( 1583550 341530 ) ( 1973630 * )
NEW met2 ( 1973630 341530 ) ( * 1500420 0 )
- NEW met1 ( 1158970 204510 ) ( 1577110 * )
+ NEW met1 ( 1158970 204510 ) ( 1583550 * )
NEW met1 ( 1158970 204510 ) M1M2_PR
NEW met2 ( 1158970 200260 ) M2M3_PR_M
NEW met3 ( 1155060 200260 ) M3M4_PR_M
- NEW met1 ( 1577110 204510 ) M1M2_PR
- NEW met1 ( 1576650 341530 ) M1M2_PR
+ NEW met1 ( 1583550 204510 ) M1M2_PR
+ NEW met1 ( 1583550 341530 ) M1M2_PR
NEW met1 ( 1973630 341530 ) M1M2_PR ;
- imem_data\[20\] ( mprj imem_data[20] ) ( mem dout0[20] ) + USE SIGNAL
- + ROUTED met2 ( 991990 201450 ) ( * 2339540 )
- NEW met3 ( 991990 2339540 ) ( 1000500 * 0 )
+ + ROUTED met2 ( 992450 201450 ) ( * 2339540 )
+ NEW met3 ( 992450 2339540 ) ( 1000500 * 0 )
NEW met2 ( 1403230 198900 ) ( * 201450 )
NEW met3 ( 1403230 198900 ) ( 1403460 * )
NEW met4 ( 1403430 198900 ) ( 1403460 * )
NEW met4 ( 1403430 198900 ) ( * 202300 0 )
- NEW met1 ( 991990 201450 ) ( 1403230 * )
- NEW met1 ( 991990 201450 ) M1M2_PR
- NEW met2 ( 991990 2339540 ) M2M3_PR_M
+ NEW met1 ( 992450 201450 ) ( 1403230 * )
+ NEW met1 ( 992450 201450 ) M1M2_PR
+ NEW met2 ( 992450 2339540 ) M2M3_PR_M
NEW met1 ( 1403230 201450 ) M1M2_PR
NEW met2 ( 1403230 198900 ) M2M3_PR_M
NEW met3 ( 1403460 198900 ) M3M4_PR_M
NEW met3 ( 1403230 198900 ) RECT ( -390 -150 0 150 ) ;
- imem_data\[21\] ( mprj imem_data[21] ) ( mem dout0[21] ) + USE SIGNAL
- + ROUTED met3 ( 2499180 2400740 0 ) ( 2513670 * )
- NEW met2 ( 2513670 201450 ) ( * 2400740 )
+ + ROUTED met3 ( 2499180 2400740 0 ) ( 2513210 * )
+ NEW met2 ( 2513210 201450 ) ( * 2400740 )
NEW met2 ( 1418410 198220 ) ( * 201450 )
NEW met3 ( 1418180 198220 ) ( 1418410 * )
NEW met4 ( 1418180 198220 ) ( * 198900 )
NEW met4 ( 1417710 198900 ) ( 1418180 * )
NEW met4 ( 1417710 198900 ) ( * 202300 0 )
- NEW met1 ( 1418410 201450 ) ( 2513670 * )
- NEW met1 ( 2513670 201450 ) M1M2_PR
- NEW met2 ( 2513670 2400740 ) M2M3_PR_M
+ NEW met1 ( 1418410 201450 ) ( 2513210 * )
+ NEW met1 ( 2513210 201450 ) M1M2_PR
+ NEW met2 ( 2513210 2400740 ) M2M3_PR_M
NEW met1 ( 1418410 201450 ) M1M2_PR
NEW met2 ( 1418410 198220 ) M2M3_PR_M
NEW met3 ( 1418180 198220 ) M3M4_PR_M
@@ -7749,23 +7731,34 @@
NEW met1 ( 1890830 204170 ) M1M2_PR
NEW met3 ( 1431290 198220 ) RECT ( 0 -150 390 150 ) ;
- imem_data\[23\] ( mprj imem_data[23] ) ( mem dout0[23] ) + USE SIGNAL
- + ROUTED met2 ( 1480510 197540 ) ( * 199580 )
- NEW met3 ( 1443940 197540 ) ( 1480510 * )
- NEW met4 ( 1443940 197540 ) ( * 198900 )
+ + ROUTED met2 ( 1448770 206550 ) ( * 207060 )
+ NEW met1 ( 1444170 206550 ) ( 1448770 * )
+ NEW met2 ( 1444170 198220 ) ( * 206550 )
+ NEW met3 ( 1443940 198220 ) ( 1444170 * )
+ NEW met4 ( 1443940 198220 ) ( * 198900 )
NEW met4 ( 1443550 198900 ) ( 1443940 * )
NEW met4 ( 1443550 198900 ) ( * 202300 0 )
- NEW met3 ( 1533180 198220 ) ( * 199580 )
- NEW met3 ( 1533180 198220 ) ( 1569980 * )
- NEW met4 ( 1569980 198220 ) ( * 3008660 )
- NEW met3 ( 1480510 199580 ) ( 1533180 * )
+ NEW met2 ( 1532950 203660 ) ( * 207060 )
+ NEW met3 ( 1532950 203660 ) ( 1574580 * )
+ NEW met3 ( 1574580 203660 ) ( * 206380 )
+ NEW met4 ( 2120140 205700 ) ( * 3008660 )
+ NEW met3 ( 1448770 207060 ) ( 1532950 * )
+ NEW met3 ( 1628400 205700 ) ( * 206380 )
+ NEW met3 ( 1574580 206380 ) ( 1628400 * )
+ NEW met3 ( 1628400 205700 ) ( 2120140 * )
NEW met2 ( 2095070 2999820 0 ) ( * 3008660 )
- NEW met3 ( 1569980 3008660 ) ( 2095070 * )
- NEW met2 ( 1480510 199580 ) M2M3_PR_M
- NEW met2 ( 1480510 197540 ) M2M3_PR_M
- NEW met3 ( 1443940 197540 ) M3M4_PR_M
- NEW met3 ( 1569980 198220 ) M3M4_PR_M
- NEW met3 ( 1569980 3008660 ) M3M4_PR_M
- NEW met2 ( 2095070 3008660 ) M2M3_PR_M ;
+ NEW met3 ( 2095070 3008660 ) ( 2120140 * )
+ NEW met2 ( 1448770 207060 ) M2M3_PR_M
+ NEW met1 ( 1448770 206550 ) M1M2_PR
+ NEW met1 ( 1444170 206550 ) M1M2_PR
+ NEW met2 ( 1444170 198220 ) M2M3_PR_M
+ NEW met3 ( 1443940 198220 ) M3M4_PR_M
+ NEW met2 ( 1532950 207060 ) M2M3_PR_M
+ NEW met2 ( 1532950 203660 ) M2M3_PR_M
+ NEW met3 ( 2120140 205700 ) M3M4_PR_M
+ NEW met3 ( 2120140 3008660 ) M3M4_PR_M
+ NEW met2 ( 2095070 3008660 ) M2M3_PR_M
+ NEW met3 ( 1444170 198220 ) RECT ( 0 -150 390 150 ) ;
- imem_data\[24\] ( mprj imem_data[24] ) ( mem dout0[24] ) + USE SIGNAL
+ ROUTED met2 ( 1457050 198220 ) ( * 201790 )
NEW met3 ( 1456820 198220 ) ( 1457050 * )
@@ -7789,18 +7782,19 @@
NEW li1 ( 1522370 202810 ) L1M1_PR_MR
NEW met3 ( 1457050 198220 ) RECT ( 0 -150 390 150 ) ;
- imem_data\[25\] ( mprj imem_data[25] ) ( mem dout0[25] ) + USE SIGNAL
- + ROUTED met2 ( 1469470 198900 ) ( * 202470 )
- NEW met3 ( 1469470 198900 ) ( 1469700 * )
+ + ROUTED met2 ( 1469470 198220 ) ( * 202470 )
+ NEW met3 ( 1469470 198220 ) ( 1469700 * )
+ NEW met4 ( 1469700 198220 ) ( * 198900 )
NEW met4 ( 1469390 198900 ) ( 1469700 * )
NEW met4 ( 1469390 198900 ) ( * 202300 0 )
NEW met1 ( 1469470 202470 ) ( 2373830 * )
NEW met2 ( 2373830 1500420 ) ( 2379350 * 0 )
NEW met2 ( 2373830 202470 ) ( * 1500420 )
NEW met1 ( 1469470 202470 ) M1M2_PR
- NEW met2 ( 1469470 198900 ) M2M3_PR_M
- NEW met3 ( 1469700 198900 ) M3M4_PR_M
+ NEW met2 ( 1469470 198220 ) M2M3_PR_M
+ NEW met3 ( 1469700 198220 ) M3M4_PR_M
NEW met1 ( 2373830 202470 ) M1M2_PR
- NEW met3 ( 1469470 198900 ) RECT ( -390 -150 0 150 ) ;
+ NEW met3 ( 1469470 198220 ) RECT ( -390 -150 0 150 ) ;
- imem_data\[26\] ( mprj imem_data[26] ) ( mem dout0[26] ) + USE SIGNAL
+ ROUTED met2 ( 1482810 198220 ) ( * 205530 )
NEW met3 ( 1482580 198220 ) ( 1482810 * )
@@ -7816,16 +7810,16 @@
NEW met1 ( 1725230 205530 ) M1M2_PR
NEW met3 ( 1482810 198220 ) RECT ( 0 -150 390 150 ) ;
- imem_data\[27\] ( mprj imem_data[27] ) ( mem dout0[27] ) + USE SIGNAL
- + ROUTED met3 ( 2499180 1560260 0 ) ( 2515050 * )
- NEW met2 ( 2515050 201790 ) ( * 1560260 )
+ + ROUTED met3 ( 2499180 1560260 0 ) ( 2506310 * )
+ NEW met2 ( 2506310 201790 ) ( * 1560260 )
NEW met2 ( 1496610 198220 ) ( * 201790 )
NEW met3 ( 1496380 198220 ) ( 1496610 * )
NEW met4 ( 1496380 198220 ) ( * 198900 )
NEW met4 ( 1495910 198900 ) ( 1496380 * )
NEW met4 ( 1495910 198900 ) ( * 202300 0 )
- NEW met1 ( 1496610 201790 ) ( 2515050 * )
- NEW met1 ( 2515050 201790 ) M1M2_PR
- NEW met2 ( 2515050 1560260 ) M2M3_PR_M
+ NEW met1 ( 1496610 201790 ) ( 2506310 * )
+ NEW met1 ( 2506310 201790 ) M1M2_PR
+ NEW met2 ( 2506310 1560260 ) M2M3_PR_M
NEW met1 ( 1496610 201790 ) M1M2_PR
NEW met2 ( 1496610 198220 ) M2M3_PR_M
NEW met3 ( 1496380 198220 ) M3M4_PR_M
@@ -7834,9 +7828,9 @@
+ ROUTED met2 ( 993370 203830 ) ( * 2939300 )
NEW met2 ( 1509030 198220 ) ( * 203830 )
NEW met3 ( 1509030 198220 ) ( 1509260 * )
- NEW met4 ( 1509260 198220 ) ( * 198900 )
- NEW met4 ( 1509260 198900 ) ( 1509510 * )
- NEW met4 ( 1509510 198900 ) ( * 202300 0 )
+ NEW met4 ( 1509260 198220 ) ( * 200260 )
+ NEW met4 ( 1509260 200260 ) ( 1509510 * )
+ NEW met4 ( 1509510 200260 ) ( * 202300 0 )
NEW met3 ( 993370 2939300 ) ( 1000500 * 0 )
NEW met1 ( 993370 203830 ) ( 1509030 * )
NEW met1 ( 993370 203830 ) M1M2_PR
@@ -7846,21 +7840,21 @@
NEW met3 ( 1509260 198220 ) M3M4_PR_M
NEW met3 ( 1509030 198220 ) RECT ( -390 -150 0 150 ) ;
- imem_data\[29\] ( mprj imem_data[29] ) ( mem dout0[29] ) + USE SIGNAL
- + ROUTED met2 ( 992450 203490 ) ( * 2459220 )
- NEW li1 ( 1485570 202810 ) ( * 203490 )
- NEW li1 ( 1485570 202810 ) ( 1486490 * )
- NEW met1 ( 1486490 202810 ) ( 1521910 * )
+ + ROUTED met2 ( 992910 203490 ) ( * 2459220 )
+ NEW li1 ( 1483730 202810 ) ( * 203490 )
+ NEW li1 ( 1483730 202810 ) ( 1484650 * )
+ NEW met1 ( 1484650 202810 ) ( 1521910 * )
NEW met2 ( 1521910 198220 ) ( * 202810 )
NEW met3 ( 1521910 198220 ) ( 1522140 * )
- NEW met4 ( 1522140 198220 ) ( * 198900 )
- NEW met4 ( 1522140 198900 ) ( 1522430 * )
- NEW met4 ( 1522430 198900 ) ( * 202300 0 )
- NEW met3 ( 992450 2459220 ) ( 1000500 * 0 )
- NEW met1 ( 992450 203490 ) ( 1485570 * )
- NEW met1 ( 992450 203490 ) M1M2_PR
- NEW met2 ( 992450 2459220 ) M2M3_PR_M
- NEW li1 ( 1485570 203490 ) L1M1_PR_MR
- NEW li1 ( 1486490 202810 ) L1M1_PR_MR
+ NEW met4 ( 1522140 198220 ) ( * 200260 )
+ NEW met4 ( 1522140 200260 ) ( 1522430 * )
+ NEW met4 ( 1522430 200260 ) ( * 202300 0 )
+ NEW met3 ( 992910 2459220 ) ( 1000500 * 0 )
+ NEW met1 ( 992910 203490 ) ( 1483730 * )
+ NEW met1 ( 992910 203490 ) M1M2_PR
+ NEW met2 ( 992910 2459220 ) M2M3_PR_M
+ NEW li1 ( 1483730 203490 ) L1M1_PR_MR
+ NEW li1 ( 1484650 202810 ) L1M1_PR_MR
NEW met1 ( 1521910 202810 ) M1M2_PR
NEW met2 ( 1521910 198220 ) M2M3_PR_M
NEW met3 ( 1522140 198220 ) M3M4_PR_M
@@ -7871,55 +7865,51 @@
NEW met4 ( 1166100 198900 ) ( * 200260 )
NEW met4 ( 1166100 198900 ) ( 1166790 * )
NEW met4 ( 1166790 198900 ) ( * 202300 0 )
- NEW met2 ( 996590 200770 ) ( * 2219860 )
- NEW met3 ( 996590 2219860 ) ( 1000500 * 0 )
- NEW met1 ( 996590 200770 ) ( 1166330 * )
- NEW met1 ( 996590 200770 ) M1M2_PR
- NEW met2 ( 996590 2219860 ) M2M3_PR_M
+ NEW met2 ( 997510 200770 ) ( * 2219860 )
+ NEW met3 ( 997510 2219860 ) ( 1000500 * 0 )
+ NEW met1 ( 997510 200770 ) ( 1166330 * )
+ NEW met1 ( 997510 200770 ) M1M2_PR
+ NEW met2 ( 997510 2219860 ) M2M3_PR_M
NEW met1 ( 1166330 200770 ) M1M2_PR
NEW met2 ( 1166330 200260 ) M2M3_PR_M
NEW met3 ( 1166100 200260 ) M3M4_PR_M
NEW met3 ( 1166330 200260 ) RECT ( 0 -150 390 150 ) ;
- imem_data\[30\] ( mprj imem_data[30] ) ( mem dout0[30] ) + USE SIGNAL
+ ROUTED met4 ( 1535350 198900 ) ( * 202300 0 )
- NEW met4 ( 1535350 198900 ) ( 1536860 * )
- NEW met4 ( 1536860 198900 ) ( * 200260 )
- NEW met3 ( 1536860 200260 ) ( 1537090 * )
- NEW met2 ( 1537090 200260 ) ( * 203830 )
- NEW met1 ( 1537090 203830 ) ( 1573890 * )
- NEW met3 ( 1574580 549100 ) ( * 549780 )
- NEW met3 ( 1574350 549780 ) ( 1574580 * )
- NEW met2 ( 1573890 549780 ) ( 1574350 * )
- NEW met2 ( 1573890 203830 ) ( * 549780 )
+ NEW met3 ( 1535250 198900 ) ( 1535350 * )
+ NEW met2 ( 1535250 198900 ) ( * 203830 )
+ NEW met1 ( 1535250 203830 ) ( 1575730 * )
+ NEW met2 ( 1575730 549100 ) ( 1576190 * )
+ NEW met2 ( 1575730 203830 ) ( * 549100 )
NEW met3 ( 1203130 2996420 ) ( 1206580 * )
NEW met2 ( 1201750 2996420 0 ) ( 1203130 * )
NEW met4 ( 1206580 552500 ) ( * 2996420 )
NEW met2 ( 1215550 549100 ) ( * 552500 )
NEW met3 ( 1206580 552500 ) ( 1215550 * )
- NEW met3 ( 1215550 549100 ) ( 1574580 * )
- NEW met3 ( 1536860 200260 ) M3M4_PR_M
- NEW met2 ( 1537090 200260 ) M2M3_PR_M
- NEW met1 ( 1537090 203830 ) M1M2_PR
- NEW met1 ( 1573890 203830 ) M1M2_PR
- NEW met2 ( 1574350 549780 ) M2M3_PR_M
+ NEW met3 ( 1215550 549100 ) ( 1576190 * )
+ NEW met3 ( 1535350 198900 ) M3M4_PR_M
+ NEW met2 ( 1535250 198900 ) M2M3_PR_M
+ NEW met1 ( 1535250 203830 ) M1M2_PR
+ NEW met1 ( 1575730 203830 ) M1M2_PR
+ NEW met2 ( 1576190 549100 ) M2M3_PR_M
NEW met3 ( 1206580 2996420 ) M3M4_PR_M
NEW met2 ( 1203130 2996420 ) M2M3_PR_M
NEW met3 ( 1206580 552500 ) M3M4_PR_M
NEW met2 ( 1215550 552500 ) M2M3_PR_M
NEW met2 ( 1215550 549100 ) M2M3_PR_M
- NEW met3 ( 1536860 200260 ) RECT ( -390 -150 0 150 ) ;
+ NEW met3 ( 1535250 198900 ) RECT ( -520 -150 0 150 ) ;
- imem_data\[31\] ( mprj imem_data[31] ) ( mem dout0[31] ) + USE SIGNAL
- + ROUTED met1 ( 1573430 254830 ) ( 1576650 * )
+ + ROUTED met1 ( 1574810 254830 ) ( 1576650 * )
NEW met2 ( 1576650 234260 ) ( * 254830 )
NEW met3 ( 1576420 234260 ) ( 1576650 * )
NEW met3 ( 1576420 233510 0 ) ( * 234260 )
- NEW met1 ( 1567910 1490390 ) ( 1573430 * )
+ NEW met1 ( 1567910 1490390 ) ( 1574810 * )
NEW met2 ( 1567910 1490390 ) ( * 1500420 0 )
- NEW met2 ( 1573430 254830 ) ( * 1490390 )
- NEW met1 ( 1573430 254830 ) M1M2_PR
+ NEW met2 ( 1574810 254830 ) ( * 1490390 )
+ NEW met1 ( 1574810 254830 ) M1M2_PR
NEW met1 ( 1576650 254830 ) M1M2_PR
NEW met2 ( 1576650 234260 ) M2M3_PR_M
- NEW met1 ( 1573430 1490390 ) M1M2_PR
+ NEW met1 ( 1574810 1490390 ) M1M2_PR
NEW met1 ( 1567910 1490390 ) M1M2_PR ;
- imem_data\[3\] ( mprj imem_data[3] ) ( mem dout0[3] ) + USE SIGNAL
+ ROUTED met2 ( 1186570 200260 ) ( * 203660 )
@@ -7930,13 +7920,13 @@
NEW li1 ( 1435430 202470 ) ( * 204170 )
NEW met1 ( 1435430 202470 ) ( 1459810 * )
NEW met1 ( 1459810 202470 ) ( * 202810 )
- NEW met2 ( 1579870 200260 ) ( * 203490 )
+ NEW met2 ( 1578030 200260 ) ( * 203490 )
NEW met4 ( 2255380 203660 ) ( * 2996420 )
- NEW met2 ( 1486030 202810 ) ( * 203490 )
- NEW met1 ( 1459810 202810 ) ( 1486030 * )
- NEW met1 ( 1486030 203490 ) ( 1579870 * )
+ NEW met2 ( 1484190 202810 ) ( * 203490 )
+ NEW met1 ( 1459810 202810 ) ( 1484190 * )
+ NEW met1 ( 1484190 203490 ) ( 1578030 * )
NEW met3 ( 1628400 200260 ) ( * 203660 )
- NEW met3 ( 1579870 200260 ) ( 1628400 * )
+ NEW met3 ( 1578030 200260 ) ( 1628400 * )
NEW met3 ( 1628400 203660 ) ( 2255380 * )
NEW met2 ( 2256530 2996420 ) ( 2256990 * 0 )
NEW met3 ( 2255380 2996420 ) ( 2256530 * )
@@ -7954,12 +7944,12 @@
NEW met3 ( 1180820 200260 ) M3M4_PR_M
NEW li1 ( 1435430 204170 ) L1M1_PR_MR
NEW li1 ( 1435430 202470 ) L1M1_PR_MR
- NEW met1 ( 1579870 203490 ) M1M2_PR
- NEW met2 ( 1579870 200260 ) M2M3_PR_M
+ NEW met1 ( 1578030 203490 ) M1M2_PR
+ NEW met2 ( 1578030 200260 ) M2M3_PR_M
NEW met3 ( 2255380 203660 ) M3M4_PR_M
NEW met3 ( 2255380 2996420 ) M3M4_PR_M
- NEW met1 ( 1486030 202810 ) M1M2_PR
- NEW met1 ( 1486030 203490 ) M1M2_PR
+ NEW met1 ( 1484190 202810 ) M1M2_PR
+ NEW met1 ( 1484190 203490 ) M1M2_PR
NEW met2 ( 2256530 2996420 ) M2M3_PR_M
NEW met2 ( 1318130 203660 ) M2M3_PR_M
NEW met1 ( 1319050 204170 ) M1M2_PR
@@ -7973,62 +7963,64 @@
NEW met4 ( 1191860 198900 ) ( * 200260 )
NEW met4 ( 1191860 198900 ) ( 1193310 * )
NEW met4 ( 1193310 198900 ) ( * 202300 0 )
- NEW met2 ( 1574350 204850 ) ( * 517500 )
NEW met3 ( 1574580 551820 ) ( * 552500 )
- NEW met3 ( 1574580 551820 ) ( 1574810 * )
- NEW met2 ( 1574810 517500 ) ( * 551820 )
- NEW met2 ( 1574350 517500 ) ( 1574810 * )
+ NEW met3 ( 1574580 551820 ) ( 1575270 * )
+ NEW met2 ( 1575270 204850 ) ( * 551820 )
NEW met3 ( 1527890 2996420 ) ( 1531340 * )
NEW met2 ( 1526510 2996420 0 ) ( 1527890 * )
NEW met3 ( 1531340 552500 ) ( 1574580 * )
NEW met4 ( 1531340 552500 ) ( * 2996420 )
- NEW met1 ( 1193470 204850 ) ( 1574350 * )
+ NEW met1 ( 1193470 204850 ) ( 1575270 * )
NEW met1 ( 1193470 204850 ) M1M2_PR
NEW met2 ( 1193470 200260 ) M2M3_PR_M
NEW met3 ( 1191860 200260 ) M3M4_PR_M
- NEW met1 ( 1574350 204850 ) M1M2_PR
- NEW met2 ( 1574810 551820 ) M2M3_PR_M
+ NEW met1 ( 1575270 204850 ) M1M2_PR
+ NEW met2 ( 1575270 551820 ) M2M3_PR_M
NEW met3 ( 1531340 2996420 ) M3M4_PR_M
NEW met2 ( 1527890 2996420 ) M2M3_PR_M
NEW met3 ( 1531340 552500 ) M3M4_PR_M ;
- imem_data\[5\] ( mprj imem_data[5] ) ( mem dout0[5] ) + USE SIGNAL
- + ROUTED met3 ( 2499180 2640100 0 ) ( 2512750 * )
- NEW met2 ( 2512750 200770 ) ( * 2640100 )
+ + ROUTED met3 ( 2499180 2640100 0 ) ( 2512290 * )
+ NEW met2 ( 2512290 200770 ) ( * 2640100 )
NEW met2 ( 1207270 200260 ) ( * 200770 )
NEW met3 ( 1207270 200260 ) ( 1207500 * )
NEW met4 ( 1206230 200260 ) ( 1207500 * )
NEW met4 ( 1206230 200260 ) ( * 202300 0 )
- NEW met1 ( 1207270 200770 ) ( 2512750 * )
- NEW met1 ( 2512750 200770 ) M1M2_PR
- NEW met2 ( 2512750 2640100 ) M2M3_PR_M
+ NEW met1 ( 1207270 200770 ) ( 2512290 * )
+ NEW met1 ( 2512290 200770 ) M1M2_PR
+ NEW met2 ( 2512290 2640100 ) M2M3_PR_M
NEW met1 ( 1207270 200770 ) M1M2_PR
NEW met2 ( 1207270 200260 ) M2M3_PR_M
NEW met3 ( 1207500 200260 ) M3M4_PR_M
NEW met3 ( 1207270 200260 ) RECT ( -390 -150 0 150 ) ;
- imem_data\[6\] ( mprj imem_data[6] ) ( mem dout0[6] ) + USE SIGNAL
- + ROUTED met3 ( 1242460 199580 ) ( * 200260 )
- NEW met3 ( 1471540 198900 ) ( * 199580 )
- NEW met3 ( 1532260 197540 ) ( * 198900 )
- NEW met3 ( 1532260 197540 ) ( 1574580 * )
- NEW met2 ( 1932230 2999820 0 ) ( * 3010020 )
- NEW met4 ( 1574580 197540 ) ( * 3010020 )
- NEW met3 ( 1241540 199580 ) ( * 200260 )
- NEW met3 ( 1232340 200260 ) ( 1241540 * )
+ + ROUTED met3 ( 1245220 199580 ) ( * 200260 )
+ NEW met3 ( 1532260 198220 ) ( * 198900 )
+ NEW met3 ( 1532260 198220 ) ( 1574580 * )
+ NEW met2 ( 1932230 2999820 0 ) ( * 3009340 )
+ NEW met4 ( 1574580 198220 ) ( * 3009340 )
+ NEW met3 ( 1242000 199580 ) ( 1245220 * )
+ NEW met3 ( 1242000 199580 ) ( * 200260 )
+ NEW met3 ( 1232340 200260 ) ( 1242000 * )
NEW met3 ( 1232340 199580 ) ( * 200260 )
NEW met3 ( 1227740 199580 ) ( 1232340 * )
NEW met3 ( 1227740 199580 ) ( * 200260 )
NEW met3 ( 1220380 200260 ) ( 1227740 * )
NEW met4 ( 1219150 200260 ) ( 1220380 * )
NEW met4 ( 1219150 200260 ) ( * 202300 0 )
- NEW met3 ( 1241540 199580 ) ( 1242460 * )
- NEW met3 ( 1471540 198900 ) ( 1532260 * )
- NEW met3 ( 1574580 3010020 ) ( 1932230 * )
- NEW met3 ( 1242460 200260 ) ( 1366200 * )
+ NEW met3 ( 1574580 3009340 ) ( 1932230 * )
+ NEW met3 ( 1245220 200260 ) ( 1366200 * )
+ NEW met3 ( 1414500 198900 ) ( 1532260 * )
NEW met3 ( 1366200 199580 ) ( * 200260 )
- NEW met3 ( 1366200 199580 ) ( 1471540 * )
- NEW met3 ( 1574580 197540 ) M3M4_PR_M
- NEW met3 ( 1574580 3010020 ) M3M4_PR_M
- NEW met2 ( 1932230 3010020 ) M2M3_PR_M
+ NEW met3 ( 1366200 199580 ) ( 1368500 * )
+ NEW met3 ( 1368500 198900 ) ( * 199580 )
+ NEW met3 ( 1368500 198900 ) ( 1372180 * )
+ NEW met3 ( 1372180 198220 ) ( * 198900 )
+ NEW met3 ( 1372180 198220 ) ( 1414500 * )
+ NEW met3 ( 1414500 198220 ) ( * 198900 )
+ NEW met3 ( 1574580 198220 ) M3M4_PR_M
+ NEW met3 ( 1574580 3009340 ) M3M4_PR_M
+ NEW met2 ( 1932230 3009340 ) M2M3_PR_M
NEW met3 ( 1220380 200260 ) M3M4_PR_M ;
- imem_data\[7\] ( mprj imem_data[7] ) ( mem dout0[7] ) + USE SIGNAL
+ ROUTED met2 ( 999810 203150 ) ( * 3008490 )
@@ -8046,62 +8038,57 @@
NEW met2 ( 1228430 200260 ) M2M3_PR_M
NEW met3 ( 1231420 200260 ) M3M4_PR_M ;
- imem_data\[8\] ( mprj imem_data[8] ) ( mem dout0[8] ) + USE SIGNAL
- + ROUTED met2 ( 1244990 198220 ) ( * 202810 )
- NEW met3 ( 1244990 198220 ) ( 1245220 * )
- NEW met4 ( 1245220 198220 ) ( * 198900 )
- NEW met4 ( 1245220 198900 ) ( 1245670 * )
+ + ROUTED met2 ( 1243610 200260 ) ( * 202810 )
+ NEW met3 ( 1243610 200260 ) ( 1244300 * )
+ NEW met4 ( 1244300 198900 ) ( * 200260 )
+ NEW met4 ( 1244300 198900 ) ( 1245670 * )
NEW met4 ( 1245670 198900 ) ( * 202300 0 )
- NEW met2 ( 1000270 202810 ) ( * 1500420 0 )
- NEW met1 ( 1000270 202810 ) ( 1244990 * )
- NEW met1 ( 1000270 202810 ) M1M2_PR
- NEW met1 ( 1244990 202810 ) M1M2_PR
- NEW met2 ( 1244990 198220 ) M2M3_PR_M
- NEW met3 ( 1245220 198220 ) M3M4_PR_M
- NEW met3 ( 1244990 198220 ) RECT ( -390 -150 0 150 ) ;
+ NEW met2 ( 1000270 1483590 ) ( * 1500420 0 )
+ NEW met1 ( 1003950 202810 ) ( 1243610 * )
+ NEW met1 ( 1000270 1483590 ) ( 1003950 * )
+ NEW met2 ( 1003950 202810 ) ( * 1483590 )
+ NEW met1 ( 1243610 202810 ) M1M2_PR
+ NEW met2 ( 1243610 200260 ) M2M3_PR_M
+ NEW met3 ( 1244300 200260 ) M3M4_PR_M
+ NEW met1 ( 1000270 1483590 ) M1M2_PR
+ NEW met1 ( 1003950 202810 ) M1M2_PR
+ NEW met1 ( 1003950 1483590 ) M1M2_PR ;
- imem_data\[9\] ( mprj imem_data[9] ) ( mem dout0[9] ) + USE SIGNAL
+ ROUTED met2 ( 1259250 198220 ) ( * 205190 )
NEW met3 ( 1259020 198220 ) ( 1259250 * )
NEW met4 ( 1259020 198220 ) ( * 198900 )
NEW met4 ( 1258590 198900 ) ( 1259020 * )
NEW met4 ( 1258590 198900 ) ( * 202300 0 )
- NEW met3 ( 1365970 2996420 ) ( 1375860 * )
- NEW met2 ( 1364590 2996420 0 ) ( 1365970 * )
- NEW met2 ( 1543990 1062330 ) ( * 1076270 )
- NEW met1 ( 1543990 1062330 ) ( 1556870 * )
- NEW met4 ( 1375860 1458940 ) ( * 2996420 )
- NEW met1 ( 1438650 1214310 ) ( 1466250 * )
- NEW met2 ( 1466250 1190170 ) ( * 1214310 )
- NEW met2 ( 1438650 1214310 ) ( * 1421370 )
- NEW met1 ( 1556870 1041930 ) ( 1570210 * )
- NEW met2 ( 1556870 1041930 ) ( * 1062330 )
- NEW met2 ( 1570210 205190 ) ( * 1041930 )
- NEW met3 ( 1375860 1458940 ) ( 1411050 * )
- NEW met1 ( 1528350 1076270 ) ( 1543990 * )
- NEW met1 ( 1466250 1190170 ) ( 1528350 * )
- NEW met2 ( 1411050 1421370 ) ( * 1458940 )
- NEW met1 ( 1411050 1421370 ) ( 1438650 * )
- NEW met2 ( 1528350 1076270 ) ( * 1190170 )
+ NEW met2 ( 1364590 2999820 0 ) ( * 3008660 )
+ NEW met1 ( 1452450 1317670 ) ( 1476830 * )
+ NEW met2 ( 1476830 1300670 ) ( * 1317670 )
+ NEW met2 ( 1452450 1317670 ) ( * 1424260 )
+ NEW met1 ( 1562850 1133050 ) ( 1570210 * )
+ NEW met2 ( 1570210 205190 ) ( * 1133050 )
+ NEW met2 ( 1562850 1133050 ) ( * 1265990 )
+ NEW met3 ( 1364590 3008660 ) ( 1389660 * )
+ NEW met1 ( 1507650 1265990 ) ( 1562850 * )
+ NEW met3 ( 1389660 1424260 ) ( 1452450 * )
+ NEW met4 ( 1389660 1424260 ) ( * 3008660 )
+ NEW met1 ( 1476830 1300670 ) ( 1507650 * )
+ NEW met2 ( 1507650 1265990 ) ( * 1300670 )
NEW met1 ( 1259250 205190 ) ( 1570210 * )
NEW met1 ( 1259250 205190 ) M1M2_PR
NEW met2 ( 1259250 198220 ) M2M3_PR_M
NEW met3 ( 1259020 198220 ) M3M4_PR_M
- NEW met3 ( 1375860 1458940 ) M3M4_PR_M
- NEW met3 ( 1375860 2996420 ) M3M4_PR_M
- NEW met2 ( 1365970 2996420 ) M2M3_PR_M
- NEW met1 ( 1466250 1190170 ) M1M2_PR
+ NEW met2 ( 1364590 3008660 ) M2M3_PR_M
NEW met1 ( 1570210 205190 ) M1M2_PR
- NEW met1 ( 1543990 1076270 ) M1M2_PR
- NEW met1 ( 1543990 1062330 ) M1M2_PR
- NEW met1 ( 1556870 1062330 ) M1M2_PR
- NEW met1 ( 1438650 1214310 ) M1M2_PR
- NEW met1 ( 1466250 1214310 ) M1M2_PR
- NEW met1 ( 1438650 1421370 ) M1M2_PR
- NEW met1 ( 1556870 1041930 ) M1M2_PR
- NEW met1 ( 1570210 1041930 ) M1M2_PR
- NEW met2 ( 1411050 1458940 ) M2M3_PR_M
- NEW met1 ( 1528350 1076270 ) M1M2_PR
- NEW met1 ( 1528350 1190170 ) M1M2_PR
- NEW met1 ( 1411050 1421370 ) M1M2_PR
+ NEW met1 ( 1562850 1265990 ) M1M2_PR
+ NEW met1 ( 1452450 1317670 ) M1M2_PR
+ NEW met1 ( 1476830 1317670 ) M1M2_PR
+ NEW met1 ( 1476830 1300670 ) M1M2_PR
+ NEW met2 ( 1452450 1424260 ) M2M3_PR_M
+ NEW met1 ( 1562850 1133050 ) M1M2_PR
+ NEW met1 ( 1570210 1133050 ) M1M2_PR
+ NEW met3 ( 1389660 3008660 ) M3M4_PR_M
+ NEW met1 ( 1507650 1265990 ) M1M2_PR
+ NEW met3 ( 1389660 1424260 ) M3M4_PR_M
+ NEW met1 ( 1507650 1300670 ) M1M2_PR
NEW met3 ( 1259250 198220 ) RECT ( 0 -150 390 150 ) ;
- io_in[0] ( PIN io_in[0] ) + USE SIGNAL ;
- io_in[10] ( PIN io_in[10] ) + USE SIGNAL ;
@@ -8217,7 +8204,19 @@
- io_out[7] ( PIN io_out[7] ) + USE SIGNAL ;
- io_out[8] ( PIN io_out[8] ) + USE SIGNAL ;
- io_out[9] ( PIN io_out[9] ) + USE SIGNAL ;
- - la_data_in[0] ( PIN la_data_in[0] ) + USE SIGNAL ;
+ - la_data_in[0] ( PIN la_data_in[0] ) ( mem din0[0] ) + USE SIGNAL
+ + ROUTED met2 ( 629510 2380 0 ) ( * 17510 )
+ NEW met1 ( 1107450 17170 ) ( * 17510 )
+ NEW met1 ( 1107450 17170 ) ( 1125390 * )
+ NEW met1 ( 629510 17510 ) ( 1107450 * )
+ NEW met3 ( 1125390 198900 ) ( 1131140 * )
+ NEW met4 ( 1131140 198900 ) ( 1131430 * )
+ NEW met4 ( 1131430 198900 ) ( * 202300 0 )
+ NEW met2 ( 1125390 17170 ) ( * 198900 )
+ NEW met1 ( 629510 17510 ) M1M2_PR
+ NEW met1 ( 1125390 17170 ) M1M2_PR
+ NEW met2 ( 1125390 198900 ) M2M3_PR_M
+ NEW met3 ( 1131140 198900 ) M3M4_PR_M ;
- la_data_in[100] ( PIN la_data_in[100] ) + USE SIGNAL ;
- la_data_in[101] ( PIN la_data_in[101] ) + USE SIGNAL ;
- la_data_in[102] ( PIN la_data_in[102] ) + USE SIGNAL ;
@@ -8228,7 +8227,18 @@
- la_data_in[107] ( PIN la_data_in[107] ) + USE SIGNAL ;
- la_data_in[108] ( PIN la_data_in[108] ) + USE SIGNAL ;
- la_data_in[109] ( PIN la_data_in[109] ) + USE SIGNAL ;
- - la_data_in[10] ( PIN la_data_in[10] ) + USE SIGNAL ;
+ - la_data_in[10] ( PIN la_data_in[10] ) ( mem din0[10] ) + USE SIGNAL
+ + ROUTED met2 ( 806610 2380 0 ) ( * 17850 )
+ NEW met3 ( 1262700 198900 ) ( 1262930 * )
+ NEW met4 ( 1262670 198900 ) ( 1262700 * )
+ NEW met4 ( 1262670 198900 ) ( * 202300 0 )
+ NEW met2 ( 1262930 17850 ) ( * 198900 )
+ NEW met1 ( 806610 17850 ) ( 1262930 * )
+ NEW met1 ( 806610 17850 ) M1M2_PR
+ NEW met1 ( 1262930 17850 ) M1M2_PR
+ NEW met2 ( 1262930 198900 ) M2M3_PR_M
+ NEW met3 ( 1262700 198900 ) M3M4_PR_M
+ NEW met3 ( 1262930 198900 ) RECT ( 0 -150 390 150 ) ;
- la_data_in[110] ( PIN la_data_in[110] ) + USE SIGNAL ;
- la_data_in[111] ( PIN la_data_in[111] ) + USE SIGNAL ;
- la_data_in[112] ( PIN la_data_in[112] ) + USE SIGNAL ;
@@ -8239,7 +8249,17 @@
- la_data_in[117] ( PIN la_data_in[117] ) + USE SIGNAL ;
- la_data_in[118] ( PIN la_data_in[118] ) + USE SIGNAL ;
- la_data_in[119] ( PIN la_data_in[119] ) + USE SIGNAL ;
- - la_data_in[11] ( PIN la_data_in[11] ) + USE SIGNAL ;
+ - la_data_in[11] ( PIN la_data_in[11] ) ( mem din0[11] ) + USE SIGNAL
+ + ROUTED met3 ( 1269830 198900 ) ( 1275580 * )
+ NEW met4 ( 1275580 198900 ) ( 1275590 * )
+ NEW met4 ( 1275590 198900 ) ( * 202300 0 )
+ NEW met2 ( 1269830 18190 ) ( * 198900 )
+ NEW met2 ( 824550 2380 0 ) ( * 18190 )
+ NEW met1 ( 824550 18190 ) ( 1269830 * )
+ NEW met1 ( 1269830 18190 ) M1M2_PR
+ NEW met2 ( 1269830 198900 ) M2M3_PR_M
+ NEW met3 ( 1275580 198900 ) M3M4_PR_M
+ NEW met1 ( 824550 18190 ) M1M2_PR ;
- la_data_in[120] ( PIN la_data_in[120] ) + USE SIGNAL ;
- la_data_in[121] ( PIN la_data_in[121] ) + USE SIGNAL ;
- la_data_in[122] ( PIN la_data_in[122] ) + USE SIGNAL ;
@@ -8248,50 +8268,453 @@
- la_data_in[125] ( PIN la_data_in[125] ) + USE SIGNAL ;
- la_data_in[126] ( PIN la_data_in[126] ) + USE SIGNAL ;
- la_data_in[127] ( PIN la_data_in[127] ) + USE SIGNAL ;
- - la_data_in[12] ( PIN la_data_in[12] ) + USE SIGNAL ;
- - la_data_in[13] ( PIN la_data_in[13] ) + USE SIGNAL ;
- - la_data_in[14] ( PIN la_data_in[14] ) + USE SIGNAL ;
- - la_data_in[15] ( PIN la_data_in[15] ) + USE SIGNAL ;
- - la_data_in[16] ( PIN la_data_in[16] ) + USE SIGNAL ;
- - la_data_in[17] ( PIN la_data_in[17] ) + USE SIGNAL ;
- - la_data_in[18] ( PIN la_data_in[18] ) + USE SIGNAL ;
- - la_data_in[19] ( PIN la_data_in[19] ) + USE SIGNAL ;
- - la_data_in[1] ( PIN la_data_in[1] ) + USE SIGNAL ;
- - la_data_in[20] ( PIN la_data_in[20] ) + USE SIGNAL ;
- - la_data_in[21] ( PIN la_data_in[21] ) + USE SIGNAL ;
- - la_data_in[22] ( PIN la_data_in[22] ) + USE SIGNAL ;
- - la_data_in[23] ( PIN la_data_in[23] ) + USE SIGNAL ;
- - la_data_in[24] ( PIN la_data_in[24] ) + USE SIGNAL ;
- - la_data_in[25] ( PIN la_data_in[25] ) + USE SIGNAL ;
- - la_data_in[26] ( PIN la_data_in[26] ) + USE SIGNAL ;
- - la_data_in[27] ( PIN la_data_in[27] ) + USE SIGNAL ;
- - la_data_in[28] ( PIN la_data_in[28] ) + USE SIGNAL ;
- - la_data_in[29] ( PIN la_data_in[29] ) + USE SIGNAL ;
- - la_data_in[2] ( PIN la_data_in[2] ) + USE SIGNAL ;
- - la_data_in[30] ( PIN la_data_in[30] ) + USE SIGNAL ;
- - la_data_in[31] ( PIN la_data_in[31] ) + USE SIGNAL ;
- - la_data_in[32] ( PIN la_data_in[32] ) + USE SIGNAL ;
+ - la_data_in[12] ( PIN la_data_in[12] ) ( mem din0[12] ) + USE SIGNAL
+ + ROUTED met3 ( 1283630 198900 ) ( 1288460 * )
+ NEW met4 ( 1288460 198900 ) ( 1288510 * )
+ NEW met4 ( 1288510 198900 ) ( * 202300 0 )
+ NEW met2 ( 1283630 19550 ) ( * 198900 )
+ NEW met2 ( 842030 2380 0 ) ( * 19550 )
+ NEW met1 ( 842030 19550 ) ( 1283630 * )
+ NEW met1 ( 1283630 19550 ) M1M2_PR
+ NEW met2 ( 1283630 198900 ) M2M3_PR_M
+ NEW met3 ( 1288460 198900 ) M3M4_PR_M
+ NEW met1 ( 842030 19550 ) M1M2_PR ;
+ - la_data_in[13] ( PIN la_data_in[13] ) ( mem din0[13] ) + USE SIGNAL
+ + ROUTED met2 ( 859970 2380 0 ) ( * 19890 )
+ NEW met1 ( 859970 19890 ) ( 1297430 * )
+ NEW met3 ( 1297430 198900 ) ( 1301340 * )
+ NEW met4 ( 1301340 198900 ) ( 1301430 * )
+ NEW met4 ( 1301430 198900 ) ( * 202300 0 )
+ NEW met2 ( 1297430 19890 ) ( * 198900 )
+ NEW met1 ( 859970 19890 ) M1M2_PR
+ NEW met1 ( 1297430 19890 ) M1M2_PR
+ NEW met2 ( 1297430 198900 ) M2M3_PR_M
+ NEW met3 ( 1301340 198900 ) M3M4_PR_M ;
+ - la_data_in[14] ( PIN la_data_in[14] ) ( mem din0[14] ) + USE SIGNAL
+ + ROUTED met2 ( 877450 2380 0 ) ( * 20570 )
+ NEW met1 ( 877450 20570 ) ( 1311230 * )
+ NEW met3 ( 1311230 198900 ) ( 1315140 * )
+ NEW met4 ( 1315030 198900 ) ( 1315140 * )
+ NEW met4 ( 1315030 198900 ) ( * 202300 0 )
+ NEW met2 ( 1311230 20570 ) ( * 198900 )
+ NEW met1 ( 877450 20570 ) M1M2_PR
+ NEW met1 ( 1311230 20570 ) M1M2_PR
+ NEW met2 ( 1311230 198900 ) M2M3_PR_M
+ NEW met3 ( 1315140 198900 ) M3M4_PR_M ;
+ - la_data_in[15] ( PIN la_data_in[15] ) ( mem din0[15] ) + USE SIGNAL
+ + ROUTED met2 ( 895390 2380 0 ) ( * 20230 )
+ NEW met1 ( 895390 20230 ) ( 1325030 * )
+ NEW met3 ( 1325030 193460 ) ( 1328020 * )
+ NEW met4 ( 1328020 193460 ) ( * 198900 )
+ NEW met4 ( 1328020 198900 ) ( 1328630 * )
+ NEW met4 ( 1328630 198900 ) ( * 202300 0 )
+ NEW met2 ( 1325030 20230 ) ( * 193460 )
+ NEW met1 ( 895390 20230 ) M1M2_PR
+ NEW met1 ( 1325030 20230 ) M1M2_PR
+ NEW met2 ( 1325030 193460 ) M2M3_PR_M
+ NEW met3 ( 1328020 193460 ) M3M4_PR_M ;
+ - la_data_in[16] ( PIN la_data_in[16] ) ( mem din0[16] ) + USE SIGNAL
+ + ROUTED met2 ( 912870 2380 0 ) ( * 16830 )
+ NEW met1 ( 912870 16830 ) ( 1338830 * )
+ NEW met3 ( 1338830 193460 ) ( 1340900 * )
+ NEW met4 ( 1340900 193460 ) ( * 198900 )
+ NEW met4 ( 1340870 198900 ) ( 1340900 * )
+ NEW met4 ( 1340870 198900 ) ( * 202300 0 )
+ NEW met2 ( 1338830 16830 ) ( * 193460 )
+ NEW met1 ( 1338830 16830 ) M1M2_PR
+ NEW met1 ( 912870 16830 ) M1M2_PR
+ NEW met2 ( 1338830 193460 ) M2M3_PR_M
+ NEW met3 ( 1340900 193460 ) M3M4_PR_M ;
+ - la_data_in[17] ( PIN la_data_in[17] ) ( mem din0[17] ) + USE SIGNAL
+ + ROUTED met2 ( 930810 2380 0 ) ( * 16490 )
+ NEW met1 ( 930810 16490 ) ( 1352630 * )
+ NEW met3 ( 1352630 198900 ) ( 1354700 * )
+ NEW met4 ( 1354470 198900 ) ( 1354700 * )
+ NEW met4 ( 1354470 198900 ) ( * 202300 0 )
+ NEW met2 ( 1352630 16490 ) ( * 198900 )
+ NEW met1 ( 1352630 16490 ) M1M2_PR
+ NEW met1 ( 930810 16490 ) M1M2_PR
+ NEW met2 ( 1352630 198900 ) M2M3_PR_M
+ NEW met3 ( 1354700 198900 ) M3M4_PR_M ;
+ - la_data_in[18] ( PIN la_data_in[18] ) ( mem din0[18] ) + USE SIGNAL
+ + ROUTED met2 ( 948750 2380 0 ) ( * 16150 )
+ NEW met1 ( 948750 16150 ) ( 1366430 * )
+ NEW met3 ( 1366430 198900 ) ( 1367580 * )
+ NEW met4 ( 1367390 198900 ) ( 1367580 * )
+ NEW met4 ( 1367390 198900 ) ( * 202300 0 )
+ NEW met2 ( 1366430 16150 ) ( * 198900 )
+ NEW met1 ( 1366430 16150 ) M1M2_PR
+ NEW met1 ( 948750 16150 ) M1M2_PR
+ NEW met2 ( 1366430 198900 ) M2M3_PR_M
+ NEW met3 ( 1367580 198900 ) M3M4_PR_M ;
+ - la_data_in[19] ( PIN la_data_in[19] ) ( mem din0[19] ) + USE SIGNAL
+ + ROUTED met2 ( 966230 2380 0 ) ( * 18530 )
+ NEW met1 ( 966230 18530 ) ( 972670 * )
+ NEW met2 ( 972670 18530 ) ( * 196010 )
+ NEW met2 ( 1380230 196010 ) ( * 196180 )
+ NEW met3 ( 1380230 196180 ) ( 1380460 * )
+ NEW met4 ( 1380460 196180 ) ( * 198900 )
+ NEW met4 ( 1380460 198900 ) ( 1380990 * )
+ NEW met4 ( 1380990 198900 ) ( * 202300 0 )
+ NEW met1 ( 972670 196010 ) ( 1380230 * )
+ NEW met1 ( 966230 18530 ) M1M2_PR
+ NEW met1 ( 972670 18530 ) M1M2_PR
+ NEW met1 ( 972670 196010 ) M1M2_PR
+ NEW met1 ( 1380230 196010 ) M1M2_PR
+ NEW met2 ( 1380230 196180 ) M2M3_PR_M
+ NEW met3 ( 1380460 196180 ) M3M4_PR_M
+ NEW met3 ( 1380230 196180 ) RECT ( -390 -150 0 150 ) ;
+ - la_data_in[1] ( PIN la_data_in[1] ) ( mem din0[1] ) + USE SIGNAL
+ + ROUTED met2 ( 1138730 193290 ) ( * 193460 )
+ NEW met3 ( 1138730 193460 ) ( 1143100 * )
+ NEW met4 ( 1143100 193460 ) ( * 198900 )
+ NEW met4 ( 1143100 198900 ) ( 1143670 * )
+ NEW met4 ( 1143670 198900 ) ( * 202300 0 )
+ NEW met1 ( 648370 193290 ) ( 1138730 * )
+ NEW met2 ( 646990 2380 0 ) ( * 34500 )
+ NEW met2 ( 646990 34500 ) ( 648370 * )
+ NEW met2 ( 648370 34500 ) ( * 193290 )
+ NEW met1 ( 648370 193290 ) M1M2_PR
+ NEW met1 ( 1138730 193290 ) M1M2_PR
+ NEW met2 ( 1138730 193460 ) M2M3_PR_M
+ NEW met3 ( 1143100 193460 ) M3M4_PR_M ;
+ - la_data_in[20] ( PIN la_data_in[20] ) ( mem din0[20] ) + USE SIGNAL
+ + ROUTED met2 ( 984170 2380 0 ) ( * 18530 )
+ NEW met1 ( 984170 18530 ) ( 986470 * )
+ NEW met2 ( 986470 18530 ) ( * 196350 )
+ NEW met2 ( 1392650 196350 ) ( * 198900 )
+ NEW met3 ( 1392650 198900 ) ( 1393340 * )
+ NEW met4 ( 1393230 198900 ) ( 1393340 * )
+ NEW met4 ( 1393230 198900 ) ( * 202300 0 )
+ NEW met1 ( 986470 196350 ) ( 1392650 * )
+ NEW met1 ( 984170 18530 ) M1M2_PR
+ NEW met1 ( 986470 18530 ) M1M2_PR
+ NEW met1 ( 986470 196350 ) M1M2_PR
+ NEW met1 ( 1392650 196350 ) M1M2_PR
+ NEW met2 ( 1392650 198900 ) M2M3_PR_M
+ NEW met3 ( 1393340 198900 ) M3M4_PR_M ;
+ - la_data_in[21] ( PIN la_data_in[21] ) ( mem din0[21] ) + USE SIGNAL
+ + ROUTED met2 ( 1001650 2380 0 ) ( * 18530 )
+ NEW met1 ( 1001650 18530 ) ( 1007170 * )
+ NEW met2 ( 1007170 18530 ) ( * 198050 )
+ NEW met2 ( 1404150 198050 ) ( * 198900 )
+ NEW met3 ( 1404150 198900 ) ( 1407140 * )
+ NEW met4 ( 1406830 198900 ) ( 1407140 * )
+ NEW met4 ( 1406830 198900 ) ( * 202300 0 )
+ NEW met1 ( 1007170 198050 ) ( 1404150 * )
+ NEW met1 ( 1001650 18530 ) M1M2_PR
+ NEW met1 ( 1007170 18530 ) M1M2_PR
+ NEW met1 ( 1007170 198050 ) M1M2_PR
+ NEW met1 ( 1404150 198050 ) M1M2_PR
+ NEW met2 ( 1404150 198900 ) M2M3_PR_M
+ NEW met3 ( 1407140 198900 ) M3M4_PR_M ;
+ - la_data_in[22] ( PIN la_data_in[22] ) ( mem din0[22] ) + USE SIGNAL
+ + ROUTED met2 ( 1414730 196690 ) ( * 196860 )
+ NEW met3 ( 1414730 196860 ) ( 1420020 * )
+ NEW met4 ( 1420020 196860 ) ( * 198900 )
+ NEW met4 ( 1420020 198900 ) ( 1420430 * )
+ NEW met4 ( 1420430 198900 ) ( * 202300 0 )
+ NEW met2 ( 1019590 2380 0 ) ( * 34500 )
+ NEW met2 ( 1019590 34500 ) ( 1020970 * )
+ NEW met2 ( 1020970 34500 ) ( * 196690 )
+ NEW met1 ( 1020970 196690 ) ( 1414730 * )
+ NEW met1 ( 1020970 196690 ) M1M2_PR
+ NEW met1 ( 1414730 196690 ) M1M2_PR
+ NEW met2 ( 1414730 196860 ) M2M3_PR_M
+ NEW met3 ( 1420020 196860 ) M3M4_PR_M ;
+ - la_data_in[23] ( PIN la_data_in[23] ) ( mem din0[23] ) + USE SIGNAL
+ + ROUTED met2 ( 1037070 2380 0 ) ( * 17170 )
+ NEW met1 ( 1037070 17170 ) ( 1041670 * )
+ NEW met2 ( 1428530 197030 ) ( * 197540 )
+ NEW met3 ( 1428530 197540 ) ( 1432900 * )
+ NEW met4 ( 1432900 197540 ) ( * 198900 )
+ NEW met4 ( 1432900 198900 ) ( 1433350 * )
+ NEW met4 ( 1433350 198900 ) ( * 202300 0 )
+ NEW met2 ( 1041670 17170 ) ( * 197030 )
+ NEW met1 ( 1041670 197030 ) ( 1428530 * )
+ NEW met1 ( 1037070 17170 ) M1M2_PR
+ NEW met1 ( 1041670 17170 ) M1M2_PR
+ NEW met1 ( 1041670 197030 ) M1M2_PR
+ NEW met1 ( 1428530 197030 ) M1M2_PR
+ NEW met2 ( 1428530 197540 ) M2M3_PR_M
+ NEW met3 ( 1432900 197540 ) M3M4_PR_M ;
+ - la_data_in[24] ( PIN la_data_in[24] ) ( mem din0[24] ) + USE SIGNAL
+ + ROUTED met2 ( 1442330 194310 ) ( * 196180 )
+ NEW met3 ( 1442330 196180 ) ( 1445780 * )
+ NEW met4 ( 1445780 196180 ) ( * 198900 )
+ NEW met4 ( 1445590 198900 ) ( 1445780 * )
+ NEW met4 ( 1445590 198900 ) ( * 202300 0 )
+ NEW met2 ( 1055010 2380 0 ) ( * 34500 )
+ NEW met2 ( 1055010 34500 ) ( 1055470 * )
+ NEW met2 ( 1055470 34500 ) ( * 194310 )
+ NEW met1 ( 1055470 194310 ) ( 1442330 * )
+ NEW met1 ( 1055470 194310 ) M1M2_PR
+ NEW met1 ( 1442330 194310 ) M1M2_PR
+ NEW met2 ( 1442330 196180 ) M2M3_PR_M
+ NEW met3 ( 1445780 196180 ) M3M4_PR_M ;
+ - la_data_in[25] ( PIN la_data_in[25] ) ( mem din0[25] ) + USE SIGNAL
+ + ROUTED met2 ( 1072490 2380 0 ) ( * 17170 )
+ NEW met1 ( 1072490 17170 ) ( 1076170 * )
+ NEW met2 ( 1456130 193970 ) ( * 194140 )
+ NEW met3 ( 1456130 194140 ) ( 1458660 * )
+ NEW met4 ( 1458660 194140 ) ( * 198900 )
+ NEW met4 ( 1458660 198900 ) ( 1459190 * )
+ NEW met4 ( 1459190 198900 ) ( * 202300 0 )
+ NEW met2 ( 1076170 17170 ) ( * 193970 )
+ NEW met1 ( 1076170 193970 ) ( 1456130 * )
+ NEW met1 ( 1072490 17170 ) M1M2_PR
+ NEW met1 ( 1076170 17170 ) M1M2_PR
+ NEW met1 ( 1076170 193970 ) M1M2_PR
+ NEW met1 ( 1456130 193970 ) M1M2_PR
+ NEW met2 ( 1456130 194140 ) M2M3_PR_M
+ NEW met3 ( 1458660 194140 ) M3M4_PR_M ;
+ - la_data_in[26] ( PIN la_data_in[26] ) ( mem din0[26] ) + USE SIGNAL
+ + ROUTED met2 ( 1090430 2380 0 ) ( * 17170 )
+ NEW met1 ( 1090430 17170 ) ( 1096870 * )
+ NEW met2 ( 1470390 198220 ) ( * 199070 )
+ NEW met3 ( 1470390 198220 ) ( 1471540 * )
+ NEW met4 ( 1471540 198220 ) ( * 198900 )
+ NEW met4 ( 1471540 198900 ) ( 1472110 * )
+ NEW met4 ( 1472110 198900 ) ( * 202300 0 )
+ NEW met2 ( 1096870 17170 ) ( * 199070 )
+ NEW met1 ( 1096870 199070 ) ( 1470390 * )
+ NEW met1 ( 1090430 17170 ) M1M2_PR
+ NEW met1 ( 1096870 17170 ) M1M2_PR
+ NEW met1 ( 1096870 199070 ) M1M2_PR
+ NEW met1 ( 1470390 199070 ) M1M2_PR
+ NEW met2 ( 1470390 198220 ) M2M3_PR_M
+ NEW met3 ( 1471540 198220 ) M3M4_PR_M ;
+ - la_data_in[27] ( PIN la_data_in[27] ) ( mem din0[27] ) + USE SIGNAL
+ + ROUTED met2 ( 1107910 2380 0 ) ( * 17510 )
+ NEW met1 ( 1107910 17510 ) ( 1110670 * )
+ NEW met2 ( 1484190 194990 ) ( * 197540 )
+ NEW met3 ( 1484190 197540 ) ( 1485340 * )
+ NEW met4 ( 1485340 197540 ) ( * 200260 )
+ NEW met4 ( 1485030 200260 ) ( 1485340 * )
+ NEW met4 ( 1485030 200260 ) ( * 202300 0 )
+ NEW met2 ( 1110670 17510 ) ( * 194990 )
+ NEW met1 ( 1110670 194990 ) ( 1484190 * )
+ NEW met1 ( 1107910 17510 ) M1M2_PR
+ NEW met1 ( 1110670 17510 ) M1M2_PR
+ NEW met1 ( 1110670 194990 ) M1M2_PR
+ NEW met1 ( 1484190 194990 ) M1M2_PR
+ NEW met2 ( 1484190 197540 ) M2M3_PR_M
+ NEW met3 ( 1485340 197540 ) M3M4_PR_M ;
+ - la_data_in[28] ( PIN la_data_in[28] ) ( mem din0[28] ) + USE SIGNAL
+ + ROUTED met2 ( 1125850 2380 0 ) ( * 17510 )
+ NEW met1 ( 1125850 17510 ) ( 1131370 * )
+ NEW met2 ( 1497530 197370 ) ( * 197540 )
+ NEW met3 ( 1497530 197540 ) ( 1499140 * )
+ NEW met4 ( 1499140 197540 ) ( * 200260 )
+ NEW met4 ( 1499140 200260 ) ( 1499310 * )
+ NEW met4 ( 1499310 200260 ) ( * 202300 0 )
+ NEW met2 ( 1131370 17510 ) ( * 197370 )
+ NEW met1 ( 1131370 197370 ) ( 1497530 * )
+ NEW met1 ( 1125850 17510 ) M1M2_PR
+ NEW met1 ( 1131370 17510 ) M1M2_PR
+ NEW met1 ( 1131370 197370 ) M1M2_PR
+ NEW met1 ( 1497530 197370 ) M1M2_PR
+ NEW met2 ( 1497530 197540 ) M2M3_PR_M
+ NEW met3 ( 1499140 197540 ) M3M4_PR_M ;
+ - la_data_in[29] ( PIN la_data_in[29] ) ( mem din0[29] ) + USE SIGNAL
+ + ROUTED met2 ( 1511330 195330 ) ( * 195500 )
+ NEW met3 ( 1511330 195500 ) ( 1512020 * )
+ NEW met4 ( 1512020 195500 ) ( * 200260 )
+ NEW met4 ( 1512020 200260 ) ( 1512230 * )
+ NEW met4 ( 1512230 200260 ) ( * 202300 0 )
+ NEW met2 ( 1143790 2380 0 ) ( * 34500 )
+ NEW met2 ( 1143790 34500 ) ( 1145170 * )
+ NEW met2 ( 1145170 34500 ) ( * 195330 )
+ NEW met1 ( 1145170 195330 ) ( 1511330 * )
+ NEW met1 ( 1145170 195330 ) M1M2_PR
+ NEW met1 ( 1511330 195330 ) M1M2_PR
+ NEW met2 ( 1511330 195500 ) M2M3_PR_M
+ NEW met3 ( 1512020 195500 ) M3M4_PR_M ;
+ - la_data_in[2] ( PIN la_data_in[2] ) ( mem din0[2] ) + USE SIGNAL
+ + ROUTED met2 ( 664930 2380 0 ) ( * 17850 )
+ NEW met1 ( 664930 17850 ) ( 669070 * )
+ NEW met2 ( 1152530 197710 ) ( * 198900 )
+ NEW met3 ( 1152530 198900 ) ( 1157820 * )
+ NEW met4 ( 1157820 198900 ) ( 1157950 * )
+ NEW met4 ( 1157950 198900 ) ( * 202300 0 )
+ NEW met2 ( 669070 17850 ) ( * 197710 )
+ NEW met1 ( 669070 197710 ) ( 1152530 * )
+ NEW met1 ( 664930 17850 ) M1M2_PR
+ NEW met1 ( 669070 17850 ) M1M2_PR
+ NEW met1 ( 669070 197710 ) M1M2_PR
+ NEW met1 ( 1152530 197710 ) M1M2_PR
+ NEW met2 ( 1152530 198900 ) M2M3_PR_M
+ NEW met3 ( 1157820 198900 ) M3M4_PR_M ;
+ - la_data_in[30] ( PIN la_data_in[30] ) ( mem din0[30] ) + USE SIGNAL
+ + ROUTED met2 ( 1161270 2380 0 ) ( * 17510 )
+ NEW met1 ( 1161270 17510 ) ( 1165870 * )
+ NEW met2 ( 1165870 17510 ) ( * 195670 )
+ NEW met2 ( 1518230 195670 ) ( * 196180 )
+ NEW met3 ( 1518230 196180 ) ( 1523980 * )
+ NEW met4 ( 1523980 196180 ) ( * 198900 )
+ NEW met4 ( 1523980 198900 ) ( 1524470 * )
+ NEW met4 ( 1524470 198900 ) ( * 202300 0 )
+ NEW met1 ( 1165870 195670 ) ( 1518230 * )
+ NEW met1 ( 1161270 17510 ) M1M2_PR
+ NEW met1 ( 1165870 17510 ) M1M2_PR
+ NEW met1 ( 1165870 195670 ) M1M2_PR
+ NEW met1 ( 1518230 195670 ) M1M2_PR
+ NEW met2 ( 1518230 196180 ) M2M3_PR_M
+ NEW met3 ( 1523980 196180 ) M3M4_PR_M ;
+ - la_data_in[31] ( PIN la_data_in[31] ) ( mem din0[31] ) + USE SIGNAL
+ + ROUTED met2 ( 1536170 197710 ) ( * 198900 )
+ NEW met3 ( 1536170 198900 ) ( 1537780 * )
+ NEW met4 ( 1537780 198900 ) ( 1538070 * )
+ NEW met4 ( 1538070 198900 ) ( * 202300 0 )
+ NEW met2 ( 1179210 2380 0 ) ( * 34500 )
+ NEW met2 ( 1179210 34500 ) ( 1179670 * )
+ NEW met2 ( 1179670 34500 ) ( * 197710 )
+ NEW met1 ( 1179670 197710 ) ( 1536170 * )
+ NEW met1 ( 1179670 197710 ) M1M2_PR
+ NEW met1 ( 1536170 197710 ) M1M2_PR
+ NEW met2 ( 1536170 198900 ) M2M3_PR_M
+ NEW met3 ( 1537780 198900 ) M3M4_PR_M ;
+ - la_data_in[32] ( PIN la_data_in[32] ) ( mprj reset ) + USE SIGNAL
+ + ROUTED met3 ( 2499180 2040340 0 ) ( 2513670 * )
+ NEW met2 ( 2513670 17170 ) ( * 2040340 )
+ NEW met2 ( 1196690 2380 0 ) ( * 17170 )
+ NEW met1 ( 1196690 17170 ) ( 2513670 * )
+ NEW met1 ( 2513670 17170 ) M1M2_PR
+ NEW met2 ( 2513670 2040340 ) M2M3_PR_M
+ NEW met1 ( 1196690 17170 ) M1M2_PR ;
- la_data_in[33] ( PIN la_data_in[33] ) + USE SIGNAL ;
- la_data_in[34] ( PIN la_data_in[34] ) + USE SIGNAL ;
- la_data_in[35] ( PIN la_data_in[35] ) + USE SIGNAL ;
- - la_data_in[36] ( PIN la_data_in[36] ) + USE SIGNAL ;
+ - la_data_in[36] ( PIN la_data_in[36] ) ( mprj init_en ) + USE SIGNAL
+ + ROUTED met2 ( 1267530 2380 0 ) ( * 14790 )
+ NEW met2 ( 996590 14790 ) ( * 2578900 )
+ NEW met1 ( 996590 14790 ) ( 1267530 * )
+ NEW met3 ( 996590 2578900 ) ( 1000500 * 0 )
+ NEW met1 ( 996590 14790 ) M1M2_PR
+ NEW met1 ( 1267530 14790 ) M1M2_PR
+ NEW met2 ( 996590 2578900 ) M2M3_PR_M ;
- la_data_in[37] ( PIN la_data_in[37] ) + USE SIGNAL ;
- la_data_in[38] ( PIN la_data_in[38] ) + USE SIGNAL ;
- la_data_in[39] ( PIN la_data_in[39] ) + USE SIGNAL ;
- - la_data_in[3] ( PIN la_data_in[3] ) + USE SIGNAL ;
- - la_data_in[40] ( PIN la_data_in[40] ) + USE SIGNAL ;
+ - la_data_in[3] ( PIN la_data_in[3] ) ( mem din0[3] ) + USE SIGNAL
+ + ROUTED met2 ( 1166330 198220 ) ( * 198390 )
+ NEW met3 ( 1166330 198220 ) ( 1169780 * )
+ NEW met4 ( 1169780 198220 ) ( * 198900 )
+ NEW met4 ( 1169780 198900 ) ( 1170190 * )
+ NEW met4 ( 1170190 198900 ) ( * 202300 0 )
+ NEW met2 ( 682410 2380 0 ) ( * 34500 )
+ NEW met2 ( 682410 34500 ) ( 682870 * )
+ NEW met2 ( 682870 34500 ) ( * 198390 )
+ NEW met1 ( 682870 198390 ) ( 1166330 * )
+ NEW met1 ( 682870 198390 ) M1M2_PR
+ NEW met1 ( 1166330 198390 ) M1M2_PR
+ NEW met2 ( 1166330 198220 ) M2M3_PR_M
+ NEW met3 ( 1169780 198220 ) M3M4_PR_M ;
+ - la_data_in[40] ( PIN la_data_in[40] ) ( mem csb0 ) + USE SIGNAL
+ + ROUTED met2 ( 1338830 2380 0 ) ( * 15130 )
+ NEW met2 ( 993830 14450 ) ( * 217940 )
+ NEW li1 ( 1024650 14450 ) ( * 15130 )
+ NEW met1 ( 993830 14450 ) ( 1024650 * )
+ NEW met3 ( 993830 217940 ) ( 1000500 * )
+ NEW met3 ( 1000500 217940 ) ( * 220590 0 )
+ NEW met1 ( 1024650 15130 ) ( 1338830 * )
+ NEW met1 ( 993830 14450 ) M1M2_PR
+ NEW met2 ( 993830 217940 ) M2M3_PR_M
+ NEW met1 ( 1338830 15130 ) M1M2_PR
+ NEW li1 ( 1024650 14450 ) L1M1_PR_MR
+ NEW li1 ( 1024650 15130 ) L1M1_PR_MR ;
- la_data_in[41] ( PIN la_data_in[41] ) + USE SIGNAL ;
- la_data_in[42] ( PIN la_data_in[42] ) + USE SIGNAL ;
- la_data_in[43] ( PIN la_data_in[43] ) + USE SIGNAL ;
- - la_data_in[44] ( PIN la_data_in[44] ) + USE SIGNAL ;
- - la_data_in[45] ( PIN la_data_in[45] ) + USE SIGNAL ;
- - la_data_in[46] ( PIN la_data_in[46] ) + USE SIGNAL ;
- - la_data_in[47] ( PIN la_data_in[47] ) + USE SIGNAL ;
- - la_data_in[48] ( PIN la_data_in[48] ) + USE SIGNAL ;
- - la_data_in[49] ( PIN la_data_in[49] ) + USE SIGNAL ;
- - la_data_in[4] ( PIN la_data_in[4] ) + USE SIGNAL ;
- - la_data_in[50] ( PIN la_data_in[50] ) + USE SIGNAL ;
- - la_data_in[51] ( PIN la_data_in[51] ) + USE SIGNAL ;
+ - la_data_in[44] ( PIN la_data_in[44] ) ( mprj init_addr[0] ) + USE SIGNAL
+ + ROUTED met2 ( 2499870 2996420 0 ) ( 2500330 * )
+ NEW met2 ( 2500330 17510 ) ( * 2996420 )
+ NEW met2 ( 1409670 2380 0 ) ( * 17510 )
+ NEW met1 ( 1409670 17510 ) ( 2500330 * )
+ NEW met1 ( 2500330 17510 ) M1M2_PR
+ NEW met1 ( 1409670 17510 ) M1M2_PR ;
+ - la_data_in[45] ( PIN la_data_in[45] ) ( mprj init_addr[1] ) + USE SIGNAL
+ + ROUTED met2 ( 1573890 19890 ) ( * 1488350 )
+ NEW met2 ( 1427150 2380 0 ) ( * 19890 )
+ NEW met1 ( 1427150 19890 ) ( 1573890 * )
+ NEW met2 ( 1486950 1488350 ) ( * 1500420 0 )
+ NEW met1 ( 1486950 1488350 ) ( 1573890 * )
+ NEW met1 ( 1573890 19890 ) M1M2_PR
+ NEW met1 ( 1573890 1488350 ) M1M2_PR
+ NEW met1 ( 1427150 19890 ) M1M2_PR
+ NEW met1 ( 1486950 1488350 ) M1M2_PR ;
+ - la_data_in[46] ( PIN la_data_in[46] ) ( mprj init_addr[2] ) + USE SIGNAL
+ + ROUTED met2 ( 1445090 2380 0 ) ( * 17850 )
+ NEW met3 ( 2499180 2520420 0 ) ( 2511830 * )
+ NEW met2 ( 2511830 17850 ) ( * 2520420 )
+ NEW met1 ( 1445090 17850 ) ( 2511830 * )
+ NEW met1 ( 1445090 17850 ) M1M2_PR
+ NEW met1 ( 2511830 17850 ) M1M2_PR
+ NEW met2 ( 2511830 2520420 ) M2M3_PR_M ;
+ - la_data_in[47] ( PIN la_data_in[47] ) ( mprj init_addr[3] ) + USE SIGNAL
+ + ROUTED met2 ( 1463030 2380 0 ) ( * 19550 )
+ NEW met2 ( 1749150 19550 ) ( * 1488010 )
+ NEW met2 ( 2216510 1488010 ) ( * 1500420 0 )
+ NEW met1 ( 1463030 19550 ) ( 1749150 * )
+ NEW met1 ( 1749150 1488010 ) ( 2216510 * )
+ NEW met1 ( 1463030 19550 ) M1M2_PR
+ NEW met1 ( 1749150 19550 ) M1M2_PR
+ NEW met1 ( 1749150 1488010 ) M1M2_PR
+ NEW met1 ( 2216510 1488010 ) M1M2_PR ;
+ - la_data_in[48] ( PIN la_data_in[48] ) ( mprj init_addr[4] ) + USE SIGNAL
+ + ROUTED met2 ( 1480510 2380 0 ) ( * 16660 )
+ NEW met3 ( 1480510 16660 ) ( 1582860 * )
+ NEW met2 ( 1689350 2999820 0 ) ( * 3008660 )
+ NEW met3 ( 1582860 3008660 ) ( 1689350 * )
+ NEW met4 ( 1582860 16660 ) ( * 3008660 )
+ NEW met2 ( 1480510 16660 ) M2M3_PR_M
+ NEW met3 ( 1582860 16660 ) M3M4_PR_M
+ NEW met3 ( 1582860 3008660 ) M3M4_PR_M
+ NEW met2 ( 1689350 3008660 ) M2M3_PR_M ;
+ - la_data_in[49] ( PIN la_data_in[49] ) ( mprj init_addr[5] ) + USE SIGNAL
+ + ROUTED met3 ( 2499180 1920660 0 ) ( 2514590 * )
+ NEW met2 ( 2514590 18190 ) ( * 1920660 )
+ NEW met2 ( 1498450 2380 0 ) ( * 18190 )
+ NEW met1 ( 1498450 18190 ) ( 2514590 * )
+ NEW met1 ( 2514590 18190 ) M1M2_PR
+ NEW met2 ( 2514590 1920660 ) M2M3_PR_M
+ NEW met1 ( 1498450 18190 ) M1M2_PR ;
+ - la_data_in[4] ( PIN la_data_in[4] ) ( mem din0[4] ) + USE SIGNAL
+ + ROUTED met2 ( 700350 2380 0 ) ( * 17850 )
+ NEW met1 ( 700350 17850 ) ( 703570 * )
+ NEW met2 ( 1180130 194650 ) ( * 194820 )
+ NEW met3 ( 1180130 194820 ) ( 1182660 * )
+ NEW met4 ( 1182660 194820 ) ( * 198900 )
+ NEW met4 ( 1182660 198900 ) ( 1183110 * )
+ NEW met4 ( 1183110 198900 ) ( * 202300 0 )
+ NEW met2 ( 703570 17850 ) ( * 194650 )
+ NEW met1 ( 703570 194650 ) ( 1180130 * )
+ NEW met1 ( 700350 17850 ) M1M2_PR
+ NEW met1 ( 703570 17850 ) M1M2_PR
+ NEW met1 ( 703570 194650 ) M1M2_PR
+ NEW met1 ( 1180130 194650 ) M1M2_PR
+ NEW met2 ( 1180130 194820 ) M2M3_PR_M
+ NEW met3 ( 1182660 194820 ) M3M4_PR_M ;
+ - la_data_in[50] ( PIN la_data_in[50] ) ( mprj init_addr[6] ) + USE SIGNAL
+ + ROUTED met2 ( 1162190 1487330 ) ( * 1500420 0 )
+ NEW met2 ( 1574350 20230 ) ( * 1487330 )
+ NEW met2 ( 1515930 2380 0 ) ( * 20230 )
+ NEW met1 ( 1515930 20230 ) ( 1574350 * )
+ NEW met1 ( 1162190 1487330 ) ( 1574350 * )
+ NEW met1 ( 1574350 20230 ) M1M2_PR
+ NEW met1 ( 1162190 1487330 ) M1M2_PR
+ NEW met1 ( 1574350 1487330 ) M1M2_PR
+ NEW met1 ( 1515930 20230 ) M1M2_PR ;
+ - la_data_in[51] ( PIN la_data_in[51] ) ( mprj init_addr[7] ) + USE SIGNAL
+ + ROUTED met2 ( 1533870 2380 0 ) ( * 16490 )
+ NEW met1 ( 1533870 16490 ) ( 1573430 * )
+ NEW met2 ( 1573430 16490 ) ( * 1488010 )
+ NEW met2 ( 1405070 1488010 ) ( * 1500420 0 )
+ NEW met1 ( 1405070 1488010 ) ( 1573430 * )
+ NEW met1 ( 1533870 16490 ) M1M2_PR
+ NEW met1 ( 1573430 16490 ) M1M2_PR
+ NEW met1 ( 1573430 1488010 ) M1M2_PR
+ NEW met1 ( 1405070 1488010 ) M1M2_PR ;
- la_data_in[52] ( PIN la_data_in[52] ) + USE SIGNAL ;
- la_data_in[53] ( PIN la_data_in[53] ) + USE SIGNAL ;
- la_data_in[54] ( PIN la_data_in[54] ) + USE SIGNAL ;
@@ -8300,7 +8723,22 @@
- la_data_in[57] ( PIN la_data_in[57] ) + USE SIGNAL ;
- la_data_in[58] ( PIN la_data_in[58] ) + USE SIGNAL ;
- la_data_in[59] ( PIN la_data_in[59] ) + USE SIGNAL ;
- - la_data_in[5] ( PIN la_data_in[5] ) + USE SIGNAL ;
+ - la_data_in[5] ( PIN la_data_in[5] ) ( mem din0[5] ) + USE SIGNAL
+ + ROUTED met2 ( 717830 2380 0 ) ( * 17850 )
+ NEW met1 ( 717830 17850 ) ( 724270 * )
+ NEW met2 ( 1195310 198730 ) ( * 198900 )
+ NEW met3 ( 1195310 198900 ) ( 1196460 * )
+ NEW met4 ( 1196460 198900 ) ( * 200260 )
+ NEW met4 ( 1196460 200260 ) ( 1196710 * )
+ NEW met4 ( 1196710 200260 ) ( * 202300 0 )
+ NEW met1 ( 724270 198730 ) ( 1195310 * )
+ NEW met2 ( 724270 17850 ) ( * 198730 )
+ NEW met1 ( 717830 17850 ) M1M2_PR
+ NEW met1 ( 724270 17850 ) M1M2_PR
+ NEW met1 ( 724270 198730 ) M1M2_PR
+ NEW met1 ( 1195310 198730 ) M1M2_PR
+ NEW met2 ( 1195310 198900 ) M2M3_PR_M
+ NEW met3 ( 1196460 198900 ) M3M4_PR_M ;
- la_data_in[60] ( PIN la_data_in[60] ) + USE SIGNAL ;
- la_data_in[61] ( PIN la_data_in[61] ) + USE SIGNAL ;
- la_data_in[62] ( PIN la_data_in[62] ) + USE SIGNAL ;
@@ -8311,7 +8749,22 @@
- la_data_in[67] ( PIN la_data_in[67] ) + USE SIGNAL ;
- la_data_in[68] ( PIN la_data_in[68] ) + USE SIGNAL ;
- la_data_in[69] ( PIN la_data_in[69] ) + USE SIGNAL ;
- - la_data_in[6] ( PIN la_data_in[6] ) + USE SIGNAL ;
+ - la_data_in[6] ( PIN la_data_in[6] ) ( mem din0[6] ) + USE SIGNAL
+ + ROUTED met2 ( 735770 2380 0 ) ( * 17850 )
+ NEW met1 ( 735770 17850 ) ( 738070 * )
+ NEW met2 ( 1207730 198900 ) ( * 200090 )
+ NEW met3 ( 1207730 198900 ) ( 1209340 * )
+ NEW met4 ( 1209340 198900 ) ( * 200260 )
+ NEW met4 ( 1209340 200260 ) ( 1209630 * )
+ NEW met4 ( 1209630 200260 ) ( * 202300 0 )
+ NEW met1 ( 738070 200090 ) ( 1207730 * )
+ NEW met2 ( 738070 17850 ) ( * 200090 )
+ NEW met1 ( 735770 17850 ) M1M2_PR
+ NEW met1 ( 738070 17850 ) M1M2_PR
+ NEW met1 ( 738070 200090 ) M1M2_PR
+ NEW met1 ( 1207730 200090 ) M1M2_PR
+ NEW met2 ( 1207730 198900 ) M2M3_PR_M
+ NEW met3 ( 1209340 198900 ) M3M4_PR_M ;
- la_data_in[70] ( PIN la_data_in[70] ) + USE SIGNAL ;
- la_data_in[71] ( PIN la_data_in[71] ) + USE SIGNAL ;
- la_data_in[72] ( PIN la_data_in[72] ) + USE SIGNAL ;
@@ -8322,7 +8775,22 @@
- la_data_in[77] ( PIN la_data_in[77] ) + USE SIGNAL ;
- la_data_in[78] ( PIN la_data_in[78] ) + USE SIGNAL ;
- la_data_in[79] ( PIN la_data_in[79] ) + USE SIGNAL ;
- - la_data_in[7] ( PIN la_data_in[7] ) + USE SIGNAL ;
+ - la_data_in[7] ( PIN la_data_in[7] ) ( mem din0[7] ) + USE SIGNAL
+ + ROUTED met2 ( 753250 2380 0 ) ( * 15470 )
+ NEW met1 ( 753250 15470 ) ( 1141950 * )
+ NEW met2 ( 1221530 193290 ) ( * 193460 )
+ NEW met3 ( 1221530 193460 ) ( 1222220 * )
+ NEW met4 ( 1222220 193460 ) ( * 200260 )
+ NEW met4 ( 1222220 200260 ) ( 1222550 * )
+ NEW met4 ( 1222550 200260 ) ( * 202300 0 )
+ NEW met1 ( 1141950 193290 ) ( 1221530 * )
+ NEW met2 ( 1141950 15470 ) ( * 193290 )
+ NEW met1 ( 753250 15470 ) M1M2_PR
+ NEW met1 ( 1141950 15470 ) M1M2_PR
+ NEW met1 ( 1141950 193290 ) M1M2_PR
+ NEW met1 ( 1221530 193290 ) M1M2_PR
+ NEW met2 ( 1221530 193460 ) M2M3_PR_M
+ NEW met3 ( 1222220 193460 ) M3M4_PR_M ;
- la_data_in[80] ( PIN la_data_in[80] ) + USE SIGNAL ;
- la_data_in[81] ( PIN la_data_in[81] ) + USE SIGNAL ;
- la_data_in[82] ( PIN la_data_in[82] ) + USE SIGNAL ;
@@ -8333,7 +8801,20 @@
- la_data_in[87] ( PIN la_data_in[87] ) + USE SIGNAL ;
- la_data_in[88] ( PIN la_data_in[88] ) + USE SIGNAL ;
- la_data_in[89] ( PIN la_data_in[89] ) + USE SIGNAL ;
- - la_data_in[8] ( PIN la_data_in[8] ) + USE SIGNAL ;
+ - la_data_in[8] ( PIN la_data_in[8] ) ( mem din0[8] ) + USE SIGNAL
+ + ROUTED met2 ( 771190 2380 0 ) ( * 34500 )
+ NEW met2 ( 771190 34500 ) ( 772570 * )
+ NEW met2 ( 772570 34500 ) ( * 199410 )
+ NEW met2 ( 1235330 198900 ) ( * 199410 )
+ NEW met3 ( 1235330 198900 ) ( 1236020 * )
+ NEW met4 ( 1236020 198900 ) ( * 200260 )
+ NEW met4 ( 1236020 200260 ) ( 1236150 * )
+ NEW met4 ( 1236150 200260 ) ( * 202300 0 )
+ NEW met1 ( 772570 199410 ) ( 1235330 * )
+ NEW met1 ( 772570 199410 ) M1M2_PR
+ NEW met1 ( 1235330 199410 ) M1M2_PR
+ NEW met2 ( 1235330 198900 ) M2M3_PR_M
+ NEW met3 ( 1236020 198900 ) M3M4_PR_M ;
- la_data_in[90] ( PIN la_data_in[90] ) + USE SIGNAL ;
- la_data_in[91] ( PIN la_data_in[91] ) + USE SIGNAL ;
- la_data_in[92] ( PIN la_data_in[92] ) + USE SIGNAL ;
@@ -8344,7 +8825,21 @@
- la_data_in[97] ( PIN la_data_in[97] ) + USE SIGNAL ;
- la_data_in[98] ( PIN la_data_in[98] ) + USE SIGNAL ;
- la_data_in[99] ( PIN la_data_in[99] ) + USE SIGNAL ;
- - la_data_in[9] ( PIN la_data_in[9] ) + USE SIGNAL ;
+ - la_data_in[9] ( PIN la_data_in[9] ) ( mem din0[9] ) + USE SIGNAL
+ + ROUTED met2 ( 789130 2380 0 ) ( * 15810 )
+ NEW met2 ( 1249130 193630 ) ( * 198900 )
+ NEW met3 ( 1249130 198900 ) ( 1249820 * )
+ NEW met4 ( 1249750 198900 ) ( 1249820 * )
+ NEW met4 ( 1249750 198900 ) ( * 202300 0 )
+ NEW met2 ( 1183350 15810 ) ( * 193630 )
+ NEW met1 ( 789130 15810 ) ( 1183350 * )
+ NEW met1 ( 1183350 193630 ) ( 1249130 * )
+ NEW met1 ( 789130 15810 ) M1M2_PR
+ NEW met1 ( 1183350 15810 ) M1M2_PR
+ NEW met1 ( 1183350 193630 ) M1M2_PR
+ NEW met1 ( 1249130 193630 ) M1M2_PR
+ NEW met2 ( 1249130 198900 ) M2M3_PR_M
+ NEW met3 ( 1249820 198900 ) M3M4_PR_M ;
- la_data_out[0] ( PIN la_data_out[0] ) + USE SIGNAL ;
- la_data_out[100] ( PIN la_data_out[100] ) + USE SIGNAL ;
- la_data_out[101] ( PIN la_data_out[101] ) + USE SIGNAL ;
@@ -8433,17 +8928,101 @@
- la_data_out[61] ( PIN la_data_out[61] ) + USE SIGNAL ;
- la_data_out[62] ( PIN la_data_out[62] ) + USE SIGNAL ;
- la_data_out[63] ( PIN la_data_out[63] ) + USE SIGNAL ;
- - la_data_out[64] ( PIN la_data_out[64] ) + USE SIGNAL ;
- - la_data_out[65] ( PIN la_data_out[65] ) + USE SIGNAL ;
- - la_data_out[66] ( PIN la_data_out[66] ) + USE SIGNAL ;
- - la_data_out[67] ( PIN la_data_out[67] ) + USE SIGNAL ;
- - la_data_out[68] ( PIN la_data_out[68] ) + USE SIGNAL ;
- - la_data_out[69] ( PIN la_data_out[69] ) + USE SIGNAL ;
+ - la_data_out[64] ( PIN la_data_out[64] ) ( mprj OUT[0] ) + USE SIGNAL
+ + ROUTED met2 ( 1770310 2380 0 ) ( * 19550 )
+ NEW met3 ( 2499180 2279700 0 ) ( 2512750 * )
+ NEW met2 ( 2512750 19550 ) ( * 2279700 )
+ NEW met1 ( 1770310 19550 ) ( 2512750 * )
+ NEW met1 ( 1770310 19550 ) M1M2_PR
+ NEW met1 ( 2512750 19550 ) M1M2_PR
+ NEW met2 ( 2512750 2279700 ) M2M3_PR_M ;
+ - la_data_out[65] ( PIN la_data_out[65] ) ( mprj OUT[1] ) + USE SIGNAL
+ + ROUTED met4 ( 2114620 16660 ) ( * 3009340 )
+ NEW met2 ( 1787790 2380 0 ) ( * 16660 )
+ NEW met3 ( 1787790 16660 ) ( 2114620 * )
+ NEW met2 ( 2176030 2999820 0 ) ( * 3009340 )
+ NEW met3 ( 2114620 3009340 ) ( 2176030 * )
+ NEW met3 ( 2114620 16660 ) M3M4_PR_M
+ NEW met3 ( 2114620 3009340 ) M3M4_PR_M
+ NEW met2 ( 1787790 16660 ) M2M3_PR_M
+ NEW met2 ( 2176030 3009340 ) M2M3_PR_M ;
+ - la_data_out[66] ( PIN la_data_out[66] ) ( mprj OUT[2] ) + USE SIGNAL
+ + ROUTED met2 ( 1805730 2380 0 ) ( * 3060 )
+ NEW met2 ( 1805730 3060 ) ( 1806650 * )
+ NEW met2 ( 1806650 2380 ) ( * 3060 )
+ NEW met2 ( 1806650 2380 ) ( 1807570 * )
+ NEW met2 ( 1807570 2380 ) ( * 1487330 )
+ NEW met2 ( 2460310 1487330 ) ( * 1500420 0 )
+ NEW met1 ( 1807570 1487330 ) ( 2460310 * )
+ NEW met1 ( 1807570 1487330 ) M1M2_PR
+ NEW met1 ( 2460310 1487330 ) M1M2_PR ;
+ - la_data_out[67] ( PIN la_data_out[67] ) ( mprj OUT[3] ) + USE SIGNAL
+ + ROUTED met2 ( 1823210 2380 0 ) ( * 19890 )
+ NEW met3 ( 2499180 2879460 0 ) ( 2504930 * )
+ NEW met2 ( 2504930 19890 ) ( * 2879460 )
+ NEW met1 ( 1823210 19890 ) ( 2504930 * )
+ NEW met1 ( 1823210 19890 ) M1M2_PR
+ NEW met1 ( 2504930 19890 ) M1M2_PR
+ NEW met2 ( 2504930 2879460 ) M2M3_PR_M ;
+ - la_data_out[68] ( PIN la_data_out[68] ) ( mprj OUT[4] ) + USE SIGNAL
+ + ROUTED met2 ( 1841150 2380 0 ) ( * 20230 )
+ NEW met3 ( 2499180 1679940 0 ) ( 2505850 * )
+ NEW met2 ( 2505850 20230 ) ( * 1679940 )
+ NEW met1 ( 1841150 20230 ) ( 2505850 * )
+ NEW met1 ( 1841150 20230 ) M1M2_PR
+ NEW met1 ( 2505850 20230 ) M1M2_PR
+ NEW met2 ( 2505850 1679940 ) M2M3_PR_M ;
+ - la_data_out[69] ( PIN la_data_out[69] ) ( mprj OUT[5] ) + USE SIGNAL
+ + ROUTED met2 ( 1858630 2380 0 ) ( * 19210 )
+ NEW met2 ( 991990 18870 ) ( * 1979140 )
+ NEW met1 ( 991990 18870 ) ( 1000500 * )
+ NEW met1 ( 1000500 18870 ) ( * 19210 )
+ NEW met1 ( 1000500 19210 ) ( 1858630 * )
+ NEW met3 ( 991990 1979140 ) ( 1000500 * 0 )
+ NEW met1 ( 991990 18870 ) M1M2_PR
+ NEW met1 ( 1858630 19210 ) M1M2_PR
+ NEW met2 ( 991990 1979140 ) M2M3_PR_M ;
- la_data_out[6] ( PIN la_data_out[6] ) + USE SIGNAL ;
- - la_data_out[70] ( PIN la_data_out[70] ) + USE SIGNAL ;
- - la_data_out[71] ( PIN la_data_out[71] ) + USE SIGNAL ;
- - la_data_out[72] ( PIN la_data_out[72] ) + USE SIGNAL ;
- - la_data_out[73] ( PIN la_data_out[73] ) + USE SIGNAL ;
+ - la_data_out[70] ( PIN la_data_out[70] ) ( mprj OUT[6] ) + USE SIGNAL
+ + ROUTED met2 ( 1859550 16830 ) ( * 1487670 )
+ NEW met2 ( 1876570 2380 0 ) ( * 16830 )
+ NEW met1 ( 1859550 16830 ) ( 1876570 * )
+ NEW met2 ( 1324110 1487670 ) ( * 1500420 0 )
+ NEW met1 ( 1324110 1487670 ) ( 1859550 * )
+ NEW met1 ( 1859550 16830 ) M1M2_PR
+ NEW met1 ( 1859550 1487670 ) M1M2_PR
+ NEW met1 ( 1876570 16830 ) M1M2_PR
+ NEW met1 ( 1324110 1487670 ) M1M2_PR ;
+ - la_data_out[71] ( PIN la_data_out[71] ) ( mprj OUT[7] ) + USE SIGNAL
+ + ROUTED met2 ( 991530 18530 ) ( * 1859460 )
+ NEW met1 ( 1001190 18530 ) ( * 18870 )
+ NEW met1 ( 991530 18530 ) ( 1001190 * )
+ NEW met3 ( 991530 1859460 ) ( 1000500 * 0 )
+ NEW met2 ( 1894510 2380 0 ) ( * 18870 )
+ NEW met1 ( 1001190 18870 ) ( 1894510 * )
+ NEW met1 ( 991530 18530 ) M1M2_PR
+ NEW met2 ( 991530 1859460 ) M2M3_PR_M
+ NEW met1 ( 1894510 18870 ) M1M2_PR ;
+ - la_data_out[72] ( PIN la_data_out[72] ) ( mprj OUT[8] ) + USE SIGNAL
+ + ROUTED met2 ( 990610 15130 ) ( * 1739780 )
+ NEW li1 ( 1024190 15130 ) ( * 18530 )
+ NEW met1 ( 990610 15130 ) ( 1024190 * )
+ NEW met3 ( 990610 1739780 ) ( 1000500 * 0 )
+ NEW met2 ( 1911990 2380 0 ) ( * 18530 )
+ NEW met1 ( 1024190 18530 ) ( 1911990 * )
+ NEW met1 ( 990610 15130 ) M1M2_PR
+ NEW met2 ( 990610 1739780 ) M2M3_PR_M
+ NEW li1 ( 1024190 15130 ) L1M1_PR_MR
+ NEW li1 ( 1024190 18530 ) L1M1_PR_MR
+ NEW met1 ( 1911990 18530 ) M1M2_PR ;
+ - la_data_out[73] ( PIN la_data_out[73] ) ( mprj OUT[9] ) + USE SIGNAL
+ + ROUTED met2 ( 1929930 2380 0 ) ( * 18530 )
+ NEW met3 ( 2499180 1800980 0 ) ( 2515050 * )
+ NEW met2 ( 2515050 18530 ) ( * 1800980 )
+ NEW met1 ( 1929930 18530 ) ( 2515050 * )
+ NEW met1 ( 1929930 18530 ) M1M2_PR
+ NEW met1 ( 2515050 18530 ) M1M2_PR
+ NEW met2 ( 2515050 1800980 ) M2M3_PR_M ;
- la_data_out[74] ( PIN la_data_out[74] ) + USE SIGNAL ;
- la_data_out[75] ( PIN la_data_out[75] ) + USE SIGNAL ;
- la_data_out[76] ( PIN la_data_out[76] ) + USE SIGNAL ;
@@ -8602,97 +9181,97 @@
- la_oenb[99] ( PIN la_oenb[99] ) + USE SIGNAL ;
- la_oenb[9] ( PIN la_oenb[9] ) + USE SIGNAL ;
- mem_addr\[0\] ( mprj mem_addr[0] ) ( mem addr0[0] ) + USE SIGNAL
- + ROUTED met2 ( 991070 199070 ) ( * 1620100 )
- NEW met2 ( 1104230 198220 ) ( * 199070 )
- NEW met3 ( 1104230 198220 ) ( 1104460 * )
- NEW met4 ( 1104460 198220 ) ( * 198900 )
+ + ROUTED met2 ( 990150 193630 ) ( * 1620100 )
+ NEW met2 ( 1104230 193630 ) ( * 194140 )
+ NEW met3 ( 1104230 194140 ) ( 1104460 * )
+ NEW met4 ( 1104460 194140 ) ( * 198900 )
NEW met4 ( 1104460 198900 ) ( 1104910 * )
NEW met4 ( 1104910 198900 ) ( * 202300 0 )
- NEW met1 ( 991070 199070 ) ( 1104230 * )
- NEW met3 ( 991070 1620100 ) ( 1000500 * 0 )
- NEW met1 ( 991070 199070 ) M1M2_PR
- NEW met2 ( 991070 1620100 ) M2M3_PR_M
- NEW met1 ( 1104230 199070 ) M1M2_PR
- NEW met2 ( 1104230 198220 ) M2M3_PR_M
- NEW met3 ( 1104460 198220 ) M3M4_PR_M
- NEW met3 ( 1104230 198220 ) RECT ( -390 -150 0 150 ) ;
+ NEW met1 ( 990150 193630 ) ( 1104230 * )
+ NEW met3 ( 990150 1620100 ) ( 1000500 * 0 )
+ NEW met1 ( 990150 193630 ) M1M2_PR
+ NEW met2 ( 990150 1620100 ) M2M3_PR_M
+ NEW met1 ( 1104230 193630 ) M1M2_PR
+ NEW met2 ( 1104230 194140 ) M2M3_PR_M
+ NEW met3 ( 1104460 194140 ) M3M4_PR_M
+ NEW met3 ( 1104230 194140 ) RECT ( -390 -150 0 150 ) ;
- mem_addr\[1\] ( mprj mem_addr[1] ) ( mem addr0[1] ) + USE SIGNAL
- + ROUTED met2 ( 1648870 1487670 ) ( * 1500420 0 )
- NEW met2 ( 1124470 198220 ) ( * 199070 )
+ + ROUTED met2 ( 1648870 1487330 ) ( * 1500420 0 )
+ NEW met2 ( 1124470 198220 ) ( * 199750 )
NEW met3 ( 1118260 198220 ) ( 1124470 * )
NEW met4 ( 1118260 198220 ) ( * 198900 )
NEW met4 ( 1117830 198900 ) ( 1118260 * )
NEW met4 ( 1117830 198900 ) ( * 202300 0 )
- NEW met2 ( 1604250 199070 ) ( * 1487670 )
- NEW met1 ( 1604250 1487670 ) ( 1648870 * )
- NEW met1 ( 1124470 199070 ) ( 1604250 * )
- NEW met1 ( 1648870 1487670 ) M1M2_PR
- NEW met1 ( 1124470 199070 ) M1M2_PR
+ NEW met2 ( 1604250 199750 ) ( * 1487330 )
+ NEW met1 ( 1604250 1487330 ) ( 1648870 * )
+ NEW met1 ( 1124470 199750 ) ( 1604250 * )
+ NEW met1 ( 1648870 1487330 ) M1M2_PR
+ NEW met1 ( 1124470 199750 ) M1M2_PR
NEW met2 ( 1124470 198220 ) M2M3_PR_M
NEW met3 ( 1118260 198220 ) M3M4_PR_M
- NEW met1 ( 1604250 199070 ) M1M2_PR
- NEW met1 ( 1604250 1487670 ) M1M2_PR ;
+ NEW met1 ( 1604250 199750 ) M1M2_PR
+ NEW met1 ( 1604250 1487330 ) M1M2_PR ;
- mem_addr\[2\] ( mprj mem_addr[2] ) ( mem addr0[2] ) + USE SIGNAL
- + ROUTED met2 ( 2418910 2999820 0 ) ( * 3009510 )
- NEW met2 ( 994290 334220 ) ( * 3009510 )
- NEW met1 ( 994290 3009510 ) ( 2418910 * )
+ + ROUTED met2 ( 2418910 2999820 0 ) ( * 3010190 )
+ NEW met2 ( 994290 334220 ) ( * 3010190 )
+ NEW met1 ( 994290 3010190 ) ( 2418910 * )
NEW met3 ( 994290 334220 ) ( 1000500 * )
NEW met3 ( 1000500 332790 0 ) ( * 334220 )
- NEW met1 ( 994290 3009510 ) M1M2_PR
- NEW met1 ( 2418910 3009510 ) M1M2_PR
+ NEW met1 ( 994290 3010190 ) M1M2_PR
+ NEW met1 ( 2418910 3010190 ) M1M2_PR
NEW met2 ( 994290 334220 ) M2M3_PR_M ;
- mem_addr\[3\] ( mprj mem_addr[3] ) ( mem addr0[3] ) + USE SIGNAL
- + ROUTED met2 ( 2337950 2999820 0 ) ( * 3009850 )
- NEW met2 ( 995210 337620 ) ( * 3009850 )
- NEW met1 ( 995210 3009850 ) ( 2337950 * )
+ + ROUTED met2 ( 2337950 2999820 0 ) ( * 3008830 )
+ NEW met2 ( 995210 337620 ) ( * 3008830 )
+ NEW met1 ( 995210 3008830 ) ( 2337950 * )
NEW met3 ( 995210 337620 ) ( 1000500 * )
NEW met3 ( 1000500 335510 0 ) ( * 337620 )
- NEW met1 ( 995210 3009850 ) M1M2_PR
- NEW met1 ( 2337950 3009850 ) M1M2_PR
+ NEW met1 ( 995210 3008830 ) M1M2_PR
+ NEW met1 ( 2337950 3008830 ) M1M2_PR
NEW met2 ( 995210 337620 ) M2M3_PR_M ;
- mem_addr\[4\] ( mprj mem_addr[4] ) ( mem addr0[4] ) + USE SIGNAL
- + ROUTED met2 ( 1445550 2999820 0 ) ( * 3010530 )
- NEW met2 ( 994750 342380 ) ( * 3010530 )
- NEW met1 ( 994750 3010530 ) ( 1445550 * )
+ + ROUTED met2 ( 1445550 2999820 0 ) ( * 3009510 )
+ NEW met2 ( 994750 342380 ) ( * 3009510 )
+ NEW met1 ( 994750 3009510 ) ( 1445550 * )
NEW met3 ( 994750 342380 ) ( 1000500 * )
NEW met3 ( 1000500 341630 0 ) ( * 342380 )
- NEW met1 ( 994750 3010530 ) M1M2_PR
- NEW met1 ( 1445550 3010530 ) M1M2_PR
+ NEW met1 ( 994750 3009510 ) M1M2_PR
+ NEW met1 ( 1445550 3009510 ) M1M2_PR
NEW met2 ( 994750 342380 ) M2M3_PR_M ;
- mem_addr\[5\] ( mprj mem_addr[5] ) ( mem addr0[5] ) + USE SIGNAL
- + ROUTED met2 ( 995670 344420 ) ( * 3010190 )
- NEW met2 ( 1607470 2999820 0 ) ( * 3010190 )
- NEW met1 ( 995670 3010190 ) ( 1607470 * )
+ + ROUTED met2 ( 995670 344420 ) ( * 3009170 )
+ NEW met2 ( 1607470 2999820 0 ) ( * 3009170 )
+ NEW met1 ( 995670 3009170 ) ( 1607470 * )
NEW met3 ( 995670 344420 ) ( 1000500 * )
NEW met3 ( 1000500 343670 0 ) ( * 344420 )
- NEW met1 ( 995670 3010190 ) M1M2_PR
+ NEW met1 ( 995670 3009170 ) M1M2_PR
NEW met2 ( 995670 344420 ) M2M3_PR_M
- NEW met1 ( 1607470 3010190 ) M1M2_PR ;
+ NEW met1 ( 1607470 3009170 ) M1M2_PR ;
- mem_addr\[6\] ( mprj mem_addr[6] ) ( mem addr0[6] ) + USE SIGNAL
+ ROUTED met3 ( 1000500 349180 ) ( 1000730 * )
NEW met3 ( 1000500 349180 ) ( * 350470 0 )
- NEW met2 ( 1000730 349180 ) ( * 1489030 )
- NEW met2 ( 1810790 1489030 ) ( * 1500420 0 )
- NEW met1 ( 1000730 1489030 ) ( 1810790 * )
+ NEW met2 ( 1000730 349180 ) ( * 1486990 )
+ NEW met2 ( 1810790 1486990 ) ( * 1500420 0 )
+ NEW met1 ( 1000730 1486990 ) ( 1810790 * )
NEW met2 ( 1000730 349180 ) M2M3_PR_M
- NEW met1 ( 1000730 1489030 ) M1M2_PR
- NEW met1 ( 1810790 1489030 ) M1M2_PR ;
+ NEW met1 ( 1000730 1486990 ) M1M2_PR
+ NEW met1 ( 1810790 1486990 ) M1M2_PR ;
- mem_addr\[7\] ( mprj mem_addr[7] ) ( mem addr0[7] ) + USE SIGNAL
- + ROUTED met2 ( 991530 354620 ) ( * 2098820 )
- NEW met3 ( 991530 354620 ) ( 1000500 * )
+ + ROUTED met2 ( 991070 354620 ) ( * 2098820 )
+ NEW met3 ( 991070 354620 ) ( 1000500 * )
NEW met3 ( 1000500 351830 0 ) ( * 354620 )
- NEW met3 ( 991530 2098820 ) ( 1000500 * 0 )
- NEW met2 ( 991530 354620 ) M2M3_PR_M
- NEW met2 ( 991530 2098820 ) M2M3_PR_M ;
+ NEW met3 ( 991070 2098820 ) ( 1000500 * 0 )
+ NEW met2 ( 991070 354620 ) M2M3_PR_M
+ NEW met2 ( 991070 2098820 ) M2M3_PR_M ;
- mem_wr ( mprj mem_wr ) ( mem web0 ) + USE SIGNAL
- + ROUTED met2 ( 997050 225420 ) ( * 3010870 )
- NEW met3 ( 997050 225420 ) ( 1000500 * )
+ + ROUTED met2 ( 993830 225420 ) ( * 3009850 )
+ NEW met3 ( 993830 225420 ) ( 1000500 * )
NEW met3 ( 1000500 222630 0 ) ( * 225420 )
- NEW met2 ( 1120790 2999820 0 ) ( * 3010870 )
- NEW met1 ( 997050 3010870 ) ( 1120790 * )
- NEW met2 ( 997050 225420 ) M2M3_PR_M
- NEW met1 ( 997050 3010870 ) M1M2_PR
- NEW met1 ( 1120790 3010870 ) M1M2_PR ;
+ NEW met2 ( 1120790 2999820 0 ) ( * 3009850 )
+ NEW met1 ( 993830 3009850 ) ( 1120790 * )
+ NEW met2 ( 993830 225420 ) M2M3_PR_M
+ NEW met1 ( 993830 3009850 ) M1M2_PR
+ NEW met1 ( 1120790 3009850 ) M1M2_PR ;
- user_clock2 ( PIN user_clock2 ) + USE SIGNAL ;
- user_irq[0] ( PIN user_irq[0] ) + USE SIGNAL ;
- user_irq[1] ( PIN user_irq[1] ) + USE SIGNAL ;
@@ -8717,25 +9296,9 @@
NEW met2 ( 1035230 192780 ) M2M3_PR_M
NEW met3 ( 1004180 3008660 ) M3M4_PR_M
NEW met3 ( 1035230 192780 ) RECT ( -800 -150 0 150 ) ;
- - wb_rst_i ( PIN wb_rst_i ) ( mprj reset ) + USE SIGNAL
- + ROUTED met2 ( 8510 2380 0 ) ( * 17510 )
- NEW met3 ( 2499180 2040340 0 ) ( 2514130 * )
- NEW met2 ( 2514130 17510 ) ( * 2040340 )
- NEW met1 ( 8510 17510 ) ( 2514130 * )
- NEW met1 ( 8510 17510 ) M1M2_PR
- NEW met1 ( 2514130 17510 ) M1M2_PR
- NEW met2 ( 2514130 2040340 ) M2M3_PR_M ;
+ - wb_rst_i ( PIN wb_rst_i ) + USE SIGNAL ;
- wbs_ack_o ( PIN wbs_ack_o ) + USE SIGNAL ;
- - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) ( mprj init_addr[0] ) + USE SIGNAL
- + ROUTED met2 ( 2499870 2999820 0 ) ( * 3011210 )
- NEW met2 ( 38410 2380 0 ) ( * 17850 )
- NEW met1 ( 38410 17850 ) ( 41170 * )
- NEW met1 ( 41170 3011210 ) ( 2499870 * )
- NEW met2 ( 41170 17850 ) ( * 3011210 )
- NEW met1 ( 2499870 3011210 ) M1M2_PR
- NEW met1 ( 38410 17850 ) M1M2_PR
- NEW met1 ( 41170 17850 ) M1M2_PR
- NEW met1 ( 41170 3011210 ) M1M2_PR ;
+ - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) + USE SIGNAL ;
- wbs_adr_i[10] ( PIN wbs_adr_i[10] ) + USE SIGNAL ;
- wbs_adr_i[11] ( PIN wbs_adr_i[11] ) + USE SIGNAL ;
- wbs_adr_i[12] ( PIN wbs_adr_i[12] ) + USE SIGNAL ;
@@ -8746,16 +9309,7 @@
- wbs_adr_i[17] ( PIN wbs_adr_i[17] ) + USE SIGNAL ;
- wbs_adr_i[18] ( PIN wbs_adr_i[18] ) + USE SIGNAL ;
- wbs_adr_i[19] ( PIN wbs_adr_i[19] ) + USE SIGNAL ;
- - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) ( mprj init_addr[1] ) + USE SIGNAL
- + ROUTED met2 ( 61870 2380 0 ) ( * 17340 )
- NEW met2 ( 60950 17340 ) ( 61870 * )
- NEW met2 ( 60950 82800 ) ( 61410 * )
- NEW met2 ( 60950 17340 ) ( * 82800 )
- NEW met2 ( 61410 82800 ) ( * 1487670 )
- NEW met2 ( 1486950 1487670 ) ( * 1500420 0 )
- NEW met1 ( 61410 1487670 ) ( 1486950 * )
- NEW met1 ( 61410 1487670 ) M1M2_PR
- NEW met1 ( 1486950 1487670 ) M1M2_PR ;
+ - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) + USE SIGNAL ;
- wbs_adr_i[20] ( PIN wbs_adr_i[20] ) + USE SIGNAL ;
- wbs_adr_i[21] ( PIN wbs_adr_i[21] ) + USE SIGNAL ;
- wbs_adr_i[22] ( PIN wbs_adr_i[22] ) + USE SIGNAL ;
@@ -8766,505 +9320,50 @@
- wbs_adr_i[27] ( PIN wbs_adr_i[27] ) + USE SIGNAL ;
- wbs_adr_i[28] ( PIN wbs_adr_i[28] ) + USE SIGNAL ;
- wbs_adr_i[29] ( PIN wbs_adr_i[29] ) + USE SIGNAL ;
- - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) ( mprj init_addr[2] ) + USE SIGNAL
- + ROUTED met2 ( 85330 2380 0 ) ( * 17340 )
- NEW met3 ( 2499180 2520420 0 ) ( 2512290 * )
- NEW met2 ( 2512290 17340 ) ( * 2520420 )
- NEW met3 ( 85330 17340 ) ( 2512290 * )
- NEW met2 ( 85330 17340 ) M2M3_PR_M
- NEW met2 ( 2512290 17340 ) M2M3_PR_M
- NEW met2 ( 2512290 2520420 ) M2M3_PR_M ;
+ - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) + USE SIGNAL ;
- wbs_adr_i[30] ( PIN wbs_adr_i[30] ) + USE SIGNAL ;
- wbs_adr_i[31] ( PIN wbs_adr_i[31] ) + USE SIGNAL ;
- - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) ( mprj init_addr[3] ) + USE SIGNAL
- + ROUTED met2 ( 109250 2380 0 ) ( * 34500 )
- NEW met2 ( 109250 34500 ) ( 110170 * )
- NEW met2 ( 110170 34500 ) ( * 1487330 )
- NEW met2 ( 2216510 1487330 ) ( * 1500420 0 )
- NEW met1 ( 110170 1487330 ) ( 2216510 * )
- NEW met1 ( 110170 1487330 ) M1M2_PR
- NEW met1 ( 2216510 1487330 ) M1M2_PR ;
- - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) ( mprj init_addr[4] ) + USE SIGNAL
- + ROUTED met2 ( 132710 2380 0 ) ( * 17850 )
- NEW met1 ( 132710 17850 ) ( 137770 * )
- NEW met2 ( 1689350 2999820 0 ) ( * 3009170 )
- NEW met1 ( 137770 3009170 ) ( 1689350 * )
- NEW met2 ( 137770 17850 ) ( * 3009170 )
- NEW met1 ( 132710 17850 ) M1M2_PR
- NEW met1 ( 137770 17850 ) M1M2_PR
- NEW met1 ( 137770 3009170 ) M1M2_PR
- NEW met1 ( 1689350 3009170 ) M1M2_PR ;
- - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) ( mprj init_addr[5] ) + USE SIGNAL
- + ROUTED met3 ( 2499180 1920660 0 ) ( 2514590 * )
- NEW met2 ( 2514590 17850 ) ( * 1920660 )
- NEW met2 ( 150650 2380 0 ) ( * 18190 )
- NEW met1 ( 150650 18190 ) ( 172730 * )
- NEW met1 ( 172730 17850 ) ( * 18190 )
- NEW met1 ( 172730 17850 ) ( 2514590 * )
- NEW met1 ( 2514590 17850 ) M1M2_PR
- NEW met2 ( 2514590 1920660 ) M2M3_PR_M
- NEW met1 ( 150650 18190 ) M1M2_PR ;
- - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) ( mprj init_addr[6] ) + USE SIGNAL
- + ROUTED met2 ( 1162190 1488690 ) ( * 1500420 0 )
- NEW met2 ( 168130 2380 0 ) ( * 17850 )
- NEW met1 ( 168130 17850 ) ( 172270 * )
- NEW met2 ( 172270 17850 ) ( * 1488690 )
- NEW met1 ( 172270 1488690 ) ( 1162190 * )
- NEW met1 ( 1162190 1488690 ) M1M2_PR
- NEW met1 ( 168130 17850 ) M1M2_PR
- NEW met1 ( 172270 17850 ) M1M2_PR
- NEW met1 ( 172270 1488690 ) M1M2_PR ;
- - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) ( mprj init_addr[7] ) + USE SIGNAL
- + ROUTED met2 ( 186070 2380 0 ) ( * 17340 )
- NEW met2 ( 185150 17340 ) ( 186070 * )
- NEW met2 ( 185150 82800 ) ( 185610 * )
- NEW met2 ( 185150 17340 ) ( * 82800 )
- NEW met2 ( 185610 82800 ) ( * 1488010 )
- NEW met2 ( 1405070 1488010 ) ( * 1500420 0 )
- NEW met1 ( 185610 1488010 ) ( 1405070 * )
- NEW met1 ( 185610 1488010 ) M1M2_PR
- NEW met1 ( 1405070 1488010 ) M1M2_PR ;
+ - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) + USE SIGNAL ;
+ - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) + USE SIGNAL ;
+ - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) + USE SIGNAL ;
+ - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) + USE SIGNAL ;
+ - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) + USE SIGNAL ;
- wbs_adr_i[8] ( PIN wbs_adr_i[8] ) + USE SIGNAL ;
- wbs_adr_i[9] ( PIN wbs_adr_i[9] ) + USE SIGNAL ;
- wbs_cyc_i ( PIN wbs_cyc_i ) + USE SIGNAL ;
- - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) ( mem din0[0] ) + USE SIGNAL
- + ROUTED met2 ( 43930 2380 0 ) ( * 18870 )
- NEW met1 ( 43930 18870 ) ( 1124930 * )
- NEW met3 ( 1124930 198900 ) ( 1131140 * )
- NEW met4 ( 1131140 198900 ) ( 1131430 * )
- NEW met4 ( 1131430 198900 ) ( * 202300 0 )
- NEW met2 ( 1124930 18870 ) ( * 198900 )
- NEW met1 ( 43930 18870 ) M1M2_PR
- NEW met1 ( 1124930 18870 ) M1M2_PR
- NEW met2 ( 1124930 198900 ) M2M3_PR_M
- NEW met3 ( 1131140 198900 ) M3M4_PR_M ;
- - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) ( mem din0[10] ) + USE SIGNAL
- + ROUTED met3 ( 1262700 198900 ) ( 1262930 * )
- NEW met4 ( 1262670 198900 ) ( 1262700 * )
- NEW met4 ( 1262670 198900 ) ( * 202300 0 )
- NEW met2 ( 1262930 20570 ) ( * 198900 )
- NEW met2 ( 244950 2380 0 ) ( * 20570 )
- NEW met1 ( 244950 20570 ) ( 1262930 * )
- NEW met1 ( 1262930 20570 ) M1M2_PR
- NEW met2 ( 1262930 198900 ) M2M3_PR_M
- NEW met3 ( 1262700 198900 ) M3M4_PR_M
- NEW met1 ( 244950 20570 ) M1M2_PR
- NEW met3 ( 1262930 198900 ) RECT ( 0 -150 390 150 ) ;
- - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) ( mem din0[11] ) + USE SIGNAL
- + ROUTED met3 ( 1269830 198900 ) ( 1275580 * )
- NEW met4 ( 1275580 198900 ) ( 1275590 * )
- NEW met4 ( 1275590 198900 ) ( * 202300 0 )
- NEW met2 ( 1269830 16830 ) ( * 198900 )
- NEW met2 ( 262890 2380 0 ) ( * 16830 )
- NEW met1 ( 262890 16830 ) ( 1269830 * )
- NEW met1 ( 1269830 16830 ) M1M2_PR
- NEW met2 ( 1269830 198900 ) M2M3_PR_M
- NEW met3 ( 1275580 198900 ) M3M4_PR_M
- NEW met1 ( 262890 16830 ) M1M2_PR ;
- - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) ( mem din0[12] ) + USE SIGNAL
- + ROUTED met2 ( 280370 2380 0 ) ( * 16490 )
- NEW met3 ( 1283630 198900 ) ( 1288460 * )
- NEW met4 ( 1288460 198900 ) ( 1288510 * )
- NEW met4 ( 1288510 198900 ) ( * 202300 0 )
- NEW met2 ( 1283630 16490 ) ( * 198900 )
- NEW met1 ( 280370 16490 ) ( 1283630 * )
- NEW met1 ( 280370 16490 ) M1M2_PR
- NEW met1 ( 1283630 16490 ) M1M2_PR
- NEW met2 ( 1283630 198900 ) M2M3_PR_M
- NEW met3 ( 1288460 198900 ) M3M4_PR_M ;
- - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) ( mem din0[13] ) + USE SIGNAL
- + ROUTED met2 ( 298310 2380 0 ) ( * 16150 )
- NEW met1 ( 298310 16150 ) ( 1297430 * )
- NEW met3 ( 1297430 198900 ) ( 1301340 * )
- NEW met4 ( 1301340 198900 ) ( 1301430 * )
- NEW met4 ( 1301430 198900 ) ( * 202300 0 )
- NEW met2 ( 1297430 16150 ) ( * 198900 )
- NEW met1 ( 298310 16150 ) M1M2_PR
- NEW met1 ( 1297430 16150 ) M1M2_PR
- NEW met2 ( 1297430 198900 ) M2M3_PR_M
- NEW met3 ( 1301340 198900 ) M3M4_PR_M ;
- - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) ( mem din0[14] ) + USE SIGNAL
- + ROUTED met2 ( 316250 2380 0 ) ( * 15810 )
- NEW met1 ( 316250 15810 ) ( 1311230 * )
- NEW met3 ( 1311230 198900 ) ( 1315140 * )
- NEW met4 ( 1315030 198900 ) ( 1315140 * )
- NEW met4 ( 1315030 198900 ) ( * 202300 0 )
- NEW met2 ( 1311230 15810 ) ( * 198900 )
- NEW met1 ( 316250 15810 ) M1M2_PR
- NEW met1 ( 1311230 15810 ) M1M2_PR
- NEW met2 ( 1311230 198900 ) M2M3_PR_M
- NEW met3 ( 1315140 198900 ) M3M4_PR_M ;
- - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) ( mem din0[15] ) + USE SIGNAL
- + ROUTED met2 ( 333730 2380 0 ) ( * 15470 )
- NEW met1 ( 333730 15470 ) ( 1325030 * )
- NEW met3 ( 1325030 193460 ) ( 1328020 * )
- NEW met4 ( 1328020 193460 ) ( * 198900 )
- NEW met4 ( 1328020 198900 ) ( 1328630 * )
- NEW met4 ( 1328630 198900 ) ( * 202300 0 )
- NEW met2 ( 1325030 15470 ) ( * 193460 )
- NEW met1 ( 333730 15470 ) M1M2_PR
- NEW met1 ( 1325030 15470 ) M1M2_PR
- NEW met2 ( 1325030 193460 ) M2M3_PR_M
- NEW met3 ( 1328020 193460 ) M3M4_PR_M ;
- - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) ( mem din0[16] ) + USE SIGNAL
- + ROUTED met2 ( 351670 2380 0 ) ( * 15130 )
- NEW met1 ( 351670 15130 ) ( 1338830 * )
- NEW met3 ( 1338830 193460 ) ( 1340900 * )
- NEW met4 ( 1340900 193460 ) ( * 198900 )
- NEW met4 ( 1340870 198900 ) ( 1340900 * )
- NEW met4 ( 1340870 198900 ) ( * 202300 0 )
- NEW met2 ( 1338830 15130 ) ( * 193460 )
- NEW met1 ( 1338830 15130 ) M1M2_PR
- NEW met1 ( 351670 15130 ) M1M2_PR
- NEW met2 ( 1338830 193460 ) M2M3_PR_M
- NEW met3 ( 1340900 193460 ) M3M4_PR_M ;
- - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) ( mem din0[17] ) + USE SIGNAL
- + ROUTED met2 ( 369150 2380 0 ) ( * 14790 )
- NEW met1 ( 369150 14790 ) ( 1352630 * )
- NEW met3 ( 1352630 198900 ) ( 1354700 * )
- NEW met4 ( 1354470 198900 ) ( 1354700 * )
- NEW met4 ( 1354470 198900 ) ( * 202300 0 )
- NEW met2 ( 1352630 14790 ) ( * 198900 )
- NEW met1 ( 1352630 14790 ) M1M2_PR
- NEW met1 ( 369150 14790 ) M1M2_PR
- NEW met2 ( 1352630 198900 ) M2M3_PR_M
- NEW met3 ( 1354700 198900 ) M3M4_PR_M ;
- - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) ( mem din0[18] ) + USE SIGNAL
- + ROUTED met2 ( 387090 2380 0 ) ( * 14450 )
- NEW met1 ( 387090 14450 ) ( 393070 * )
- NEW met2 ( 393070 14450 ) ( * 195330 )
- NEW met2 ( 1366890 195330 ) ( * 198900 )
- NEW met3 ( 1366890 198900 ) ( 1367580 * )
- NEW met4 ( 1367390 198900 ) ( 1367580 * )
- NEW met4 ( 1367390 198900 ) ( * 202300 0 )
- NEW met1 ( 393070 195330 ) ( 1366890 * )
- NEW met1 ( 387090 14450 ) M1M2_PR
- NEW met1 ( 393070 14450 ) M1M2_PR
- NEW met1 ( 393070 195330 ) M1M2_PR
- NEW met1 ( 1366890 195330 ) M1M2_PR
- NEW met2 ( 1366890 198900 ) M2M3_PR_M
- NEW met3 ( 1367580 198900 ) M3M4_PR_M ;
- - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) ( mem din0[19] ) + USE SIGNAL
- + ROUTED met2 ( 404570 2380 0 ) ( * 14450 )
- NEW met1 ( 404570 14450 ) ( 406870 * )
- NEW met2 ( 406870 14450 ) ( * 194990 )
- NEW met2 ( 1380230 194990 ) ( * 195500 )
- NEW met3 ( 1380230 195500 ) ( 1380460 * )
- NEW met4 ( 1380460 195500 ) ( * 198900 )
- NEW met4 ( 1380460 198900 ) ( 1380990 * )
- NEW met4 ( 1380990 198900 ) ( * 202300 0 )
- NEW met1 ( 406870 194990 ) ( 1380230 * )
- NEW met1 ( 404570 14450 ) M1M2_PR
- NEW met1 ( 406870 14450 ) M1M2_PR
- NEW met1 ( 406870 194990 ) M1M2_PR
- NEW met1 ( 1380230 194990 ) M1M2_PR
- NEW met2 ( 1380230 195500 ) M2M3_PR_M
- NEW met3 ( 1380460 195500 ) M3M4_PR_M
- NEW met3 ( 1380230 195500 ) RECT ( -390 -150 0 150 ) ;
- - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) ( mem din0[1] ) + USE SIGNAL
- + ROUTED met2 ( 1138730 193290 ) ( * 193460 )
- NEW met3 ( 1138730 193460 ) ( 1143100 * )
- NEW met4 ( 1143100 193460 ) ( * 198900 )
- NEW met4 ( 1143100 198900 ) ( 1143670 * )
- NEW met4 ( 1143670 198900 ) ( * 202300 0 )
- NEW met1 ( 68770 193290 ) ( 1138730 * )
- NEW met2 ( 67850 2380 0 ) ( * 34500 )
- NEW met2 ( 67850 34500 ) ( 68770 * )
- NEW met2 ( 68770 34500 ) ( * 193290 )
- NEW met1 ( 68770 193290 ) M1M2_PR
- NEW met1 ( 1138730 193290 ) M1M2_PR
- NEW met2 ( 1138730 193460 ) M2M3_PR_M
- NEW met3 ( 1143100 193460 ) M3M4_PR_M ;
- - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) ( mem din0[20] ) + USE SIGNAL
- + ROUTED met2 ( 422510 2380 0 ) ( * 14450 )
- NEW met1 ( 422510 14450 ) ( 427570 * )
- NEW met2 ( 427570 14450 ) ( * 196010 )
- NEW met2 ( 1392650 196010 ) ( * 198900 )
- NEW met3 ( 1392650 198900 ) ( 1393340 * )
- NEW met4 ( 1393230 198900 ) ( 1393340 * )
- NEW met4 ( 1393230 198900 ) ( * 202300 0 )
- NEW met1 ( 427570 196010 ) ( 1392650 * )
- NEW met1 ( 422510 14450 ) M1M2_PR
- NEW met1 ( 427570 14450 ) M1M2_PR
- NEW met1 ( 427570 196010 ) M1M2_PR
- NEW met1 ( 1392650 196010 ) M1M2_PR
- NEW met2 ( 1392650 198900 ) M2M3_PR_M
- NEW met3 ( 1393340 198900 ) M3M4_PR_M ;
- - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) ( mem din0[21] ) + USE SIGNAL
- + ROUTED met2 ( 439990 2380 0 ) ( * 34500 )
- NEW met2 ( 439990 34500 ) ( 441370 * )
- NEW met2 ( 441370 34500 ) ( * 195670 )
- NEW met2 ( 1400930 195670 ) ( * 196180 )
- NEW met3 ( 1400930 196180 ) ( 1406220 * )
- NEW met4 ( 1406220 196180 ) ( * 198900 )
- NEW met4 ( 1406220 198900 ) ( 1406830 * )
- NEW met4 ( 1406830 198900 ) ( * 202300 0 )
- NEW met1 ( 441370 195670 ) ( 1400930 * )
- NEW met1 ( 441370 195670 ) M1M2_PR
- NEW met1 ( 1400930 195670 ) M1M2_PR
- NEW met2 ( 1400930 196180 ) M2M3_PR_M
- NEW met3 ( 1406220 196180 ) M3M4_PR_M ;
- - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) ( mem din0[22] ) + USE SIGNAL
- + ROUTED met2 ( 457930 2380 0 ) ( * 14450 )
- NEW met1 ( 457930 14450 ) ( 462070 * )
- NEW met2 ( 1414730 196350 ) ( * 196860 )
- NEW met3 ( 1414730 196860 ) ( 1420020 * )
- NEW met4 ( 1420020 196860 ) ( * 198900 )
- NEW met4 ( 1420020 198900 ) ( 1420430 * )
- NEW met4 ( 1420430 198900 ) ( * 202300 0 )
- NEW met2 ( 462070 14450 ) ( * 196350 )
- NEW met1 ( 462070 196350 ) ( 1414730 * )
- NEW met1 ( 457930 14450 ) M1M2_PR
- NEW met1 ( 462070 14450 ) M1M2_PR
- NEW met1 ( 462070 196350 ) M1M2_PR
- NEW met1 ( 1414730 196350 ) M1M2_PR
- NEW met2 ( 1414730 196860 ) M2M3_PR_M
- NEW met3 ( 1420020 196860 ) M3M4_PR_M ;
- - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) ( mem din0[23] ) + USE SIGNAL
- + ROUTED met2 ( 475870 2380 0 ) ( * 196690 )
- NEW met2 ( 1428530 196690 ) ( * 196860 )
- NEW met3 ( 1428530 196860 ) ( 1432900 * )
- NEW met4 ( 1432900 196860 ) ( * 198900 )
- NEW met4 ( 1432900 198900 ) ( 1433350 * )
- NEW met4 ( 1433350 198900 ) ( * 202300 0 )
- NEW met1 ( 475870 196690 ) ( 1428530 * )
- NEW met1 ( 475870 196690 ) M1M2_PR
- NEW met1 ( 1428530 196690 ) M1M2_PR
- NEW met2 ( 1428530 196860 ) M2M3_PR_M
- NEW met3 ( 1432900 196860 ) M3M4_PR_M ;
- - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) ( mem din0[24] ) + USE SIGNAL
- + ROUTED met2 ( 493350 2380 0 ) ( * 14450 )
- NEW met1 ( 493350 14450 ) ( 496570 * )
- NEW met2 ( 1442330 197030 ) ( * 198900 )
- NEW met3 ( 1442330 198900 ) ( 1445780 * )
- NEW met4 ( 1445590 198900 ) ( 1445780 * )
- NEW met4 ( 1445590 198900 ) ( * 202300 0 )
- NEW met2 ( 496570 14450 ) ( * 197030 )
- NEW met1 ( 496570 197030 ) ( 1442330 * )
- NEW met1 ( 493350 14450 ) M1M2_PR
- NEW met1 ( 496570 14450 ) M1M2_PR
- NEW met1 ( 496570 197030 ) M1M2_PR
- NEW met1 ( 1442330 197030 ) M1M2_PR
- NEW met2 ( 1442330 198900 ) M2M3_PR_M
- NEW met3 ( 1445780 198900 ) M3M4_PR_M ;
- - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) ( mem din0[25] ) + USE SIGNAL
- + ROUTED met2 ( 511290 2380 0 ) ( * 14450 )
- NEW met1 ( 511290 14450 ) ( 517270 * )
- NEW met2 ( 1457970 197370 ) ( * 198220 )
- NEW met3 ( 1457970 198220 ) ( 1458660 * )
- NEW met4 ( 1458660 198220 ) ( * 198900 )
- NEW met4 ( 1458660 198900 ) ( 1459190 * )
- NEW met4 ( 1459190 198900 ) ( * 202300 0 )
- NEW met2 ( 517270 14450 ) ( * 197370 )
- NEW met1 ( 517270 197370 ) ( 1457970 * )
- NEW met1 ( 511290 14450 ) M1M2_PR
- NEW met1 ( 517270 14450 ) M1M2_PR
- NEW met1 ( 517270 197370 ) M1M2_PR
- NEW met1 ( 1457970 197370 ) M1M2_PR
- NEW met2 ( 1457970 198220 ) M2M3_PR_M
- NEW met3 ( 1458660 198220 ) M3M4_PR_M ;
- - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) ( mem din0[26] ) + USE SIGNAL
- + ROUTED met2 ( 1469930 197710 ) ( * 198220 )
- NEW met3 ( 1469930 198220 ) ( 1471540 * )
- NEW met4 ( 1471540 198220 ) ( * 198900 )
- NEW met4 ( 1471540 198900 ) ( 1472110 * )
- NEW met4 ( 1472110 198900 ) ( * 202300 0 )
- NEW met2 ( 528770 2380 0 ) ( * 14450 )
- NEW met1 ( 528770 14450 ) ( 531070 * )
- NEW met2 ( 531070 14450 ) ( * 197710 )
- NEW met1 ( 531070 197710 ) ( 1469930 * )
- NEW met1 ( 1469930 197710 ) M1M2_PR
- NEW met2 ( 1469930 198220 ) M2M3_PR_M
- NEW met3 ( 1471540 198220 ) M3M4_PR_M
- NEW met1 ( 528770 14450 ) M1M2_PR
- NEW met1 ( 531070 14450 ) M1M2_PR
- NEW met1 ( 531070 197710 ) M1M2_PR ;
- - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) ( mem din0[27] ) + USE SIGNAL
- + ROUTED met2 ( 546710 2380 0 ) ( * 14450 )
- NEW met1 ( 546710 14450 ) ( 551770 * )
- NEW met2 ( 1484190 198050 ) ( * 198220 )
- NEW met3 ( 1484190 198220 ) ( 1484420 * )
- NEW met4 ( 1484420 198220 ) ( * 198900 )
- NEW met4 ( 1484420 198900 ) ( 1485030 * )
- NEW met4 ( 1485030 198900 ) ( * 202300 0 )
- NEW met2 ( 551770 14450 ) ( * 198050 )
- NEW met1 ( 551770 198050 ) ( 1484190 * )
- NEW met1 ( 546710 14450 ) M1M2_PR
- NEW met1 ( 551770 14450 ) M1M2_PR
- NEW met1 ( 551770 198050 ) M1M2_PR
- NEW met1 ( 1484190 198050 ) M1M2_PR
- NEW met2 ( 1484190 198220 ) M2M3_PR_M
- NEW met3 ( 1484420 198220 ) M3M4_PR_M
- NEW met3 ( 1484190 198220 ) RECT ( -390 -150 0 150 ) ;
- - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) ( mem din0[28] ) + USE SIGNAL
- + ROUTED met2 ( 1497530 198220 ) ( * 198390 )
- NEW met3 ( 1497530 198220 ) ( 1499140 * )
- NEW met4 ( 1499140 198220 ) ( * 198900 )
- NEW met4 ( 1499140 198900 ) ( 1499310 * )
- NEW met4 ( 1499310 198900 ) ( * 202300 0 )
- NEW met2 ( 564190 2380 0 ) ( * 34500 )
- NEW met2 ( 564190 34500 ) ( 565570 * )
- NEW met2 ( 565570 34500 ) ( * 198390 )
- NEW met1 ( 565570 198390 ) ( 1497530 * )
- NEW met1 ( 565570 198390 ) M1M2_PR
- NEW met1 ( 1497530 198390 ) M1M2_PR
- NEW met2 ( 1497530 198220 ) M2M3_PR_M
- NEW met3 ( 1499140 198220 ) M3M4_PR_M ;
- - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) ( mem din0[29] ) + USE SIGNAL
- + ROUTED met2 ( 582130 2380 0 ) ( * 14450 )
- NEW met1 ( 582130 14450 ) ( 1511330 * )
- NEW met3 ( 1511330 193460 ) ( 1512020 * )
- NEW met4 ( 1512020 193460 ) ( * 198900 )
- NEW met4 ( 1512020 198900 ) ( 1512230 * )
- NEW met4 ( 1512230 198900 ) ( * 202300 0 )
- NEW met2 ( 1511330 14450 ) ( * 193460 )
- NEW met1 ( 582130 14450 ) M1M2_PR
- NEW met1 ( 1511330 14450 ) M1M2_PR
- NEW met2 ( 1511330 193460 ) M2M3_PR_M
- NEW met3 ( 1512020 193460 ) M3M4_PR_M ;
- - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) ( mem din0[2] ) + USE SIGNAL
- + ROUTED met2 ( 91310 2380 0 ) ( * 14450 )
- NEW met1 ( 91310 14450 ) ( 96370 * )
- NEW met2 ( 1152530 193630 ) ( * 198900 )
- NEW met3 ( 1152530 198900 ) ( 1157820 * )
- NEW met4 ( 1157820 198900 ) ( 1157950 * )
- NEW met4 ( 1157950 198900 ) ( * 202300 0 )
- NEW met2 ( 96370 14450 ) ( * 193630 )
- NEW met1 ( 96370 193630 ) ( 1152530 * )
- NEW met1 ( 91310 14450 ) M1M2_PR
- NEW met1 ( 96370 14450 ) M1M2_PR
- NEW met1 ( 96370 193630 ) M1M2_PR
- NEW met1 ( 1152530 193630 ) M1M2_PR
- NEW met2 ( 1152530 198900 ) M2M3_PR_M
- NEW met3 ( 1157820 198900 ) M3M4_PR_M ;
- - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) ( mem din0[30] ) + USE SIGNAL
- + ROUTED met2 ( 599610 2380 0 ) ( * 14110 )
- NEW met1 ( 599610 14110 ) ( 1518230 * )
- NEW met3 ( 1518230 193460 ) ( 1523980 * )
- NEW met4 ( 1523980 193460 ) ( * 198900 )
- NEW met4 ( 1523980 198900 ) ( 1524470 * )
- NEW met4 ( 1524470 198900 ) ( * 202300 0 )
- NEW met2 ( 1518230 14110 ) ( * 193460 )
- NEW met1 ( 599610 14110 ) M1M2_PR
- NEW met1 ( 1518230 14110 ) M1M2_PR
- NEW met2 ( 1518230 193460 ) M2M3_PR_M
- NEW met3 ( 1523980 193460 ) M3M4_PR_M ;
- - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) ( mem din0[31] ) + USE SIGNAL
- + ROUTED met2 ( 1535250 198730 ) ( * 198900 )
- NEW met3 ( 1535250 198900 ) ( 1537780 * )
- NEW met4 ( 1537780 198900 ) ( 1538070 * )
- NEW met4 ( 1538070 198900 ) ( * 202300 0 )
- NEW met2 ( 617550 2380 0 ) ( * 34500 )
- NEW met2 ( 617550 34500 ) ( 620770 * )
- NEW met2 ( 620770 34500 ) ( * 198730 )
- NEW met1 ( 620770 198730 ) ( 1535250 * )
- NEW met1 ( 1535250 198730 ) M1M2_PR
- NEW met2 ( 1535250 198900 ) M2M3_PR_M
- NEW met3 ( 1537780 198900 ) M3M4_PR_M
- NEW met1 ( 620770 198730 ) M1M2_PR ;
- - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) ( mem din0[3] ) + USE SIGNAL
- + ROUTED met2 ( 115230 2380 0 ) ( * 19210 )
- NEW met3 ( 1166330 193460 ) ( 1169780 * )
- NEW met4 ( 1169780 193460 ) ( * 198900 )
- NEW met4 ( 1169780 198900 ) ( 1170190 * )
- NEW met4 ( 1170190 198900 ) ( * 202300 0 )
- NEW met2 ( 1166330 19210 ) ( * 193460 )
- NEW met1 ( 115230 19210 ) ( 1166330 * )
- NEW met1 ( 115230 19210 ) M1M2_PR
- NEW met1 ( 1166330 19210 ) M1M2_PR
- NEW met2 ( 1166330 193460 ) M2M3_PR_M
- NEW met3 ( 1169780 193460 ) M3M4_PR_M ;
- - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) ( mem din0[4] ) + USE SIGNAL
- + ROUTED met2 ( 1180130 193970 ) ( * 194140 )
- NEW met3 ( 1180130 194140 ) ( 1182660 * )
- NEW met4 ( 1182660 194140 ) ( * 198900 )
- NEW met4 ( 1182660 198900 ) ( 1183110 * )
- NEW met4 ( 1183110 198900 ) ( * 202300 0 )
- NEW met2 ( 138690 2380 0 ) ( * 17850 )
- NEW met1 ( 138690 17850 ) ( 144670 * )
- NEW met1 ( 144670 193970 ) ( 1180130 * )
- NEW met2 ( 144670 17850 ) ( * 193970 )
- NEW met1 ( 1180130 193970 ) M1M2_PR
- NEW met2 ( 1180130 194140 ) M2M3_PR_M
- NEW met3 ( 1182660 194140 ) M3M4_PR_M
- NEW met1 ( 138690 17850 ) M1M2_PR
- NEW met1 ( 144670 17850 ) M1M2_PR
- NEW met1 ( 144670 193970 ) M1M2_PR ;
- - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) ( mem din0[5] ) + USE SIGNAL
- + ROUTED met2 ( 156630 2380 0 ) ( * 19550 )
- NEW met1 ( 156630 19550 ) ( 1193930 * )
- NEW met3 ( 1193930 193460 ) ( 1196460 * )
- NEW met4 ( 1196460 193460 ) ( * 200260 )
- NEW met4 ( 1196460 200260 ) ( 1196710 * )
- NEW met4 ( 1196710 200260 ) ( * 202300 0 )
- NEW met2 ( 1193930 19550 ) ( * 193460 )
- NEW met1 ( 156630 19550 ) M1M2_PR
- NEW met1 ( 1193930 19550 ) M1M2_PR
- NEW met2 ( 1193930 193460 ) M2M3_PR_M
- NEW met3 ( 1196460 193460 ) M3M4_PR_M ;
- - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) ( mem din0[6] ) + USE SIGNAL
- + ROUTED met2 ( 174110 2380 0 ) ( * 16830 )
- NEW met1 ( 174110 16830 ) ( 179170 * )
- NEW met2 ( 1207730 194310 ) ( * 198220 )
- NEW met3 ( 1207730 198220 ) ( 1209340 * )
- NEW met4 ( 1209340 198220 ) ( * 200260 )
- NEW met4 ( 1209340 200260 ) ( 1209630 * )
- NEW met4 ( 1209630 200260 ) ( * 202300 0 )
- NEW met1 ( 179170 194310 ) ( 1207730 * )
- NEW met2 ( 179170 16830 ) ( * 194310 )
- NEW met1 ( 174110 16830 ) M1M2_PR
- NEW met1 ( 179170 16830 ) M1M2_PR
- NEW met1 ( 179170 194310 ) M1M2_PR
- NEW met1 ( 1207730 194310 ) M1M2_PR
- NEW met2 ( 1207730 198220 ) M2M3_PR_M
- NEW met3 ( 1209340 198220 ) M3M4_PR_M ;
- - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) ( mem din0[7] ) + USE SIGNAL
- + ROUTED met2 ( 192050 2380 0 ) ( * 19890 )
- NEW met1 ( 192050 19890 ) ( 1221530 * )
- NEW met3 ( 1221530 193460 ) ( 1222220 * )
- NEW met4 ( 1222220 193460 ) ( * 200260 )
- NEW met4 ( 1222220 200260 ) ( 1222550 * )
- NEW met4 ( 1222550 200260 ) ( * 202300 0 )
- NEW met2 ( 1221530 19890 ) ( * 193460 )
- NEW met1 ( 192050 19890 ) M1M2_PR
- NEW met1 ( 1221530 19890 ) M1M2_PR
- NEW met2 ( 1221530 193460 ) M2M3_PR_M
- NEW met3 ( 1222220 193460 ) M3M4_PR_M ;
- - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) ( mem din0[8] ) + USE SIGNAL
- + ROUTED met2 ( 209530 2380 0 ) ( * 16830 )
- NEW met1 ( 209530 16830 ) ( 213670 * )
- NEW met2 ( 213670 16830 ) ( * 194650 )
- NEW met2 ( 1235330 194650 ) ( * 194820 )
- NEW met3 ( 1235330 194820 ) ( 1236020 * )
- NEW met4 ( 1236020 194820 ) ( * 200260 )
- NEW met4 ( 1236020 200260 ) ( 1236150 * )
- NEW met4 ( 1236150 200260 ) ( * 202300 0 )
- NEW met1 ( 213670 194650 ) ( 1235330 * )
- NEW met1 ( 209530 16830 ) M1M2_PR
- NEW met1 ( 213670 16830 ) M1M2_PR
- NEW met1 ( 213670 194650 ) M1M2_PR
- NEW met1 ( 1235330 194650 ) M1M2_PR
- NEW met2 ( 1235330 194820 ) M2M3_PR_M
- NEW met3 ( 1236020 194820 ) M3M4_PR_M ;
- - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) ( mem din0[9] ) + USE SIGNAL
- + ROUTED met2 ( 227470 2380 0 ) ( * 20230 )
- NEW met3 ( 1249130 198900 ) ( 1249820 * )
- NEW met4 ( 1249750 198900 ) ( 1249820 * )
- NEW met4 ( 1249750 198900 ) ( * 202300 0 )
- NEW met2 ( 1249130 20230 ) ( * 198900 )
- NEW met1 ( 227470 20230 ) ( 1249130 * )
- NEW met1 ( 227470 20230 ) M1M2_PR
- NEW met1 ( 1249130 20230 ) M1M2_PR
- NEW met2 ( 1249130 198900 ) M2M3_PR_M
- NEW met3 ( 1249820 198900 ) M3M4_PR_M ;
- - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) ( mprj OUT[0] ) + USE SIGNAL
- + ROUTED met3 ( 2499180 2279700 0 ) ( 2513210 * )
- NEW met2 ( 2513210 16660 ) ( * 2279700 )
- NEW met2 ( 49910 2380 0 ) ( * 16660 )
- NEW met3 ( 49910 16660 ) ( 2513210 * )
- NEW met2 ( 2513210 16660 ) M2M3_PR_M
- NEW met2 ( 2513210 2279700 ) M2M3_PR_M
- NEW met2 ( 49910 16660 ) M2M3_PR_M ;
+ - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) + USE SIGNAL ;
+ - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) + USE SIGNAL ;
+ - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) + USE SIGNAL ;
+ - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) + USE SIGNAL ;
+ - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) + USE SIGNAL ;
+ - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) + USE SIGNAL ;
+ - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) + USE SIGNAL ;
+ - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) + USE SIGNAL ;
+ - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) + USE SIGNAL ;
+ - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) + USE SIGNAL ;
+ - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) + USE SIGNAL ;
+ - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) + USE SIGNAL ;
+ - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) + USE SIGNAL ;
+ - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) + USE SIGNAL ;
+ - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) + USE SIGNAL ;
+ - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) + USE SIGNAL ;
+ - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) + USE SIGNAL ;
+ - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) + USE SIGNAL ;
+ - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) + USE SIGNAL ;
+ - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) + USE SIGNAL ;
+ - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) + USE SIGNAL ;
+ - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) + USE SIGNAL ;
+ - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) + USE SIGNAL ;
+ - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) + USE SIGNAL ;
+ - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) + USE SIGNAL ;
+ - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) + USE SIGNAL ;
+ - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) + USE SIGNAL ;
+ - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) + USE SIGNAL ;
+ - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) + USE SIGNAL ;
+ - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) + USE SIGNAL ;
+ - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) + USE SIGNAL ;
+ - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) + USE SIGNAL ;
+ - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) + USE SIGNAL ;
- wbs_dat_o[10] ( PIN wbs_dat_o[10] ) + USE SIGNAL ;
- wbs_dat_o[11] ( PIN wbs_dat_o[11] ) + USE SIGNAL ;
- wbs_dat_o[12] ( PIN wbs_dat_o[12] ) + USE SIGNAL ;
@@ -9275,14 +9374,7 @@
- wbs_dat_o[17] ( PIN wbs_dat_o[17] ) + USE SIGNAL ;
- wbs_dat_o[18] ( PIN wbs_dat_o[18] ) + USE SIGNAL ;
- wbs_dat_o[19] ( PIN wbs_dat_o[19] ) + USE SIGNAL ;
- - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) ( mprj OUT[1] ) + USE SIGNAL
- + ROUTED met2 ( 2176030 2999820 0 ) ( * 3008830 )
- NEW met1 ( 75670 3008830 ) ( 2176030 * )
- NEW met2 ( 73830 2380 0 ) ( * 34500 )
- NEW met2 ( 73830 34500 ) ( 75670 * )
- NEW met2 ( 75670 34500 ) ( * 3008830 )
- NEW met1 ( 75670 3008830 ) M1M2_PR
- NEW met1 ( 2176030 3008830 ) M1M2_PR ;
+ - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) + USE SIGNAL ;
- wbs_dat_o[20] ( PIN wbs_dat_o[20] ) + USE SIGNAL ;
- wbs_dat_o[21] ( PIN wbs_dat_o[21] ) + USE SIGNAL ;
- wbs_dat_o[22] ( PIN wbs_dat_o[22] ) + USE SIGNAL ;
@@ -9293,111 +9385,21 @@
- wbs_dat_o[27] ( PIN wbs_dat_o[27] ) + USE SIGNAL ;
- wbs_dat_o[28] ( PIN wbs_dat_o[28] ) + USE SIGNAL ;
- wbs_dat_o[29] ( PIN wbs_dat_o[29] ) + USE SIGNAL ;
- - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) ( mprj OUT[2] ) + USE SIGNAL
- + ROUTED met2 ( 97290 2380 0 ) ( * 15130 )
- NEW met1 ( 97290 15130 ) ( 103270 * )
- NEW met2 ( 103270 15130 ) ( * 1486990 )
- NEW met2 ( 2460310 1486990 ) ( * 1500420 0 )
- NEW met1 ( 103270 1486990 ) ( 2460310 * )
- NEW met1 ( 97290 15130 ) M1M2_PR
- NEW met1 ( 103270 15130 ) M1M2_PR
- NEW met1 ( 103270 1486990 ) M1M2_PR
- NEW met1 ( 2460310 1486990 ) M1M2_PR ;
+ - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) + USE SIGNAL ;
- wbs_dat_o[30] ( PIN wbs_dat_o[30] ) + USE SIGNAL ;
- wbs_dat_o[31] ( PIN wbs_dat_o[31] ) + USE SIGNAL ;
- - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) ( mprj OUT[3] ) + USE SIGNAL
- + ROUTED met2 ( 121210 2380 0 ) ( * 18020 )
- NEW met3 ( 2499180 2879460 0 ) ( 2511830 * )
- NEW met2 ( 2511830 18020 ) ( * 2879460 )
- NEW met3 ( 121210 18020 ) ( 2511830 * )
- NEW met2 ( 121210 18020 ) M2M3_PR_M
- NEW met2 ( 2511830 18020 ) M2M3_PR_M
- NEW met2 ( 2511830 2879460 ) M2M3_PR_M ;
- - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) ( mprj OUT[4] ) + USE SIGNAL
- + ROUTED met3 ( 2499180 1679940 0 ) ( 2506310 * )
- NEW met2 ( 2506310 18190 ) ( * 1679940 )
- NEW met2 ( 144670 2380 0 ) ( * 9180 )
- NEW met2 ( 144210 9180 ) ( 144670 * )
- NEW met2 ( 144210 9180 ) ( * 18530 )
- NEW met1 ( 144210 18530 ) ( 179400 * )
- NEW met1 ( 179400 18190 ) ( * 18530 )
- NEW met1 ( 179400 18190 ) ( 2506310 * )
- NEW met1 ( 2506310 18190 ) M1M2_PR
- NEW met2 ( 2506310 1679940 ) M2M3_PR_M
- NEW met1 ( 144210 18530 ) M1M2_PR ;
- - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) ( mprj OUT[5] ) + USE SIGNAL
- + ROUTED met2 ( 987850 1973530 ) ( * 1979140 )
- NEW met2 ( 162150 2380 0 ) ( * 17850 )
- NEW met1 ( 162150 17850 ) ( 165370 * )
- NEW met2 ( 165370 17850 ) ( * 1973530 )
- NEW met1 ( 165370 1973530 ) ( 987850 * )
- NEW met3 ( 987850 1979140 ) ( 1000500 * 0 )
- NEW met2 ( 987850 1979140 ) M2M3_PR_M
- NEW met1 ( 987850 1973530 ) M1M2_PR
- NEW met1 ( 162150 17850 ) M1M2_PR
- NEW met1 ( 165370 17850 ) M1M2_PR
- NEW met1 ( 165370 1973530 ) M1M2_PR ;
- - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) ( mprj OUT[6] ) + USE SIGNAL
- + ROUTED met2 ( 180090 2380 0 ) ( * 18530 )
- NEW met1 ( 180090 18530 ) ( 185610 * )
- NEW met2 ( 185610 18530 ) ( * 34500 )
- NEW met2 ( 185610 34500 ) ( 186070 * )
- NEW met2 ( 186070 34500 ) ( * 1488350 )
- NEW met2 ( 1324110 1488350 ) ( * 1500420 0 )
- NEW met1 ( 186070 1488350 ) ( 1324110 * )
- NEW met1 ( 180090 18530 ) M1M2_PR
- NEW met1 ( 185610 18530 ) M1M2_PR
- NEW met1 ( 186070 1488350 ) M1M2_PR
- NEW met1 ( 1324110 1488350 ) M1M2_PR ;
- - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) ( mprj OUT[7] ) + USE SIGNAL
- + ROUTED met2 ( 989230 1856230 ) ( * 1859460 )
- NEW met2 ( 198030 2380 0 ) ( * 34500 )
- NEW met2 ( 198030 34500 ) ( 199870 * )
- NEW met2 ( 199870 34500 ) ( * 1856230 )
- NEW met1 ( 199870 1856230 ) ( 989230 * )
- NEW met3 ( 989230 1859460 ) ( 1000500 * 0 )
- NEW met1 ( 199870 1856230 ) M1M2_PR
- NEW met2 ( 989230 1859460 ) M2M3_PR_M
- NEW met1 ( 989230 1856230 ) M1M2_PR ;
- - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) ( mprj OUT[8] ) + USE SIGNAL
- + ROUTED met2 ( 215510 2380 0 ) ( * 16830 )
- NEW met1 ( 215510 16830 ) ( 220570 * )
- NEW met2 ( 986930 1738930 ) ( * 1739780 )
- NEW met2 ( 220570 16830 ) ( * 1738930 )
- NEW met1 ( 220570 1738930 ) ( 986930 * )
- NEW met3 ( 986930 1739780 ) ( 1000500 * 0 )
- NEW met1 ( 215510 16830 ) M1M2_PR
- NEW met1 ( 220570 16830 ) M1M2_PR
- NEW met1 ( 220570 1738930 ) M1M2_PR
- NEW met2 ( 986930 1739780 ) M2M3_PR_M
- NEW met1 ( 986930 1738930 ) M1M2_PR ;
- - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) ( mprj OUT[9] ) + USE SIGNAL
- + ROUTED met3 ( 2499180 1800980 0 ) ( 2505850 * )
- NEW met2 ( 2505850 18530 ) ( * 1800980 )
- NEW met2 ( 233450 2380 0 ) ( * 18530 )
- NEW met1 ( 233450 18530 ) ( 2505850 * )
- NEW met1 ( 2505850 18530 ) M1M2_PR
- NEW met2 ( 2505850 1800980 ) M2M3_PR_M
- NEW met1 ( 233450 18530 ) M1M2_PR ;
- - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) ( mprj init_en ) + USE SIGNAL
- + ROUTED met2 ( 987850 2573970 ) ( * 2578900 )
- NEW met2 ( 55890 2380 0 ) ( * 17850 )
- NEW met1 ( 55890 17850 ) ( 61410 * )
- NEW met2 ( 61410 17850 ) ( * 34500 )
- NEW met2 ( 61410 34500 ) ( 61870 * )
- NEW met2 ( 61870 34500 ) ( * 2573970 )
- NEW met1 ( 61870 2573970 ) ( 987850 * )
- NEW met3 ( 987850 2578900 ) ( 1000500 * 0 )
- NEW met2 ( 987850 2578900 ) M2M3_PR_M
- NEW met1 ( 987850 2573970 ) M1M2_PR
- NEW met1 ( 55890 17850 ) M1M2_PR
- NEW met1 ( 61410 17850 ) M1M2_PR
- NEW met1 ( 61870 2573970 ) M1M2_PR ;
+ - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) + USE SIGNAL ;
+ - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) + USE SIGNAL ;
+ - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) + USE SIGNAL ;
+ - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) + USE SIGNAL ;
+ - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) + USE SIGNAL ;
+ - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) + USE SIGNAL ;
+ - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) + USE SIGNAL ;
+ - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) + USE SIGNAL ;
- wbs_sel_i[1] ( PIN wbs_sel_i[1] ) + USE SIGNAL ;
- wbs_sel_i[2] ( PIN wbs_sel_i[2] ) + USE SIGNAL ;
- wbs_sel_i[3] ( PIN wbs_sel_i[3] ) + USE SIGNAL ;
- wbs_stb_i ( PIN wbs_stb_i ) + USE SIGNAL ;
- wbs_we_i ( PIN wbs_we_i ) + USE SIGNAL ;
- - zero_ ( mem csb0 ) + USE GROUND ;
END NETS
END DESIGN
diff --git a/gds/sram_32_256_sky130A.gds b/gds/sram_32_256_sky130A.gds
deleted file mode 100644
index 17f5412..0000000
--- a/gds/sram_32_256_sky130A.gds
+++ /dev/null
Binary files differ
diff --git a/gds/sram_32_256_sky130A.gds.gz b/gds/sram_32_256_sky130A.gds.gz
new file mode 100644
index 0000000..5ace880
--- /dev/null
+++ b/gds/sram_32_256_sky130A.gds.gz
Binary files differ
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
deleted file mode 100644
index adc6c88..0000000
--- a/gds/user_proj_example.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_proj_example.gds.gz b/gds/user_proj_example.gds.gz
new file mode 100644
index 0000000..41c8686
--- /dev/null
+++ b/gds/user_proj_example.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
deleted file mode 100644
index d7ccd07..0000000
--- a/gds/user_project_wrapper.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..0acc120
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef
index 9fb6c1f..eedd96e 100644
--- a/lef/user_project_wrapper.lef
+++ b/lef/user_project_wrapper.lef
@@ -6789,438 +6789,438 @@
END wbs_we_i
OBS
LAYER li1 ;
- RECT 1005.520 201.705 2494.080 2987.925 ;
+ RECT 1005.520 14.365 2494.080 2987.925 ;
LAYER met1 ;
- RECT 2.830 13.980 2515.210 3011.340 ;
+ RECT 2.830 14.320 2515.210 3010.320 ;
LAYER met2 ;
RECT 2.860 2.680 2515.190 3011.565 ;
- RECT 3.550 2.400 7.950 2.680 ;
- RECT 9.070 2.400 13.930 2.680 ;
- RECT 15.050 2.400 19.910 2.680 ;
- RECT 21.030 2.400 25.890 2.680 ;
- RECT 27.010 2.400 31.870 2.680 ;
- RECT 32.990 2.400 37.850 2.680 ;
- RECT 38.970 2.400 43.370 2.680 ;
- RECT 44.490 2.400 49.350 2.680 ;
- RECT 50.470 2.400 55.330 2.680 ;
- RECT 56.450 2.400 61.310 2.680 ;
- RECT 62.430 2.400 67.290 2.680 ;
- RECT 68.410 2.400 73.270 2.680 ;
- RECT 74.390 2.400 79.250 2.680 ;
- RECT 80.370 2.400 84.770 2.680 ;
- RECT 85.890 2.400 90.750 2.680 ;
- RECT 91.870 2.400 96.730 2.680 ;
- RECT 97.850 2.400 102.710 2.680 ;
- RECT 103.830 2.400 108.690 2.680 ;
- RECT 109.810 2.400 114.670 2.680 ;
- RECT 115.790 2.400 120.650 2.680 ;
- RECT 121.770 2.400 126.170 2.680 ;
- RECT 127.290 2.400 132.150 2.680 ;
- RECT 133.270 2.400 138.130 2.680 ;
- RECT 139.250 2.400 144.110 2.680 ;
- RECT 145.230 2.400 150.090 2.680 ;
- RECT 151.210 2.400 156.070 2.680 ;
- RECT 157.190 2.400 161.590 2.680 ;
- RECT 162.710 2.400 167.570 2.680 ;
- RECT 168.690 2.400 173.550 2.680 ;
- RECT 174.670 2.400 179.530 2.680 ;
- RECT 180.650 2.400 185.510 2.680 ;
- RECT 186.630 2.400 191.490 2.680 ;
- RECT 192.610 2.400 197.470 2.680 ;
- RECT 198.590 2.400 202.990 2.680 ;
- RECT 204.110 2.400 208.970 2.680 ;
- RECT 210.090 2.400 214.950 2.680 ;
- RECT 216.070 2.400 220.930 2.680 ;
- RECT 222.050 2.400 226.910 2.680 ;
- RECT 228.030 2.400 232.890 2.680 ;
- RECT 234.010 2.400 238.870 2.680 ;
- RECT 239.990 2.400 244.390 2.680 ;
- RECT 245.510 2.400 250.370 2.680 ;
- RECT 251.490 2.400 256.350 2.680 ;
- RECT 257.470 2.400 262.330 2.680 ;
- RECT 263.450 2.400 268.310 2.680 ;
- RECT 269.430 2.400 274.290 2.680 ;
- RECT 275.410 2.400 279.810 2.680 ;
- RECT 280.930 2.400 285.790 2.680 ;
- RECT 286.910 2.400 291.770 2.680 ;
- RECT 292.890 2.400 297.750 2.680 ;
- RECT 298.870 2.400 303.730 2.680 ;
- RECT 304.850 2.400 309.710 2.680 ;
- RECT 310.830 2.400 315.690 2.680 ;
- RECT 316.810 2.400 321.210 2.680 ;
- RECT 322.330 2.400 327.190 2.680 ;
- RECT 328.310 2.400 333.170 2.680 ;
- RECT 334.290 2.400 339.150 2.680 ;
- RECT 340.270 2.400 345.130 2.680 ;
- RECT 346.250 2.400 351.110 2.680 ;
- RECT 352.230 2.400 357.090 2.680 ;
- RECT 358.210 2.400 362.610 2.680 ;
- RECT 363.730 2.400 368.590 2.680 ;
- RECT 369.710 2.400 374.570 2.680 ;
- RECT 375.690 2.400 380.550 2.680 ;
- RECT 381.670 2.400 386.530 2.680 ;
- RECT 387.650 2.400 392.510 2.680 ;
- RECT 393.630 2.400 398.030 2.680 ;
- RECT 399.150 2.400 404.010 2.680 ;
- RECT 405.130 2.400 409.990 2.680 ;
- RECT 411.110 2.400 415.970 2.680 ;
- RECT 417.090 2.400 421.950 2.680 ;
- RECT 423.070 2.400 427.930 2.680 ;
- RECT 429.050 2.400 433.910 2.680 ;
- RECT 435.030 2.400 439.430 2.680 ;
- RECT 440.550 2.400 445.410 2.680 ;
- RECT 446.530 2.400 451.390 2.680 ;
- RECT 452.510 2.400 457.370 2.680 ;
- RECT 458.490 2.400 463.350 2.680 ;
- RECT 464.470 2.400 469.330 2.680 ;
- RECT 470.450 2.400 475.310 2.680 ;
- RECT 476.430 2.400 480.830 2.680 ;
- RECT 481.950 2.400 486.810 2.680 ;
- RECT 487.930 2.400 492.790 2.680 ;
- RECT 493.910 2.400 498.770 2.680 ;
- RECT 499.890 2.400 504.750 2.680 ;
- RECT 505.870 2.400 510.730 2.680 ;
- RECT 511.850 2.400 516.250 2.680 ;
- RECT 517.370 2.400 522.230 2.680 ;
- RECT 523.350 2.400 528.210 2.680 ;
- RECT 529.330 2.400 534.190 2.680 ;
- RECT 535.310 2.400 540.170 2.680 ;
- RECT 541.290 2.400 546.150 2.680 ;
- RECT 547.270 2.400 552.130 2.680 ;
- RECT 553.250 2.400 557.650 2.680 ;
- RECT 558.770 2.400 563.630 2.680 ;
- RECT 564.750 2.400 569.610 2.680 ;
- RECT 570.730 2.400 575.590 2.680 ;
- RECT 576.710 2.400 581.570 2.680 ;
- RECT 582.690 2.400 587.550 2.680 ;
- RECT 588.670 2.400 593.530 2.680 ;
- RECT 594.650 2.400 599.050 2.680 ;
- RECT 600.170 2.400 605.030 2.680 ;
- RECT 606.150 2.400 611.010 2.680 ;
- RECT 612.130 2.400 616.990 2.680 ;
- RECT 618.110 2.400 622.970 2.680 ;
- RECT 624.090 2.400 628.950 2.680 ;
- RECT 630.070 2.400 634.470 2.680 ;
- RECT 635.590 2.400 640.450 2.680 ;
- RECT 641.570 2.400 646.430 2.680 ;
- RECT 647.550 2.400 652.410 2.680 ;
- RECT 653.530 2.400 658.390 2.680 ;
- RECT 659.510 2.400 664.370 2.680 ;
- RECT 665.490 2.400 670.350 2.680 ;
- RECT 671.470 2.400 675.870 2.680 ;
- RECT 676.990 2.400 681.850 2.680 ;
- RECT 682.970 2.400 687.830 2.680 ;
- RECT 688.950 2.400 693.810 2.680 ;
- RECT 694.930 2.400 699.790 2.680 ;
- RECT 700.910 2.400 705.770 2.680 ;
- RECT 706.890 2.400 711.750 2.680 ;
- RECT 712.870 2.400 717.270 2.680 ;
- RECT 718.390 2.400 723.250 2.680 ;
- RECT 724.370 2.400 729.230 2.680 ;
- RECT 730.350 2.400 735.210 2.680 ;
- RECT 736.330 2.400 741.190 2.680 ;
- RECT 742.310 2.400 747.170 2.680 ;
- RECT 748.290 2.400 752.690 2.680 ;
- RECT 753.810 2.400 758.670 2.680 ;
- RECT 759.790 2.400 764.650 2.680 ;
- RECT 765.770 2.400 770.630 2.680 ;
- RECT 771.750 2.400 776.610 2.680 ;
- RECT 777.730 2.400 782.590 2.680 ;
- RECT 783.710 2.400 788.570 2.680 ;
- RECT 789.690 2.400 794.090 2.680 ;
- RECT 795.210 2.400 800.070 2.680 ;
- RECT 801.190 2.400 806.050 2.680 ;
- RECT 807.170 2.400 812.030 2.680 ;
- RECT 813.150 2.400 818.010 2.680 ;
- RECT 819.130 2.400 823.990 2.680 ;
- RECT 825.110 2.400 829.970 2.680 ;
- RECT 831.090 2.400 835.490 2.680 ;
- RECT 836.610 2.400 841.470 2.680 ;
- RECT 842.590 2.400 847.450 2.680 ;
- RECT 848.570 2.400 853.430 2.680 ;
- RECT 854.550 2.400 859.410 2.680 ;
- RECT 860.530 2.400 865.390 2.680 ;
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LAYER met3 ;
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LAYER met4 ;
RECT 1002.470 3009.600 1017.170 3011.545 ;
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@@ -7317,47 +7317,74 @@
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END
END user_project_wrapper
END LIBRARY
diff --git a/mag/user_proj_example.mag b/mag/user_proj_example.mag
index 242522c..1a1538d 100644
--- a/mag/user_proj_example.mag
+++ b/mag/user_proj_example.mag
Binary files differ
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index 19828c9..21927e7 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,82 +1,67 @@
magic
tech sky130A
magscale 1 2
-timestamp 1636003697
+timestamp 1636199702
<< locali >>
rect 287069 40511 287103 40817
rect 291853 40579 291887 40817
-rect 297097 40579 297131 40681
-rect 297097 40545 297281 40579
+rect 296729 40579 296763 40681
+rect 296729 40545 296913 40579
rect 299213 40375 299247 41157
rect 304457 40579 304491 41157
+rect 204821 3043 204855 3689
+rect 204913 2907 204947 3009
<< viali >>
rect 299213 41157 299247 41191
rect 287069 40817 287103 40851
rect 291853 40817 291887 40851
rect 291853 40545 291887 40579
-rect 297097 40681 297131 40715
-rect 297281 40545 297315 40579
+rect 296729 40681 296763 40715
+rect 296913 40545 296947 40579
rect 287069 40477 287103 40511
rect 304457 41157 304491 41191
rect 304457 40545 304491 40579
rect 299213 40341 299247 40375
+rect 204821 3689 204855 3723
+rect 204821 3009 204855 3043
+rect 204913 3009 204947 3043
+rect 204913 2873 204947 2907
<< metal1 >>
-rect 8202 602216 8208 602268
-rect 8260 602256 8266 602268
-rect 499942 602256 499948 602268
-rect 8260 602228 499948 602256
-rect 8260 602216 8266 602228
-rect 499942 602216 499948 602228
-rect 500000 602216 500006 602268
-rect 199378 602148 199384 602200
-rect 199436 602188 199442 602200
-rect 224126 602188 224132 602200
-rect 199436 602160 224132 602188
-rect 199436 602148 199442 602160
-rect 224126 602148 224132 602160
-rect 224184 602148 224190 602200
-rect 198918 602080 198924 602132
-rect 198976 602120 198982 602132
-rect 289078 602120 289084 602132
-rect 198976 602092 289084 602120
-rect 198976 602080 198982 602092
-rect 289078 602080 289084 602092
-rect 289136 602080 289142 602132
-rect 199102 602012 199108 602064
-rect 199160 602052 199166 602064
-rect 321462 602052 321468 602064
-rect 199160 602024 321468 602052
-rect 199160 602012 199166 602024
-rect 321462 602012 321468 602024
-rect 321520 602012 321526 602064
-rect 199010 601944 199016 601996
-rect 199068 601984 199074 601996
-rect 467558 601984 467564 601996
-rect 199068 601956 467564 601984
-rect 199068 601944 199074 601956
-rect 467558 601944 467564 601956
-rect 467616 601944 467622 601996
-rect 198826 601876 198832 601928
-rect 198884 601916 198890 601928
-rect 483750 601916 483756 601928
-rect 198884 601888 483756 601916
-rect 198884 601876 198890 601888
-rect 483750 601876 483756 601888
-rect 483808 601876 483814 601928
-rect 27522 601808 27528 601860
-rect 27580 601848 27586 601860
-rect 337838 601848 337844 601860
-rect 27580 601820 337844 601848
-rect 27580 601808 27586 601820
-rect 337838 601808 337844 601820
-rect 337896 601808 337902 601860
-rect 15102 601740 15108 601792
-rect 15160 601780 15166 601792
-rect 435174 601780 435180 601792
-rect 15160 601752 435180 601780
-rect 15160 601740 15166 601752
-rect 435174 601740 435180 601752
-rect 435232 601740 435238 601792
+rect 198826 602012 198832 602064
+rect 198884 602052 198890 602064
+rect 483750 602052 483756 602064
+rect 198884 602024 483756 602052
+rect 198884 602012 198890 602024
+rect 483750 602012 483756 602024
+rect 483808 602012 483814 602064
+rect 198734 601944 198740 601996
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+rect 224126 601984 224132 601996
+rect 198792 601956 224132 601984
+rect 198792 601944 198798 601956
+rect 224126 601944 224132 601956
+rect 224184 601944 224190 601996
+rect 198918 601876 198924 601928
+rect 198976 601916 198982 601928
+rect 289078 601916 289084 601928
+rect 198976 601888 289084 601916
+rect 198976 601876 198982 601888
+rect 289078 601876 289084 601888
+rect 289136 601876 289142 601928
+rect 199102 601808 199108 601860
+rect 199160 601848 199166 601860
+rect 321462 601848 321468 601860
+rect 199160 601820 321468 601848
+rect 199160 601808 199166 601820
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+rect 321520 601808 321526 601860
+rect 199010 601740 199016 601792
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+rect 467558 601780 467564 601792
+rect 199068 601752 467564 601780
+rect 199068 601740 199074 601752
+rect 467558 601740 467564 601752
+rect 467616 601740 467622 601792
rect 199930 601672 199936 601724
rect 199988 601712 199994 601724
rect 207934 601712 207940 601724
@@ -84,207 +69,176 @@
rect 199988 601672 199994 601684
rect 207934 601672 207940 601684
rect 207992 601672 207998 601724
-rect 12342 514768 12348 514820
-rect 12400 514808 12406 514820
-rect 197538 514808 197544 514820
-rect 12400 514780 197544 514808
-rect 12400 514768 12406 514780
-rect 197538 514768 197544 514780
-rect 197596 514768 197602 514820
-rect 33042 394680 33048 394732
-rect 33100 394720 33106 394732
-rect 197538 394720 197544 394732
-rect 33100 394692 197544 394720
-rect 33100 394680 33106 394692
-rect 197538 394680 197544 394692
-rect 197596 394680 197602 394732
-rect 39942 371220 39948 371272
-rect 40000 371260 40006 371272
-rect 197814 371260 197820 371272
-rect 40000 371232 197820 371260
-rect 40000 371220 40006 371232
-rect 197814 371220 197820 371232
-rect 197872 371220 197878 371272
-rect 44082 347760 44088 347812
-rect 44140 347800 44146 347812
-rect 197354 347800 197360 347812
-rect 44140 347772 197360 347800
-rect 44140 347760 44146 347772
-rect 197354 347760 197360 347772
-rect 197412 347760 197418 347812
rect 313550 298052 313556 298104
rect 313608 298092 313614 298104
-rect 314654 298092 314660 298104
-rect 313608 298064 314660 298092
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rect 313608 298052 313614 298064
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-rect 314712 298052 314718 298104
-rect 201402 297848 201408 297900
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-rect 216214 297848 216220 297860
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-rect 200172 297780 200178 297792
-rect 362126 297780 362132 297792
-rect 362184 297780 362190 297832
-rect 34422 297712 34428 297764
-rect 34480 297752 34486 297764
-rect 232406 297752 232412 297764
-rect 34480 297724 232412 297752
-rect 34480 297712 34486 297724
-rect 232406 297712 232412 297724
-rect 232464 297712 232470 297764
-rect 37182 297644 37188 297696
-rect 37240 297684 37246 297696
-rect 264790 297684 264796 297696
-rect 37240 297656 264796 297684
-rect 37240 297644 37246 297656
-rect 264790 297644 264796 297656
-rect 264848 297644 264854 297696
-rect 37090 297576 37096 297628
-rect 37148 297616 37154 297628
-rect 280982 297616 280988 297628
-rect 37148 297588 280988 297616
-rect 37148 297576 37154 297588
-rect 280982 297576 280988 297588
-rect 281040 297576 281046 297628
-rect 12250 297508 12256 297560
-rect 12308 297548 12314 297560
-rect 297358 297548 297364 297560
-rect 12308 297520 297364 297548
-rect 12308 297508 12314 297520
-rect 297358 297508 297364 297520
-rect 297416 297508 297422 297560
-rect 320818 297508 320824 297560
-rect 320876 297548 320882 297560
-rect 329742 297548 329748 297560
-rect 320876 297520 329748 297548
-rect 320876 297508 320882 297520
-rect 329742 297508 329748 297520
-rect 329800 297508 329806 297560
-rect 22002 297440 22008 297492
-rect 22060 297480 22066 297492
-rect 443270 297480 443276 297492
-rect 22060 297452 443276 297480
-rect 22060 297440 22066 297452
-rect 443270 297440 443276 297452
-rect 443328 297440 443334 297492
-rect 20622 297372 20628 297424
-rect 20680 297412 20686 297424
-rect 492030 297412 492036 297424
-rect 20680 297384 492036 297412
-rect 20680 297372 20686 297384
-rect 492030 297372 492036 297384
-rect 492088 297372 492094 297424
-rect 282178 284248 282184 284300
-rect 282236 284288 282242 284300
-rect 287698 284288 287704 284300
-rect 282236 284260 287704 284288
-rect 282236 284248 282242 284260
-rect 287698 284248 287704 284260
-rect 287756 284248 287762 284300
-rect 287698 242836 287704 242888
-rect 287756 242876 287762 242888
-rect 293218 242876 293224 242888
-rect 287756 242848 293224 242876
-rect 287756 242836 287762 242848
-rect 293218 242836 293224 242848
-rect 293276 242836 293282 242888
-rect 293218 238008 293224 238060
-rect 293276 238048 293282 238060
-rect 305638 238048 305644 238060
-rect 293276 238020 305644 238048
-rect 293276 238008 293282 238020
-rect 305638 238008 305644 238020
-rect 305696 238008 305702 238060
-rect 305638 215228 305644 215280
-rect 305696 215268 305702 215280
-rect 308766 215268 308772 215280
-rect 305696 215240 308772 215268
-rect 305696 215228 305702 215240
-rect 308766 215228 308772 215240
-rect 308824 215228 308830 215280
-rect 308766 212440 308772 212492
-rect 308824 212480 308830 212492
-rect 311342 212480 311348 212492
-rect 308824 212452 311348 212480
-rect 308824 212440 308830 212452
-rect 311342 212440 311348 212452
-rect 311400 212440 311406 212492
-rect 311342 208360 311348 208412
-rect 311400 208400 311406 208412
-rect 314010 208400 314016 208412
-rect 311400 208372 314016 208400
-rect 311400 208360 311406 208372
-rect 314010 208360 314016 208372
-rect 314068 208360 314074 208412
-rect 220078 170348 220084 170400
-rect 220136 170388 220142 170400
-rect 248414 170388 248420 170400
-rect 220136 170360 248420 170388
-rect 220136 170348 220142 170360
-rect 248414 170348 248420 170360
-rect 248472 170348 248478 170400
-rect 218054 158040 218060 158092
-rect 218112 158080 218118 158092
-rect 220078 158080 220084 158092
-rect 218112 158052 220084 158080
-rect 218112 158040 218118 158052
-rect 220078 158040 220084 158052
-rect 220136 158040 220142 158092
-rect 216674 154232 216680 154284
-rect 216732 154272 216738 154284
-rect 218054 154272 218060 154284
-rect 216732 154244 218060 154272
-rect 216732 154232 216738 154244
-rect 218054 154232 218060 154244
-rect 218112 154232 218118 154284
-rect 214558 145596 214564 145648
-rect 214616 145636 214622 145648
-rect 216674 145636 216680 145648
-rect 214616 145608 216680 145636
-rect 214616 145596 214622 145608
-rect 216674 145596 216680 145608
-rect 216732 145596 216738 145648
-rect 213362 124108 213368 124160
-rect 213420 124148 213426 124160
-rect 214558 124148 214564 124160
-rect 213420 124120 214564 124148
-rect 213420 124108 213426 124120
-rect 214558 124108 214564 124120
-rect 214616 124108 214622 124160
-rect 210510 116152 210516 116204
-rect 210568 116192 210574 116204
-rect 213362 116192 213368 116204
-rect 210568 116164 213368 116192
-rect 210568 116152 210574 116164
-rect 213362 116152 213368 116164
-rect 213420 116152 213426 116204
-rect 201310 115200 201316 115252
-rect 201368 115240 201374 115252
-rect 210510 115240 210516 115252
-rect 201368 115212 210516 115240
-rect 201368 115200 201374 115212
-rect 210510 115200 210516 115212
-rect 210568 115200 210574 115252
-rect 315298 68280 315304 68332
-rect 315356 68320 315362 68332
+rect 314930 298052 314936 298064
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+rect 297358 297644 297364 297696
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+rect 349798 297576 349804 297628
+rect 349856 297616 349862 297628
+rect 443270 297616 443276 297628
+rect 349856 297588 443276 297616
+rect 349856 297576 349862 297588
+rect 443270 297576 443276 297588
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+rect 371878 297548 371884 297560
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-rect 314654 50940 314660 50992
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rect 201310 42712 201316 42764
@@ -294,13 +248,13 @@
rect 201368 42712 201374 42724
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-rect 272978 41352 272984 41404
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@@ -328,18 +282,18 @@
rect 314068 41012 314074 41064
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@@ -379,29 +333,29 @@
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-rect 297232 40672 297238 40684
-rect 315942 40672 315948 40684
-rect 316000 40672 316006 40724
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@@ -409,13 +363,6 @@
rect 199988 40604 199994 40616
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@@ -423,13 +370,13 @@
rect 278372 40604 278378 40616
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@@ -438,9 +385,9 @@
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@@ -452,15 +399,15 @@
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rect 304350 40536 304356 40548
rect 304408 40536 304414 40588
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@@ -482,11 +429,11 @@
rect 293920 40468 293926 40480
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@@ -496,11 +443,11 @@
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@@ -514,25 +461,25 @@
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@@ -542,295 +489,385 @@
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<< metal2 >>
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@@ -1963,25 +1881,25 @@
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+rect 316684 40928 316736 40934
+rect 316684 40870 316736 40876
+rect 315580 40724 315632 40730
+rect 315580 40666 315632 40672
+rect 315592 40089 315620 40666
+rect 315578 40080 315634 40089
+rect 315578 40015 315634 40024
+rect 320836 39982 320864 297434
rect 345032 41138 345060 300070
-rect 362144 297838 362172 300084
-rect 378152 300070 378534 300098
-rect 362132 297832 362184 297838
-rect 362132 297774 362184 297780
+rect 349804 297628 349856 297634
+rect 349804 297570 349856 297576
rect 345020 41132 345072 41138
rect 345020 41074 345072 41080
-rect 378152 40866 378180 300070
-rect 394712 68338 394740 300084
-rect 409892 300070 410918 300098
-rect 426452 300070 427110 300098
-rect 394700 68332 394752 68338
-rect 394700 68274 394752 68280
-rect 378140 40860 378192 40866
-rect 378140 40802 378192 40808
-rect 409892 40662 409920 300070
-rect 409880 40656 409932 40662
-rect 409880 40598 409932 40604
-rect 426452 40594 426480 300070
-rect 443288 297498 443316 300084
-rect 459572 300070 459678 300098
-rect 474752 300070 475870 300098
-rect 443276 297492 443328 297498
-rect 443276 297434 443328 297440
-rect 426440 40588 426492 40594
-rect 426440 40530 426492 40536
-rect 459572 40458 459600 300070
-rect 474752 40526 474780 300070
-rect 492048 297430 492076 300084
-rect 492036 297424 492088 297430
-rect 492036 297366 492088 297372
-rect 474740 40520 474792 40526
-rect 474740 40462 474792 40468
-rect 459560 40452 459612 40458
-rect 459560 40394 459612 40400
-rect 500972 40118 501000 551919
-rect 501050 432032 501106 432041
-rect 501050 431967 501106 431976
-rect 501064 40254 501092 431967
-rect 501142 360224 501198 360233
-rect 501142 360159 501198 360168
-rect 501052 40248 501104 40254
-rect 501052 40190 501104 40196
-rect 500960 40112 501012 40118
-rect 500960 40054 501012 40060
-rect 320824 39840 320876 39846
-rect 307022 39808 307078 39817
-rect 320824 39782 320876 39788
-rect 307022 39743 307024 39752
-rect 307076 39743 307078 39752
-rect 307024 39714 307076 39720
-rect 299532 39672 299534 39681
-rect 299478 39607 299534 39616
-rect 301778 39672 301834 39681
-rect 301778 39607 301834 39616
-rect 304354 39672 304410 39681
-rect 304354 39607 304410 39616
-rect 296812 39578 296864 39584
-rect 293960 39510 294012 39516
-rect 296074 39536 296130 39545
-rect 291568 39500 291620 39506
-rect 296074 39471 296130 39480
-rect 291568 39442 291620 39448
-rect 288440 39432 288492 39438
-rect 282918 39400 282974 39409
-rect 282918 39335 282974 39344
-rect 285678 39400 285734 39409
-rect 288440 39374 288492 39380
-rect 285678 39335 285680 39344
-rect 282932 39302 282960 39335
-rect 285732 39335 285734 39344
-rect 285680 39306 285732 39312
-rect 282920 39296 282972 39302
-rect 280158 39264 280214 39273
-rect 278504 39228 278556 39234
-rect 282920 39238 282972 39244
-rect 280158 39199 280214 39208
-rect 278504 39170 278556 39176
-rect 280172 39166 280200 39199
-rect 280160 39160 280212 39166
-rect 276018 39128 276074 39137
-rect 273352 39092 273404 39098
-rect 280160 39102 280212 39108
-rect 276018 39063 276074 39072
-rect 273352 39034 273404 39040
-rect 276032 39030 276060 39063
-rect 276020 39024 276072 39030
-rect 276020 38966 276072 38972
-rect 302238 38720 302294 38729
-rect 302238 38655 302294 38664
-rect 303618 38720 303674 38729
-rect 303618 38655 303674 38664
-rect 270500 2984 270552 2990
-rect 270500 2926 270552 2932
-rect 302252 2922 302280 38655
-rect 302240 2916 302292 2922
-rect 302240 2858 302292 2864
-rect 303632 2854 303660 38655
-rect 501156 3738 501184 360159
-rect 501234 336016 501290 336025
-rect 501234 335951 501290 335960
-rect 501144 3732 501196 3738
-rect 501144 3674 501196 3680
-rect 501248 3670 501276 335951
-rect 501236 3664 501288 3670
-rect 502352 3641 502380 575855
-rect 502522 528048 502578 528057
-rect 502522 527983 502578 527992
-rect 502430 504112 502486 504121
-rect 502430 504047 502486 504056
-rect 501236 3606 501288 3612
-rect 502338 3632 502394 3641
-rect 502338 3567 502394 3576
-rect 502444 3505 502472 504047
-rect 502536 40186 502564 527983
-rect 502706 480176 502762 480185
-rect 502706 480111 502762 480120
-rect 502614 455968 502670 455977
-rect 502614 455903 502670 455912
-rect 502524 40180 502576 40186
-rect 502524 40122 502576 40128
-rect 502430 3496 502486 3505
-rect 502430 3431 502486 3440
-rect 502628 3369 502656 455903
-rect 502720 40322 502748 480111
-rect 502798 408096 502854 408105
-rect 502798 408031 502854 408040
-rect 502708 40316 502760 40322
-rect 502708 40258 502760 40264
-rect 502812 3534 502840 408031
-rect 502890 384160 502946 384169
-rect 502890 384095 502946 384104
-rect 502904 3602 502932 384095
-rect 502982 312080 503038 312089
-rect 502982 312015 503038 312024
-rect 502996 40390 503024 312015
-rect 502984 40384 503036 40390
-rect 502984 40326 503036 40332
-rect 502892 3596 502944 3602
-rect 502892 3538 502944 3544
-rect 502800 3528 502852 3534
-rect 502800 3470 502852 3476
-rect 502614 3360 502670 3369
-rect 502614 3295 502670 3304
-rect 303620 2848 303672 2854
-rect 303620 2790 303672 2796
+rect 320824 39976 320876 39982
+rect 320824 39918 320876 39924
+rect 315210 39536 315266 39545
+rect 315210 39471 315266 39480
+rect 314844 4072 314896 4078
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+rect 314752 4004 314804 4010
+rect 314752 3946 314804 3952
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+rect 361488 297492 361540 297498
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+rect 349804 3936 349856 3942
+rect 349804 3878 349856 3884
+rect 354036 3936 354088 3942
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+rect 306748 3324 306800 3330
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+rect 314660 3324 314712 3330
+rect 314660 3266 314712 3272
+rect 306760 480 306788 3266
+rect 354048 480 354076 3878
+rect 357530 3360 357586 3369
+rect 357530 3295 357586 3304
+rect 357544 480 357572 3295
+rect 361132 598 361344 626
+rect 361132 480 361160 598
+rect 361316 490 361344 598
+rect 361500 490 361528 297434
+rect 362144 297430 362172 300084
+rect 378152 300070 378534 300098
+rect 371884 297560 371936 297566
+rect 371884 297502 371936 297508
+rect 362132 297424 362184 297430
+rect 362132 297366 362184 297372
+rect 368204 4072 368256 4078
+rect 368204 4014 368256 4020
+rect 364616 4004 364668 4010
+rect 364616 3946 364668 3952
rect 542 -960 654 480
rect 1646 -960 1758 480
rect 2842 -960 2954 480
@@ -2671,6 +2556,118 @@
rect 358698 -960 358810 480
rect 359894 -960 360006 480
rect 361090 -960 361202 480
+rect 361316 462 361528 490
+rect 364628 480 364656 3946
+rect 368216 480 368244 4014
+rect 371700 3868 371752 3874
+rect 371700 3810 371752 3816
+rect 371712 480 371740 3810
+rect 371896 3398 371924 297502
+rect 378152 40866 378180 300070
+rect 394712 68338 394740 300084
+rect 409892 300070 410918 300098
+rect 426452 300070 427110 300098
+rect 394700 68332 394752 68338
+rect 394700 68274 394752 68280
+rect 378140 40860 378192 40866
+rect 378140 40802 378192 40808
+rect 409892 40662 409920 300070
+rect 409880 40656 409932 40662
+rect 409880 40598 409932 40604
+rect 426452 40594 426480 300070
+rect 443288 297634 443316 300084
+rect 459572 300070 459678 300098
+rect 474752 300070 475870 300098
+rect 443276 297628 443328 297634
+rect 443276 297570 443328 297576
+rect 426440 40588 426492 40594
+rect 426440 40530 426492 40536
+rect 459572 40458 459600 300070
+rect 474752 40526 474780 300070
+rect 492048 297498 492076 300084
+rect 492036 297492 492088 297498
+rect 492036 297434 492088 297440
+rect 474740 40520 474792 40526
+rect 474740 40462 474792 40468
+rect 459560 40452 459612 40458
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+rect 378876 3800 378928 3806
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+rect 371884 3392 371936 3398
+rect 371884 3334 371936 3340
+rect 375288 3392 375340 3398
+rect 375288 3334 375340 3340
+rect 375300 480 375328 3334
+rect 378888 480 378916 3742
+rect 382372 3732 382424 3738
+rect 382372 3674 382424 3680
+rect 385960 3732 386012 3738
+rect 385960 3674 386012 3680
+rect 382384 480 382412 3674
+rect 385972 480 386000 3674
+rect 500052 3534 500080 599270
+rect 500958 575920 501014 575929
+rect 500958 575855 501014 575864
+rect 500972 4010 501000 575855
+rect 501050 551984 501106 551993
+rect 501050 551919 501106 551928
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+rect 502430 527983 502486 527992
+rect 502338 504112 502394 504121
+rect 502338 504047 502394 504056
+rect 501142 336016 501198 336025
+rect 501142 335951 501198 335960
+rect 501052 40112 501104 40118
+rect 501052 40054 501104 40060
+rect 501156 4078 501184 335951
+rect 501234 312080 501290 312089
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+rect 501248 40390 501276 312015
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+rect 501236 40326 501288 40332
+rect 501144 4072 501196 4078
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+rect 500960 4004 501012 4010
+rect 500960 3946 501012 3952
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+rect 502614 480176 502670 480185
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+rect 502522 455968 502578 455977
+rect 502522 455903 502578 455912
+rect 502432 40180 502484 40186
+rect 502432 40122 502484 40128
+rect 502536 3942 502564 455903
+rect 502628 40322 502656 480111
+rect 502798 432032 502854 432041
+rect 502798 431967 502854 431976
+rect 502706 408096 502762 408105
+rect 502706 408031 502762 408040
+rect 502616 40316 502668 40322
+rect 502616 40258 502668 40264
+rect 502524 3936 502576 3942
+rect 502524 3878 502576 3884
+rect 502340 3596 502392 3602
+rect 502340 3538 502392 3544
+rect 500040 3528 500092 3534
+rect 500040 3470 500092 3476
+rect 502720 3466 502748 408031
+rect 502812 40254 502840 431967
+rect 502890 384160 502946 384169
+rect 502890 384095 502946 384104
+rect 502800 40248 502852 40254
+rect 502800 40190 502852 40196
+rect 502904 3670 502932 384095
+rect 502982 360224 503038 360233
+rect 502982 360159 503038 360168
+rect 502996 3738 503024 360159
+rect 502984 3732 503036 3738
+rect 502984 3674 503036 3680
+rect 502892 3664 502944 3670
+rect 502892 3606 502944 3612
+rect 502708 3460 502760 3466
+rect 502708 3402 502760 3408
rect 362286 -960 362398 480
rect 363482 -960 363594 480
rect 364586 -960 364698 480
@@ -2860,45 +2857,45 @@
rect 582166 -960 582278 480
rect 583362 -960 583474 480
<< via2 >>
-rect 354034 602248 354090 602304
-rect 9954 3304 10010 3360
-rect 17038 3440 17094 3496
-rect 24214 3576 24270 3632
+rect 402610 602248 402666 602304
+rect 354034 602112 354090 602168
rect 198646 587832 198702 587888
-rect 198554 563896 198610 563952
-rect 197542 515752 197598 515808
-rect 198462 491816 198518 491872
-rect 198370 467880 198426 467936
-rect 198278 419736 198334 419792
-rect 197542 395800 197598 395856
-rect 197818 371864 197874 371920
-rect 197358 347928 197414 347984
-rect 198186 323992 198242 324048
-rect 198278 70896 198334 70952
+rect 198554 491816 198610 491872
+rect 198462 467880 198518 467936
+rect 198186 419736 198242 419792
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+rect 198002 323992 198058 324048
+rect 198370 395800 198426 395856
+rect 198278 371864 198334 371920
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-rect 199198 539688 199254 539744
+rect 199198 563896 199254 563952
rect 199106 68856 199162 68912
rect 199014 67496 199070 67552
rect 198830 66816 198886 66872
-rect 199290 443944 199346 444000
-rect 199382 45056 199438 45112
+rect 198738 45056 198794 45112
+rect 198738 43560 198794 43616
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+rect 199290 515752 199346 515808
+rect 199474 443944 199530 444000
rect 256698 601704 256754 601760
-rect 370226 602112 370282 602168
-rect 386418 601976 386474 602032
-rect 402610 601840 402666 601896
+rect 272890 601704 272946 601760
+rect 337842 601704 337898 601760
+rect 370226 601976 370282 602032
+rect 386418 601840 386474 601896
+rect 435178 601840 435234 601896
rect 418986 601704 419042 601760
rect 240598 599256 240654 599312
-rect 273166 599256 273222 599312
rect 305550 599256 305606 599312
rect 451278 599256 451334 599312
-rect 502338 575864 502394 575920
-rect 500958 551928 501014 551984
rect 200118 69808 200174 69864
-rect 282182 291760 282238 291816
+rect 290462 284824 290518 284880
rect 243082 110472 243138 110528
rect 243082 109792 243138 109848
rect 267646 41384 267702 41440
-rect 267830 41384 267886 41440
+rect 277306 41384 277362 41440
+rect 289726 41384 289782 41440
+rect 306562 41384 306618 41440
rect 237286 40704 237342 40760
rect 228638 40060 228640 40080
rect 228640 40060 228692 40080
@@ -2910,120 +2907,123 @@
rect 238666 40024 238722 40080
rect 241426 40024 241482 40080
rect 245658 40024 245714 40080
-rect 224958 39752 225014 39808
-rect 230478 39752 230534 39808
-rect 220818 39616 220874 39672
-rect 224866 39616 224922 39672
+rect 248694 40024 248750 40080
rect 207018 38528 207074 38584
+rect 225050 39752 225106 39808
+rect 230478 39752 230534 39808
+rect 239034 39772 239090 39808
+rect 239034 39752 239036 39772
+rect 239036 39752 239088 39772
+rect 239088 39752 239090 39772
+rect 224866 39616 224922 39672
+rect 220818 38800 220874 38856
+rect 241518 39752 241574 39808
+rect 247038 39752 247094 39808
rect 249798 39752 249854 39808
-rect 241518 39616 241574 39672
-rect 248970 39616 249026 39672
-rect 247038 38956 247094 38992
-rect 247038 38936 247040 38956
-rect 247040 38936 247092 38956
-rect 247092 38936 247094 38956
-rect 235998 38820 236054 38856
-rect 235998 38800 236000 38820
-rect 236000 38800 236052 38820
-rect 236052 38800 236054 38820
+rect 233238 39652 233240 39672
+rect 233240 39652 233292 39672
+rect 233292 39652 233294 39672
+rect 233238 39616 233294 39652
rect 227718 38684 227774 38720
rect 227718 38664 227720 38684
rect 227720 38664 227772 38684
rect 227772 38664 227774 38684
-rect 233238 38664 233294 38720
-rect 238758 38664 238814 38720
-rect 244278 38664 244334 38720
+rect 235998 38956 236054 38992
+rect 235998 38936 236000 38956
+rect 236000 38936 236052 38956
+rect 236052 38936 236054 38956
rect 254490 39888 254546 39944
rect 252558 39752 252614 39808
rect 253938 39752 253994 39808
rect 256698 39752 256754 39808
rect 251822 39616 251878 39672
+rect 244278 38684 244334 38720
+rect 244278 38664 244280 38684
+rect 244280 38664 244332 38684
+rect 244332 38664 244334 38684
rect 259458 39752 259514 39808
rect 256882 39616 256938 39672
rect 263598 40704 263654 40760
rect 263874 40704 263930 40760
-rect 267554 40704 267610 40760
rect 262494 39888 262550 39944
-rect 306562 41384 306618 41440
-rect 267830 40704 267886 40760
-rect 272982 40704 273038 40760
-rect 273166 40704 273222 40760
rect 273350 40024 273406 40080
-rect 282734 40024 282790 40080
+rect 273902 39888 273958 39944
rect 262218 39752 262274 39808
rect 264886 39752 264942 39808
rect 267646 39752 267702 39808
rect 270222 39752 270278 39808
rect 270498 39752 270554 39808
-rect 273350 39752 273406 39808
-rect 275466 39752 275522 39808
-rect 278318 39752 278374 39808
-rect 278502 39752 278558 39808
-rect 280618 39752 280674 39808
-rect 281446 39752 281502 39808
+rect 273258 39752 273314 39808
rect 259550 39616 259606 39672
rect 264978 38664 265034 38720
rect 267738 38664 267794 38720
-rect 288438 39752 288494 39808
+rect 275466 39752 275522 39808
+rect 273902 39616 273958 39672
+rect 282734 40024 282790 40080
+rect 278318 39752 278374 39808
+rect 278502 39752 278558 39808
+rect 280618 39752 280674 39808
+rect 280802 39752 280858 39808
+rect 277306 39480 277362 39536
+rect 306378 40704 306434 40760
+rect 306562 40704 306618 40760
+rect 306654 40024 306710 40080
+rect 307022 39752 307078 39808
+rect 307206 39752 307262 39808
rect 283654 39616 283710 39672
rect 286230 39616 286286 39672
-rect 296074 39888 296130 39944
-rect 293866 39752 293922 39808
+rect 288806 39616 288862 39672
rect 291382 39616 291438 39672
-rect 291566 39616 291622 39672
-rect 293958 39616 294014 39672
-rect 314934 110336 314990 110392
-rect 314842 109928 314898 109984
-rect 315302 46824 315358 46880
+rect 293866 39616 293922 39672
+rect 294050 39616 294106 39672
rect 296534 39616 296590 39672
-rect 296810 39636 296866 39672
-rect 296810 39616 296812 39636
-rect 296812 39616 296864 39636
-rect 296864 39616 296866 39636
rect 299294 39616 299350 39672
-rect 306378 40704 306434 40760
-rect 306378 40044 306434 40080
-rect 306378 40024 306380 40044
-rect 306380 40024 306432 40044
-rect 306432 40024 306434 40044
-rect 306562 40704 306618 40760
-rect 315762 40704 315818 40760
-rect 306654 40024 306710 40080
-rect 307390 40024 307446 40080
-rect 315946 40024 316002 40080
-rect 501050 431976 501106 432032
-rect 501142 360168 501198 360224
-rect 307022 39772 307078 39808
-rect 307022 39752 307024 39772
-rect 307024 39752 307076 39772
-rect 307076 39752 307078 39772
-rect 299478 39652 299480 39672
-rect 299480 39652 299532 39672
-rect 299532 39652 299534 39672
-rect 299478 39616 299534 39652
rect 301778 39616 301834 39672
rect 304354 39616 304410 39672
-rect 296074 39480 296130 39536
-rect 282918 39344 282974 39400
-rect 285678 39364 285734 39400
-rect 285678 39344 285680 39364
-rect 285680 39344 285732 39364
-rect 285732 39344 285734 39364
-rect 280158 39208 280214 39264
-rect 276018 39072 276074 39128
-rect 302238 38664 302294 38720
-rect 303618 38664 303674 38720
-rect 501234 335960 501290 336016
-rect 502522 527992 502578 528048
-rect 502430 504056 502486 504112
-rect 502338 3576 502394 3632
-rect 502706 480120 502762 480176
-rect 502614 455912 502670 455968
-rect 502430 3440 502486 3496
-rect 502798 408040 502854 408096
+rect 285678 39480 285734 39536
+rect 296810 39480 296866 39536
+rect 299478 39500 299534 39536
+rect 299478 39480 299480 39500
+rect 299480 39480 299532 39500
+rect 299532 39480 299534 39500
+rect 282918 39364 282974 39400
+rect 282918 39344 282920 39364
+rect 282920 39344 282972 39364
+rect 282972 39344 282974 39364
+rect 276018 39228 276074 39264
+rect 276018 39208 276020 39228
+rect 276020 39208 276072 39228
+rect 276072 39208 276074 39228
+rect 288438 39208 288494 39264
+rect 303618 39208 303674 39264
+rect 302238 39092 302294 39128
+rect 302238 39072 302240 39092
+rect 302240 39072 302292 39092
+rect 302292 39072 302294 39092
+rect 291198 38820 291254 38856
+rect 291198 38800 291200 38820
+rect 291200 38800 291252 38820
+rect 291252 38800 291254 38820
+rect 296074 3304 296130 3360
+rect 315026 110336 315082 110392
+rect 315210 109792 315266 109848
+rect 315302 46824 315358 46880
+rect 315210 41112 315266 41168
+rect 315578 40024 315634 40080
+rect 315210 39480 315266 39536
+rect 357530 3304 357586 3360
+rect 500958 575864 501014 575920
+rect 501050 551928 501106 551984
+rect 502430 527992 502486 528048
+rect 502338 504056 502394 504112
+rect 501142 335960 501198 336016
+rect 501234 312024 501290 312080
+rect 502614 480120 502670 480176
+rect 502522 455912 502578 455968
+rect 502798 431976 502854 432032
+rect 502706 408040 502762 408096
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-rect 502982 312024 503038 312080
-rect 502614 3304 502670 3360
+rect 502982 360168 503038 360224
<< metal3 >>
rect -960 697220 480 697460
rect 583520 697084 584960 697324
@@ -3043,40 +3043,49 @@
rect 583520 604060 584960 604300
rect 318006 602244 318012 602308
rect 318076 602306 318082 602308
-rect 354029 602306 354095 602309
-rect 318076 602304 354095 602306
-rect 318076 602248 354034 602304
-rect 354090 602248 354095 602304
-rect 318076 602246 354095 602248
+rect 402605 602306 402671 602309
+rect 318076 602304 402671 602306
+rect 318076 602248 402610 602304
+rect 402666 602248 402671 602304
+rect 318076 602246 402671 602248
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-rect 354029 602243 354095 602246
-rect 316534 602108 316540 602172
-rect 316604 602170 316610 602172
-rect 370221 602170 370287 602173
-rect 316604 602168 370287 602170
-rect 316604 602112 370226 602168
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-rect 319732 601896 402671 601898
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@@ -3086,15 +3095,33 @@
rect 200868 601702 256759 601704
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-rect 313958 601700 313964 601764
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@@ -3104,15 +3131,6 @@
rect 240593 599251 240659 599254
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-rect 273161 599314 273227 599317
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@@ -3141,129 +3159,129 @@
rect 198641 587827 198707 587830
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-rect 502333 575922 502399 575925
-rect 499836 575920 502399 575922
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-rect 499836 575862 502399 575864
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-rect 198549 563954 198615 563957
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rect -960 540684 480 540924
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rect -960 527764 480 528004
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-rect 501106 431976 501111 432032
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-rect 499836 408038 502859 408040
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@@ -3273,65 +3291,65 @@
rect 499836 384102 502951 384104
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-rect 275134 291756 275140 291820
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@@ -3372,36 +3390,34 @@
rect 306300 110530 306306 110532
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-rect 198273 70954 198339 70957
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@@ -3447,33 +3463,39 @@
rect 315254 46702 315314 46819
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-rect 267702 41384 267830 41440
-rect 267886 41384 267891 41440
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-rect 272760 41380 272766 41444
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-rect 272830 41440 306623 41442
-rect 272830 41384 306562 41440
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-rect 272830 41382 306623 41384
-rect 272830 41380 272836 41382
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-rect 318006 41034 318012 41036
-rect 314886 40974 318012 41034
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@@ -3484,43 +3506,39 @@
rect 237281 40699 237347 40702
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-rect 267549 40762 267615 40765
-rect 263869 40760 267615 40762
-rect 263869 40704 263874 40760
-rect 263930 40704 267554 40760
-rect 267610 40704 267615 40760
-rect 263869 40702 267615 40704
-rect 263869 40699 263935 40702
-rect 267549 40699 267615 40702
-rect 267825 40762 267891 40765
-rect 272977 40762 273043 40765
-rect 267825 40760 273043 40762
-rect 267825 40704 267830 40760
-rect 267886 40704 272982 40760
-rect 273038 40704 273043 40760
-rect 267825 40702 273043 40704
-rect 267825 40699 267891 40702
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-rect 273161 40762 273227 40765
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-rect 273161 40760 306439 40762
-rect 273161 40704 273166 40760
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@@ -3587,18 +3605,27 @@
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@@ -3616,68 +3643,45 @@
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@@ -3689,6 +3693,33 @@
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@@ -3775,21 +3806,78 @@
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@@ -3816,100 +3904,32 @@
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@@ -3922,74 +3942,61 @@
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-rect 285673 39342 286548 39344
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-rect 286542 39340 286548 39342
-rect 286612 39340 286618 39404
-rect 280153 39266 280219 39269
-rect 281206 39266 281212 39268
-rect 280153 39264 281212 39266
-rect 280153 39208 280158 39264
-rect 280214 39208 281212 39264
-rect 280153 39206 281212 39208
-rect 280153 39203 280219 39206
-rect 281206 39204 281212 39206
-rect 281276 39204 281282 39268
-rect 276013 39132 276079 39133
-rect 276013 39130 276060 39132
-rect 275968 39128 276060 39130
-rect 275968 39072 276018 39128
-rect 275968 39070 276060 39072
-rect 276013 39068 276060 39070
-rect 276124 39068 276130 39132
-rect 276013 39067 276079 39068
-rect 247033 38994 247099 38997
-rect 247166 38994 247172 38996
-rect 247033 38992 247172 38994
-rect 247033 38936 247038 38992
-rect 247094 38936 247172 38992
-rect 247033 38934 247172 38936
-rect 247033 38931 247099 38934
-rect 247166 38932 247172 38934
-rect 247236 38932 247242 38996
-rect 235993 38858 236059 38861
-rect 236494 38858 236500 38860
-rect 235993 38856 236500 38858
-rect 235993 38800 235998 38856
-rect 236054 38800 236500 38856
-rect 235993 38798 236500 38800
-rect 235993 38795 236059 38798
-rect 236494 38796 236500 38798
-rect 236564 38796 236570 38860
+rect 276013 39268 276079 39269
+rect 276013 39266 276060 39268
+rect 275968 39264 276060 39266
+rect 275968 39208 276018 39264
+rect 275968 39206 276060 39208
+rect 276013 39204 276060 39206
+rect 276124 39204 276130 39268
+rect 288433 39266 288499 39269
+rect 289118 39266 289124 39268
+rect 288433 39264 289124 39266
+rect 288433 39208 288438 39264
+rect 288494 39208 289124 39264
+rect 288433 39206 289124 39208
+rect 276013 39203 276079 39204
+rect 288433 39203 288499 39206
+rect 289118 39204 289124 39206
+rect 289188 39204 289194 39268
+rect 303613 39266 303679 39269
+rect 304758 39266 304764 39268
+rect 303613 39264 304764 39266
+rect 303613 39208 303618 39264
+rect 303674 39208 304764 39264
+rect 303613 39206 304764 39208
+rect 303613 39203 303679 39206
+rect 304758 39204 304764 39206
+rect 304828 39204 304834 39268
+rect 302233 39130 302299 39133
+rect 302366 39130 302372 39132
+rect 302233 39128 302372 39130
+rect 302233 39072 302238 39128
+rect 302294 39072 302372 39128
+rect 302233 39070 302372 39072
+rect 302233 39067 302299 39070
+rect 302366 39068 302372 39070
+rect 302436 39068 302442 39132
+rect 235993 38994 236059 38997
+rect 236494 38994 236500 38996
+rect 235993 38992 236500 38994
+rect 235993 38936 235998 38992
+rect 236054 38936 236500 38992
+rect 235993 38934 236500 38936
+rect 235993 38931 236059 38934
+rect 236494 38932 236500 38934
+rect 236564 38932 236570 38996
+rect 220813 38860 220879 38861
+rect 220813 38858 220860 38860
+rect 220768 38856 220860 38858
+rect 220768 38800 220818 38856
+rect 220768 38798 220860 38800
+rect 220813 38796 220860 38798
+rect 220924 38796 220930 38860
+rect 291193 38858 291259 38861
+rect 291694 38858 291700 38860
+rect 291193 38856 291700 38858
+rect 291193 38800 291198 38856
+rect 291254 38800 291700 38856
+rect 291193 38798 291700 38800
+rect 220813 38795 220879 38796
+rect 291193 38795 291259 38798
+rect 291694 38796 291700 38798
+rect 291764 38796 291770 38860
rect 207606 38660 207612 38724
rect 207676 38660 207682 38724
rect 227713 38722 227779 38725
@@ -4096,24 +4154,6 @@
rect 227713 38659 227779 38662
rect 228582 38660 228588 38662
rect 228652 38660 228658 38724
-rect 233233 38722 233299 38725
-rect 233918 38722 233924 38724
-rect 233233 38720 233924 38722
-rect 233233 38664 233238 38720
-rect 233294 38664 233924 38720
-rect 233233 38662 233924 38664
-rect 233233 38659 233299 38662
-rect 233918 38660 233924 38662
-rect 233988 38660 233994 38724
-rect 238753 38722 238819 38725
-rect 239254 38722 239260 38724
-rect 238753 38720 239260 38722
-rect 238753 38664 238758 38720
-rect 238814 38664 239260 38720
-rect 238753 38662 239260 38664
-rect 238753 38659 238819 38662
-rect 239254 38660 239260 38662
-rect 239324 38660 239330 38724
rect 244273 38722 244339 38725
rect 244406 38722 244412 38724
rect 244273 38720 244412 38722
@@ -4141,24 +4181,6 @@
rect 267733 38659 267799 38662
rect 268142 38660 268148 38662
rect 268212 38660 268218 38724
-rect 302233 38722 302299 38725
-rect 302366 38722 302372 38724
-rect 302233 38720 302372 38722
-rect 302233 38664 302238 38720
-rect 302294 38664 302372 38720
-rect 302233 38662 302372 38664
-rect 302233 38659 302299 38662
-rect 302366 38660 302372 38662
-rect 302436 38660 302442 38724
-rect 303613 38722 303679 38725
-rect 304758 38722 304764 38724
-rect 303613 38720 304764 38722
-rect 303613 38664 303618 38720
-rect 303674 38664 304764 38720
-rect 303613 38662 304764 38664
-rect 303613 38659 303679 38662
-rect 304758 38660 304764 38662
-rect 304828 38660 304834 38724
rect 200868 38584 207674 38586
rect 200868 38528 207018 38584
rect 207074 38528 207674 38584
@@ -4171,49 +4193,42 @@
rect -960 19260 480 19500
rect -960 6340 480 6580
rect 583520 6476 584960 6716
-rect 24209 3634 24275 3637
-rect 502333 3634 502399 3637
-rect 24209 3632 502399 3634
-rect 24209 3576 24214 3632
-rect 24270 3576 502338 3632
-rect 502394 3576 502399 3632
-rect 24209 3574 502399 3576
-rect 24209 3571 24275 3574
-rect 502333 3571 502399 3574
-rect 17033 3498 17099 3501
-rect 502425 3498 502491 3501
-rect 17033 3496 502491 3498
-rect 17033 3440 17038 3496
-rect 17094 3440 502430 3496
-rect 502486 3440 502491 3496
-rect 17033 3438 502491 3440
-rect 17033 3435 17099 3438
-rect 502425 3435 502491 3438
-rect 9949 3362 10015 3365
-rect 502609 3362 502675 3365
-rect 9949 3360 502675 3362
-rect 9949 3304 9954 3360
-rect 10010 3304 502614 3360
-rect 502670 3304 502675 3360
-rect 9949 3302 502675 3304
-rect 9949 3299 10015 3302
-rect 502609 3299 502675 3302
+rect 296069 3362 296135 3365
+rect 316534 3362 316540 3364
+rect 296069 3360 316540 3362
+rect 296069 3304 296074 3360
+rect 296130 3304 316540 3360
+rect 296069 3302 316540 3304
+rect 296069 3299 296135 3302
+rect 316534 3300 316540 3302
+rect 316604 3300 316610 3364
+rect 357525 3362 357591 3365
+rect 422886 3362 422892 3364
+rect 357525 3360 422892 3362
+rect 357525 3304 357530 3360
+rect 357586 3304 422892 3360
+rect 357525 3302 422892 3304
+rect 357525 3299 357591 3302
+rect 422886 3300 422892 3302
+rect 422956 3300 422962 3364
<< via3 >>
rect 318012 602244 318076 602308
-rect 316540 602108 316604 602172
-rect 314884 601972 314948 602036
-rect 319668 601836 319732 601900
+rect 313964 602108 314028 602172
+rect 319668 601972 319732 602036
+rect 314884 601836 314948 601900
+rect 422892 601836 422956 601900
rect 200804 601700 200868 601764
-rect 313964 601700 314028 601764
+rect 277900 601700 277964 601764
+rect 316540 601700 316604 601764
+rect 423996 601700 424060 601764
rect 241284 599252 241348 599316
-rect 275140 599252 275204 599316
rect 306236 599252 306300 599316
rect 451044 599252 451108 599316
-rect 275140 291756 275204 291820
+rect 277900 284820 277964 284884
rect 241284 110468 241348 110532
rect 306236 110468 306300 110532
-rect 272766 41380 272830 41444
-rect 318012 40972 318076 41036
+rect 318012 41108 318076 41172
+rect 423996 41108 424060 41172
rect 228404 40020 228468 40084
rect 230980 40020 231044 40084
rect 233188 40080 233252 40084
@@ -4228,24 +4243,24 @@
rect 241468 40020 241532 40024
rect 244044 40020 244108 40084
rect 246252 40020 246316 40084
+rect 248828 40020 248892 40084
rect 254532 39944 254596 39948
rect 254532 39888 254546 39944
rect 254546 39888 254596 39944
rect 254532 39884 254596 39888
rect 262444 39944 262508 39948
rect 282868 40020 282932 40084
-rect 307340 40080 307404 40084
-rect 316540 40836 316604 40900
-rect 319668 40700 319732 40764
-rect 307340 40024 307390 40080
-rect 307390 40024 307404 40080
-rect 307340 40020 307404 40024
+rect 306420 40020 306484 40084
+rect 319668 40156 319732 40220
rect 451044 40700 451108 40764
rect 262444 39888 262494 39944
rect 262494 39888 262508 39944
rect 262444 39884 262508 39888
rect 226196 39748 226260 39812
rect 231532 39748 231596 39812
+rect 239260 39748 239324 39812
+rect 241836 39748 241900 39812
+rect 247172 39748 247236 39812
rect 249932 39748 249996 39812
rect 252508 39808 252572 39812
rect 252508 39752 252558 39808
@@ -4269,35 +4284,12 @@
rect 270172 39748 270236 39752
rect 270908 39748 270972 39812
rect 273484 39748 273548 39812
+rect 313964 39884 314028 39948
rect 275508 39808 275572 39812
rect 275508 39752 275522 39808
rect 275522 39752 275572 39808
-rect 275508 39748 275572 39752
-rect 278268 39808 278332 39812
-rect 278268 39752 278318 39808
-rect 278318 39752 278332 39808
-rect 278268 39748 278332 39752
-rect 278636 39748 278700 39812
-rect 280660 39808 280724 39812
-rect 280660 39752 280674 39808
-rect 280674 39752 280724 39808
-rect 280660 39748 280724 39752
-rect 282868 39748 282932 39812
-rect 289124 39748 289188 39812
-rect 293908 39808 293972 39812
-rect 293908 39752 293922 39808
-rect 293922 39752 293972 39808
-rect 293908 39748 293972 39752
-rect 220860 39672 220924 39676
-rect 220860 39616 220874 39672
-rect 220874 39616 220924 39672
-rect 220860 39612 220924 39616
rect 223620 39612 223684 39676
-rect 241836 39612 241900 39676
-rect 249012 39672 249076 39676
-rect 249012 39616 249026 39672
-rect 249026 39616 249076 39672
-rect 249012 39612 249076 39616
+rect 233924 39612 233988 39676
rect 251772 39672 251836 39676
rect 251772 39616 251822 39672
rect 251822 39616 251836 39672
@@ -4310,6 +4302,21 @@
rect 259500 39616 259550 39672
rect 259550 39616 259564 39672
rect 259500 39612 259564 39616
+rect 272748 39612 272812 39676
+rect 275508 39748 275572 39752
+rect 278268 39808 278332 39812
+rect 278268 39752 278318 39808
+rect 278318 39752 278332 39808
+rect 278268 39748 278332 39752
+rect 278636 39748 278700 39812
+rect 280660 39808 280724 39812
+rect 280660 39752 280674 39808
+rect 280674 39752 280724 39808
+rect 280660 39748 280724 39752
+rect 281396 39748 281460 39812
+rect 307038 39808 307102 39812
+rect 307038 39752 307078 39808
+rect 307078 39752 307102 39808
rect 283604 39672 283668 39676
rect 283604 39616 283654 39672
rect 283654 39616 283668 39672
@@ -4318,25 +4325,27 @@
rect 286180 39616 286230 39672
rect 286230 39616 286244 39672
rect 286180 39612 286244 39616
+rect 288756 39672 288820 39676
+rect 288756 39616 288806 39672
+rect 288806 39616 288820 39672
+rect 288756 39612 288820 39616
rect 291332 39672 291396 39676
rect 291332 39616 291382 39672
rect 291382 39616 291396 39672
rect 291332 39612 291396 39616
-rect 291700 39612 291764 39676
+rect 293908 39672 293972 39676
+rect 293908 39616 293922 39672
+rect 293922 39616 293972 39672
+rect 293908 39612 293972 39616
rect 294276 39612 294340 39676
rect 296484 39672 296548 39676
rect 296484 39616 296534 39672
rect 296534 39616 296548 39672
rect 296484 39612 296548 39616
-rect 296852 39672 296916 39676
-rect 296852 39616 296866 39672
-rect 296866 39616 296916 39672
-rect 296852 39612 296916 39616
rect 299244 39672 299308 39676
rect 299244 39616 299294 39672
rect 299294 39616 299308 39672
rect 299244 39612 299308 39616
-rect 299796 39612 299860 39676
rect 301820 39672 301884 39676
rect 301820 39616 301834 39672
rect 301834 39616 301884 39672
@@ -4345,29 +4354,36 @@
rect 304396 39616 304410 39672
rect 304410 39616 304460 39672
rect 304396 39612 304460 39616
-rect 288756 39476 288820 39540
+rect 307038 39748 307102 39752
rect 307524 39748 307588 39812
-rect 313964 39612 314028 39676
-rect 314884 39476 314948 39540
+rect 314884 39612 314948 39676
+rect 282684 39476 282748 39540
+rect 286548 39476 286612 39540
+rect 297036 39476 297100 39540
+rect 299796 39476 299860 39540
+rect 306420 39476 306484 39540
rect 283972 39340 284036 39404
-rect 286548 39340 286612 39404
-rect 281212 39204 281276 39268
-rect 276060 39128 276124 39132
-rect 276060 39072 276074 39128
-rect 276074 39072 276124 39128
-rect 276060 39068 276124 39072
-rect 247172 38932 247236 38996
-rect 236500 38796 236564 38860
+rect 276060 39264 276124 39268
+rect 276060 39208 276074 39264
+rect 276074 39208 276124 39264
+rect 276060 39204 276124 39208
+rect 289124 39204 289188 39268
+rect 304764 39204 304828 39268
+rect 302372 39068 302436 39132
+rect 236500 38932 236564 38996
+rect 220860 38856 220924 38860
+rect 220860 38800 220874 38856
+rect 220874 38800 220924 38856
+rect 220860 38796 220924 38800
+rect 291700 38796 291764 38860
rect 207612 38660 207676 38724
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rect 228588 38660 228652 38724
-rect 233924 38660 233988 38724
-rect 239260 38660 239324 38724
rect 244412 38660 244476 38724
rect 265572 38660 265636 38724
rect 268148 38660 268212 38724
-rect 302372 38660 302436 38724
-rect 304764 38660 304828 38724
+rect 316540 3300 316604 3364
+rect 422892 3300 422956 3364
<< metal4 >>
rect -8726 711558 -8106 711590
rect -8726 711322 -8694 711558
@@ -14063,75 +14079,18 @@
rect 315234 604338 315266 604574
rect 315502 604338 315586 604574
rect 315822 604338 315854 604574
-rect 314883 602036 314949 602037
-rect 314883 601972 314884 602036
-rect 314948 601972 314949 602036
-rect 315234 602000 315854 604338
-rect 318954 680614 319574 711002
-rect 336954 710598 337574 711590
-rect 336954 710362 336986 710598
-rect 337222 710362 337306 710598
-rect 337542 710362 337574 710598
-rect 336954 710278 337574 710362
-rect 336954 710042 336986 710278
-rect 337222 710042 337306 710278
-rect 337542 710042 337574 710278
-rect 333234 708678 333854 709670
-rect 333234 708442 333266 708678
-rect 333502 708442 333586 708678
-rect 333822 708442 333854 708678
-rect 333234 708358 333854 708442
-rect 333234 708122 333266 708358
-rect 333502 708122 333586 708358
-rect 333822 708122 333854 708358
-rect 329514 706758 330134 707750
-rect 329514 706522 329546 706758
-rect 329782 706522 329866 706758
-rect 330102 706522 330134 706758
-rect 329514 706438 330134 706522
-rect 329514 706202 329546 706438
-rect 329782 706202 329866 706438
-rect 330102 706202 330134 706438
-rect 318954 680378 318986 680614
-rect 319222 680378 319306 680614
-rect 319542 680378 319574 680614
-rect 318954 680294 319574 680378
-rect 318954 680058 318986 680294
-rect 319222 680058 319306 680294
-rect 319542 680058 319574 680294
-rect 318954 644614 319574 680058
-rect 318954 644378 318986 644614
-rect 319222 644378 319306 644614
-rect 319542 644378 319574 644614
-rect 318954 644294 319574 644378
-rect 318954 644058 318986 644294
-rect 319222 644058 319306 644294
-rect 319542 644058 319574 644294
-rect 318954 608614 319574 644058
-rect 318954 608378 318986 608614
-rect 319222 608378 319306 608614
-rect 319542 608378 319574 608614
-rect 318954 608294 319574 608378
-rect 318954 608058 318986 608294
-rect 319222 608058 319306 608294
-rect 319542 608058 319574 608294
-rect 318011 602308 318077 602309
-rect 318011 602244 318012 602308
-rect 318076 602244 318077 602308
-rect 318011 602243 318077 602244
-rect 316539 602172 316605 602173
-rect 316539 602108 316540 602172
-rect 316604 602108 316605 602172
-rect 316539 602107 316605 602108
-rect 314883 601971 314949 601972
+rect 313963 602172 314029 602173
+rect 313963 602108 313964 602172
+rect 314028 602108 314029 602172
+rect 313963 602107 314029 602108
rect 200803 601764 200869 601765
rect 200803 601700 200804 601764
rect 200868 601700 200869 601764
rect 200803 601699 200869 601700
-rect 313963 601764 314029 601765
-rect 313963 601700 313964 601764
-rect 314028 601700 314029 601764
-rect 313963 601699 314029 601700
+rect 277899 601764 277965 601765
+rect 277899 601700 277900 601764
+rect 277964 601700 277965 601764
+rect 277899 601699 277965 601700
rect 192954 590378 192986 590614
rect 193222 590378 193306 590614
rect 193542 590378 193574 590614
@@ -14320,14 +14279,6 @@
rect 241283 599252 241284 599316
rect 241348 599252 241349 599316
rect 241283 599251 241349 599252
-rect 275139 599316 275205 599317
-rect 275139 599252 275140 599316
-rect 275204 599252 275205 599316
-rect 275139 599251 275205 599252
-rect 306235 599316 306301 599317
-rect 306235 599252 306236 599316
-rect 306300 599252 306301 599316
-rect 306235 599251 306301 599252
rect 219568 597454 219888 597486
rect 219568 597218 219610 597454
rect 219846 597218 219888 597454
@@ -15255,7 +15206,52 @@
rect 265542 122058 265574 122294
rect 264954 113068 265574 122058
rect 271794 273454 272414 298000
-rect 275142 291821 275202 599251
+rect 271794 273218 271826 273454
+rect 272062 273218 272146 273454
+rect 272382 273218 272414 273454
+rect 271794 273134 272414 273218
+rect 271794 272898 271826 273134
+rect 272062 272898 272146 273134
+rect 272382 272898 272414 273134
+rect 271794 237454 272414 272898
+rect 271794 237218 271826 237454
+rect 272062 237218 272146 237454
+rect 272382 237218 272414 237454
+rect 271794 237134 272414 237218
+rect 271794 236898 271826 237134
+rect 272062 236898 272146 237134
+rect 272382 236898 272414 237134
+rect 271794 201454 272414 236898
+rect 271794 201218 271826 201454
+rect 272062 201218 272146 201454
+rect 272382 201218 272414 201454
+rect 271794 201134 272414 201218
+rect 271794 200898 271826 201134
+rect 272062 200898 272146 201134
+rect 272382 200898 272414 201134
+rect 271794 165454 272414 200898
+rect 271794 165218 271826 165454
+rect 272062 165218 272146 165454
+rect 272382 165218 272414 165454
+rect 271794 165134 272414 165218
+rect 271794 164898 271826 165134
+rect 272062 164898 272146 165134
+rect 272382 164898 272414 165134
+rect 271794 129454 272414 164898
+rect 271794 129218 271826 129454
+rect 272062 129218 272146 129454
+rect 272382 129218 272414 129454
+rect 271794 129134 272414 129218
+rect 271794 128898 271826 129134
+rect 272062 128898 272146 129134
+rect 272382 128898 272414 129134
+rect 271794 113068 272414 128898
+rect 275514 277174 276134 298000
+rect 277902 284885 277962 601699
+rect 306235 599316 306301 599317
+rect 306235 599252 306236 599316
+rect 306300 599252 306301 599316
+rect 306235 599251 306301 599252
rect 281008 597454 281328 597486
rect 281008 597218 281050 597454
rect 281286 597218 281328 597454
@@ -15375,51 +15371,10 @@
rect 281008 308898 281050 309134
rect 281286 308898 281328 309134
rect 281008 308866 281328 308898
-rect 275139 291820 275205 291821
-rect 275139 291756 275140 291820
-rect 275204 291756 275205 291820
-rect 275139 291755 275205 291756
-rect 271794 273218 271826 273454
-rect 272062 273218 272146 273454
-rect 272382 273218 272414 273454
-rect 271794 273134 272414 273218
-rect 271794 272898 271826 273134
-rect 272062 272898 272146 273134
-rect 272382 272898 272414 273134
-rect 271794 237454 272414 272898
-rect 271794 237218 271826 237454
-rect 272062 237218 272146 237454
-rect 272382 237218 272414 237454
-rect 271794 237134 272414 237218
-rect 271794 236898 271826 237134
-rect 272062 236898 272146 237134
-rect 272382 236898 272414 237134
-rect 271794 201454 272414 236898
-rect 271794 201218 271826 201454
-rect 272062 201218 272146 201454
-rect 272382 201218 272414 201454
-rect 271794 201134 272414 201218
-rect 271794 200898 271826 201134
-rect 272062 200898 272146 201134
-rect 272382 200898 272414 201134
-rect 271794 165454 272414 200898
-rect 271794 165218 271826 165454
-rect 272062 165218 272146 165454
-rect 272382 165218 272414 165454
-rect 271794 165134 272414 165218
-rect 271794 164898 271826 165134
-rect 272062 164898 272146 165134
-rect 272382 164898 272414 165134
-rect 271794 129454 272414 164898
-rect 271794 129218 271826 129454
-rect 272062 129218 272146 129454
-rect 272382 129218 272414 129454
-rect 271794 129134 272414 129218
-rect 271794 128898 271826 129134
-rect 272062 128898 272146 129134
-rect 272382 128898 272414 129134
-rect 271794 113068 272414 128898
-rect 275514 277174 276134 298000
+rect 277899 284884 277965 284885
+rect 277899 284820 277900 284884
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@@ -15875,11 +15830,6 @@
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@@ -15889,7 +15839,7 @@
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@@ -15917,14 +15867,14 @@
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@@ -15949,21 +15899,12 @@
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@@ -15973,17 +15914,34 @@
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@@ -15991,15 +15949,23 @@
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@@ -16067,10 +16033,6 @@
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@@ -16083,10 +16045,6 @@
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@@ -16099,17 +16057,20 @@
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@@ -16123,9 +16084,18 @@
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@@ -16138,22 +16108,18 @@
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@@ -16163,76 +16129,69 @@
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@@ -16241,54 +16200,110 @@
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-rect 192954 -6426 193574 -6342
-rect 192954 -6662 192986 -6426
-rect 193222 -6662 193306 -6426
-rect 193542 -6662 193574 -6426
-rect 192954 -7654 193574 -6662
-rect 210954 -7066 211574 32058
-rect 217794 3454 218414 38000
-rect 217794 3218 217826 3454
-rect 218062 3218 218146 3454
-rect 218382 3218 218414 3454
-rect 217794 3134 218414 3218
-rect 217794 2898 217826 3134
-rect 218062 2898 218146 3134
-rect 218382 2898 218414 3134
-rect 217794 -346 218414 2898
-rect 217794 -582 217826 -346
-rect 218062 -582 218146 -346
-rect 218382 -582 218414 -346
-rect 217794 -666 218414 -582
-rect 217794 -902 217826 -666
-rect 218062 -902 218146 -666
-rect 218382 -902 218414 -666
-rect 217794 -1894 218414 -902
-rect 221514 7174 222134 38000
-rect 221514 6938 221546 7174
-rect 221782 6938 221866 7174
-rect 222102 6938 222134 7174
-rect 221514 6854 222134 6938
-rect 221514 6618 221546 6854
-rect 221782 6618 221866 6854
-rect 222102 6618 222134 6854
-rect 221514 -2266 222134 6618
-rect 221514 -2502 221546 -2266
-rect 221782 -2502 221866 -2266
-rect 222102 -2502 222134 -2266
-rect 221514 -2586 222134 -2502
-rect 221514 -2822 221546 -2586
-rect 221782 -2822 221866 -2586
-rect 222102 -2822 222134 -2586
-rect 221514 -3814 222134 -2822
-rect 225234 10894 225854 38000
-rect 225234 10658 225266 10894
-rect 225502 10658 225586 10894
-rect 225822 10658 225854 10894
-rect 225234 10574 225854 10658
-rect 225234 10338 225266 10574
-rect 225502 10338 225586 10574
-rect 225822 10338 225854 10574
-rect 225234 -4186 225854 10338
-rect 225234 -4422 225266 -4186
-rect 225502 -4422 225586 -4186
-rect 225822 -4422 225854 -4186
-rect 225234 -4506 225854 -4422
-rect 225234 -4742 225266 -4506
-rect 225502 -4742 225586 -4506
-rect 225822 -4742 225854 -4506
-rect 225234 -5734 225854 -4742
-rect 228954 14614 229574 38000
-rect 228954 14378 228986 14614
-rect 229222 14378 229306 14614
-rect 229542 14378 229574 14614
-rect 228954 14294 229574 14378
-rect 228954 14058 228986 14294
-rect 229222 14058 229306 14294
-rect 229542 14058 229574 14294
-rect 210954 -7302 210986 -7066
-rect 211222 -7302 211306 -7066
-rect 211542 -7302 211574 -7066
-rect 210954 -7386 211574 -7302
-rect 210954 -7622 210986 -7386
-rect 211222 -7622 211306 -7386
-rect 211542 -7622 211574 -7386
-rect 210954 -7654 211574 -7622
-rect 228954 -6106 229574 14058
-rect 235794 21454 236414 38000
-rect 235794 21218 235826 21454
-rect 236062 21218 236146 21454
-rect 236382 21218 236414 21454
-rect 235794 21134 236414 21218
-rect 235794 20898 235826 21134
-rect 236062 20898 236146 21134
-rect 236382 20898 236414 21134
-rect 235794 -1306 236414 20898
-rect 235794 -1542 235826 -1306
-rect 236062 -1542 236146 -1306
-rect 236382 -1542 236414 -1306
-rect 235794 -1626 236414 -1542
-rect 235794 -1862 235826 -1626
-rect 236062 -1862 236146 -1626
-rect 236382 -1862 236414 -1626
-rect 235794 -1894 236414 -1862
-rect 239514 25174 240134 38000
-rect 239514 24938 239546 25174
-rect 239782 24938 239866 25174
-rect 240102 24938 240134 25174
-rect 239514 24854 240134 24938
-rect 239514 24618 239546 24854
-rect 239782 24618 239866 24854
-rect 240102 24618 240134 24854
-rect 239514 -3226 240134 24618
-rect 239514 -3462 239546 -3226
-rect 239782 -3462 239866 -3226
-rect 240102 -3462 240134 -3226
-rect 239514 -3546 240134 -3462
-rect 239514 -3782 239546 -3546
-rect 239782 -3782 239866 -3546
-rect 240102 -3782 240134 -3546
-rect 239514 -3814 240134 -3782
-rect 243234 28894 243854 38000
-rect 243234 28658 243266 28894
-rect 243502 28658 243586 28894
-rect 243822 28658 243854 28894
-rect 243234 28574 243854 28658
-rect 243234 28338 243266 28574
-rect 243502 28338 243586 28574
-rect 243822 28338 243854 28574
-rect 243234 -5146 243854 28338
-rect 243234 -5382 243266 -5146
-rect 243502 -5382 243586 -5146
-rect 243822 -5382 243854 -5146
-rect 243234 -5466 243854 -5382
-rect 243234 -5702 243266 -5466
-rect 243502 -5702 243586 -5466
-rect 243822 -5702 243854 -5466
-rect 243234 -5734 243854 -5702
-rect 246954 32614 247574 38000
-rect 246954 32378 246986 32614
-rect 247222 32378 247306 32614
-rect 247542 32378 247574 32614
-rect 246954 32294 247574 32378
-rect 246954 32058 246986 32294
-rect 247222 32058 247306 32294
-rect 247542 32058 247574 32294
-rect 228954 -6342 228986 -6106
-rect 229222 -6342 229306 -6106
-rect 229542 -6342 229574 -6106
-rect 228954 -6426 229574 -6342
-rect 228954 -6662 228986 -6426
-rect 229222 -6662 229306 -6426
-rect 229542 -6662 229574 -6426
-rect 228954 -7654 229574 -6662
-rect 246954 -7066 247574 32058
-rect 253794 3454 254414 38000
-rect 253794 3218 253826 3454
-rect 254062 3218 254146 3454
-rect 254382 3218 254414 3454
-rect 253794 3134 254414 3218
-rect 253794 2898 253826 3134
-rect 254062 2898 254146 3134
-rect 254382 2898 254414 3134
-rect 253794 -346 254414 2898
-rect 253794 -582 253826 -346
-rect 254062 -582 254146 -346
-rect 254382 -582 254414 -346
-rect 253794 -666 254414 -582
-rect 253794 -902 253826 -666
-rect 254062 -902 254146 -666
-rect 254382 -902 254414 -666
-rect 253794 -1894 254414 -902
-rect 257514 7174 258134 38000
-rect 257514 6938 257546 7174
-rect 257782 6938 257866 7174
-rect 258102 6938 258134 7174
-rect 257514 6854 258134 6938
-rect 257514 6618 257546 6854
-rect 257782 6618 257866 6854
-rect 258102 6618 258134 6854
-rect 257514 -2266 258134 6618
-rect 257514 -2502 257546 -2266
-rect 257782 -2502 257866 -2266
-rect 258102 -2502 258134 -2266
-rect 257514 -2586 258134 -2502
-rect 257514 -2822 257546 -2586
-rect 257782 -2822 257866 -2586
-rect 258102 -2822 258134 -2586
-rect 257514 -3814 258134 -2822
-rect 261234 10894 261854 38000
-rect 261234 10658 261266 10894
-rect 261502 10658 261586 10894
-rect 261822 10658 261854 10894
-rect 261234 10574 261854 10658
-rect 261234 10338 261266 10574
-rect 261502 10338 261586 10574
-rect 261822 10338 261854 10574
-rect 261234 -4186 261854 10338
-rect 261234 -4422 261266 -4186
-rect 261502 -4422 261586 -4186
-rect 261822 -4422 261854 -4186
-rect 261234 -4506 261854 -4422
-rect 261234 -4742 261266 -4506
-rect 261502 -4742 261586 -4506
-rect 261822 -4742 261854 -4506
-rect 261234 -5734 261854 -4742
-rect 264954 14614 265574 38000
-rect 264954 14378 264986 14614
-rect 265222 14378 265306 14614
-rect 265542 14378 265574 14614
-rect 264954 14294 265574 14378
-rect 264954 14058 264986 14294
-rect 265222 14058 265306 14294
-rect 265542 14058 265574 14294
-rect 246954 -7302 246986 -7066
-rect 247222 -7302 247306 -7066
-rect 247542 -7302 247574 -7066
-rect 246954 -7386 247574 -7302
-rect 246954 -7622 246986 -7386
-rect 247222 -7622 247306 -7386
-rect 247542 -7622 247574 -7386
-rect 246954 -7654 247574 -7622
-rect 264954 -6106 265574 14058
-rect 271794 21454 272414 38000
-rect 271794 21218 271826 21454
-rect 272062 21218 272146 21454
-rect 272382 21218 272414 21454
-rect 271794 21134 272414 21218
-rect 271794 20898 271826 21134
-rect 272062 20898 272146 21134
-rect 272382 20898 272414 21134
-rect 271794 -1306 272414 20898
-rect 271794 -1542 271826 -1306
-rect 272062 -1542 272146 -1306
-rect 272382 -1542 272414 -1306
-rect 271794 -1626 272414 -1542
-rect 271794 -1862 271826 -1626
-rect 272062 -1862 272146 -1626
-rect 272382 -1862 272414 -1626
-rect 271794 -1894 272414 -1862
-rect 275514 25174 276134 38000
-rect 275514 24938 275546 25174
-rect 275782 24938 275866 25174
-rect 276102 24938 276134 25174
-rect 275514 24854 276134 24938
-rect 275514 24618 275546 24854
-rect 275782 24618 275866 24854
-rect 276102 24618 276134 24854
-rect 275514 -3226 276134 24618
-rect 275514 -3462 275546 -3226
-rect 275782 -3462 275866 -3226
-rect 276102 -3462 276134 -3226
-rect 275514 -3546 276134 -3462
-rect 275514 -3782 275546 -3546
-rect 275782 -3782 275866 -3546
-rect 276102 -3782 276134 -3546
-rect 275514 -3814 276134 -3782
-rect 279234 28894 279854 38000
-rect 279234 28658 279266 28894
-rect 279502 28658 279586 28894
-rect 279822 28658 279854 28894
-rect 279234 28574 279854 28658
-rect 279234 28338 279266 28574
-rect 279502 28338 279586 28574
-rect 279822 28338 279854 28574
-rect 279234 -5146 279854 28338
-rect 279234 -5382 279266 -5146
-rect 279502 -5382 279586 -5146
-rect 279822 -5382 279854 -5146
-rect 279234 -5466 279854 -5382
-rect 279234 -5702 279266 -5466
-rect 279502 -5702 279586 -5466
-rect 279822 -5702 279854 -5466
-rect 279234 -5734 279854 -5702
-rect 282954 32614 283574 38000
-rect 282954 32378 282986 32614
-rect 283222 32378 283306 32614
-rect 283542 32378 283574 32614
-rect 282954 32294 283574 32378
-rect 282954 32058 282986 32294
-rect 283222 32058 283306 32294
-rect 283542 32058 283574 32294
-rect 264954 -6342 264986 -6106
-rect 265222 -6342 265306 -6106
-rect 265542 -6342 265574 -6106
-rect 264954 -6426 265574 -6342
-rect 264954 -6662 264986 -6426
-rect 265222 -6662 265306 -6426
-rect 265542 -6662 265574 -6426
-rect 264954 -7654 265574 -6662
-rect 282954 -7066 283574 32058
-rect 289794 3454 290414 38000
-rect 289794 3218 289826 3454
-rect 290062 3218 290146 3454
-rect 290382 3218 290414 3454
-rect 289794 3134 290414 3218
-rect 289794 2898 289826 3134
-rect 290062 2898 290146 3134
-rect 290382 2898 290414 3134
-rect 289794 -346 290414 2898
-rect 289794 -582 289826 -346
-rect 290062 -582 290146 -346
-rect 290382 -582 290414 -346
-rect 289794 -666 290414 -582
-rect 289794 -902 289826 -666
-rect 290062 -902 290146 -666
-rect 290382 -902 290414 -666
-rect 289794 -1894 290414 -902
-rect 293514 7174 294134 38000
-rect 293514 6938 293546 7174
-rect 293782 6938 293866 7174
-rect 294102 6938 294134 7174
-rect 293514 6854 294134 6938
-rect 293514 6618 293546 6854
-rect 293782 6618 293866 6854
-rect 294102 6618 294134 6854
-rect 293514 -2266 294134 6618
-rect 293514 -2502 293546 -2266
-rect 293782 -2502 293866 -2266
-rect 294102 -2502 294134 -2266
-rect 293514 -2586 294134 -2502
-rect 293514 -2822 293546 -2586
-rect 293782 -2822 293866 -2586
-rect 294102 -2822 294134 -2586
-rect 293514 -3814 294134 -2822
-rect 297234 10894 297854 38000
-rect 297234 10658 297266 10894
-rect 297502 10658 297586 10894
-rect 297822 10658 297854 10894
-rect 297234 10574 297854 10658
-rect 297234 10338 297266 10574
-rect 297502 10338 297586 10574
-rect 297822 10338 297854 10574
-rect 297234 -4186 297854 10338
-rect 297234 -4422 297266 -4186
-rect 297502 -4422 297586 -4186
-rect 297822 -4422 297854 -4186
-rect 297234 -4506 297854 -4422
-rect 297234 -4742 297266 -4506
-rect 297502 -4742 297586 -4506
-rect 297822 -4742 297854 -4506
-rect 297234 -5734 297854 -4742
-rect 300954 14614 301574 38000
-rect 300954 14378 300986 14614
-rect 301222 14378 301306 14614
-rect 301542 14378 301574 14614
-rect 300954 14294 301574 14378
-rect 300954 14058 300986 14294
-rect 301222 14058 301306 14294
-rect 301542 14058 301574 14294
-rect 282954 -7302 282986 -7066
-rect 283222 -7302 283306 -7066
-rect 283542 -7302 283574 -7066
-rect 282954 -7386 283574 -7302
-rect 282954 -7622 282986 -7386
-rect 283222 -7622 283306 -7386
-rect 283542 -7622 283574 -7386
-rect 282954 -7654 283574 -7622
-rect 300954 -6106 301574 14058
-rect 307794 21454 308414 38000
-rect 307794 21218 307826 21454
-rect 308062 21218 308146 21454
-rect 308382 21218 308414 21454
-rect 307794 21134 308414 21218
-rect 307794 20898 307826 21134
-rect 308062 20898 308146 21134
-rect 308382 20898 308414 21134
-rect 307794 -1306 308414 20898
-rect 307794 -1542 307826 -1306
-rect 308062 -1542 308146 -1306
-rect 308382 -1542 308414 -1306
-rect 307794 -1626 308414 -1542
-rect 307794 -1862 307826 -1626
-rect 308062 -1862 308146 -1626
-rect 308382 -1862 308414 -1626
-rect 307794 -1894 308414 -1862
-rect 311514 25174 312134 38000
-rect 311514 24938 311546 25174
-rect 311782 24938 311866 25174
-rect 312102 24938 312134 25174
-rect 311514 24854 312134 24938
-rect 311514 24618 311546 24854
-rect 311782 24618 311866 24854
-rect 312102 24618 312134 24854
-rect 311514 -3226 312134 24618
-rect 311514 -3462 311546 -3226
-rect 311782 -3462 311866 -3226
-rect 312102 -3462 312134 -3226
-rect 311514 -3546 312134 -3462
-rect 311514 -3782 311546 -3546
-rect 311782 -3782 311866 -3546
-rect 312102 -3782 312134 -3546
-rect 311514 -3814 312134 -3782
-rect 315234 28894 315854 38000
-rect 315234 28658 315266 28894
-rect 315502 28658 315586 28894
-rect 315822 28658 315854 28894
-rect 315234 28574 315854 28658
-rect 315234 28338 315266 28574
-rect 315502 28338 315586 28574
-rect 315822 28338 315854 28574
-rect 315234 -5146 315854 28338
-rect 315234 -5382 315266 -5146
-rect 315502 -5382 315586 -5146
-rect 315822 -5382 315854 -5146
-rect 315234 -5466 315854 -5382
-rect 315234 -5702 315266 -5466
-rect 315502 -5702 315586 -5466
-rect 315822 -5702 315854 -5466
-rect 315234 -5734 315854 -5702
+rect 318011 41172 318077 41173
+rect 318011 41108 318012 41172
+rect 318076 41108 318077 41172
+rect 318011 41107 318077 41108
rect 318954 32614 319574 68058
-rect 319670 40765 319730 601835
-rect 451043 599316 451109 599317
-rect 451043 599252 451044 599316
-rect 451108 599252 451109 599316
-rect 451043 599251 451109 599252
+rect 319670 40221 319730 601971
+rect 422891 601900 422957 601901
+rect 422891 601836 422892 601900
+rect 422956 601836 422957 601900
+rect 422891 601835 422957 601836
rect 342448 597454 342768 597486
rect 342448 597218 342490 597454
rect 342726 597218 342768 597454
@@ -18245,13 +18261,6 @@
rect 403888 596898 403930 597134
rect 404166 596898 404208 597134
rect 403888 596866 404208 596898
-rect 434608 597454 434928 597486
-rect 434608 597218 434650 597454
-rect 434886 597218 434928 597454
-rect 434608 597134 434928 597218
-rect 434608 596898 434650 597134
-rect 434886 596898 434928 597134
-rect 434608 596866 434928 596898
rect 327088 579454 327408 579486
rect 327088 579218 327130 579454
rect 327366 579218 327408 579454
@@ -18280,13 +18289,6 @@
rect 419248 578898 419290 579134
rect 419526 578898 419568 579134
rect 419248 578866 419568 578898
-rect 449968 579454 450288 579486
-rect 449968 579218 450010 579454
-rect 450246 579218 450288 579454
-rect 449968 579134 450288 579218
-rect 449968 578898 450010 579134
-rect 450246 578898 450288 579134
-rect 449968 578866 450288 578898
rect 342448 561454 342768 561486
rect 342448 561218 342490 561454
rect 342726 561218 342768 561454
@@ -18308,13 +18310,6 @@
rect 403888 560898 403930 561134
rect 404166 560898 404208 561134
rect 403888 560866 404208 560898
-rect 434608 561454 434928 561486
-rect 434608 561218 434650 561454
-rect 434886 561218 434928 561454
-rect 434608 561134 434928 561218
-rect 434608 560898 434650 561134
-rect 434886 560898 434928 561134
-rect 434608 560866 434928 560898
rect 327088 543454 327408 543486
rect 327088 543218 327130 543454
rect 327366 543218 327408 543454
@@ -18343,13 +18338,6 @@
rect 419248 542898 419290 543134
rect 419526 542898 419568 543134
rect 419248 542866 419568 542898
-rect 449968 543454 450288 543486
-rect 449968 543218 450010 543454
-rect 450246 543218 450288 543454
-rect 449968 543134 450288 543218
-rect 449968 542898 450010 543134
-rect 450246 542898 450288 543134
-rect 449968 542866 450288 542898
rect 342448 525454 342768 525486
rect 342448 525218 342490 525454
rect 342726 525218 342768 525454
@@ -18371,13 +18359,6 @@
rect 403888 524898 403930 525134
rect 404166 524898 404208 525134
rect 403888 524866 404208 524898
-rect 434608 525454 434928 525486
-rect 434608 525218 434650 525454
-rect 434886 525218 434928 525454
-rect 434608 525134 434928 525218
-rect 434608 524898 434650 525134
-rect 434886 524898 434928 525134
-rect 434608 524866 434928 524898
rect 327088 507454 327408 507486
rect 327088 507218 327130 507454
rect 327366 507218 327408 507454
@@ -18406,13 +18387,6 @@
rect 419248 506898 419290 507134
rect 419526 506898 419568 507134
rect 419248 506866 419568 506898
-rect 449968 507454 450288 507486
-rect 449968 507218 450010 507454
-rect 450246 507218 450288 507454
-rect 449968 507134 450288 507218
-rect 449968 506898 450010 507134
-rect 450246 506898 450288 507134
-rect 449968 506866 450288 506898
rect 342448 489454 342768 489486
rect 342448 489218 342490 489454
rect 342726 489218 342768 489454
@@ -18434,13 +18408,6 @@
rect 403888 488898 403930 489134
rect 404166 488898 404208 489134
rect 403888 488866 404208 488898
-rect 434608 489454 434928 489486
-rect 434608 489218 434650 489454
-rect 434886 489218 434928 489454
-rect 434608 489134 434928 489218
-rect 434608 488898 434650 489134
-rect 434886 488898 434928 489134
-rect 434608 488866 434928 488898
rect 327088 471454 327408 471486
rect 327088 471218 327130 471454
rect 327366 471218 327408 471454
@@ -18469,13 +18436,6 @@
rect 419248 470898 419290 471134
rect 419526 470898 419568 471134
rect 419248 470866 419568 470898
-rect 449968 471454 450288 471486
-rect 449968 471218 450010 471454
-rect 450246 471218 450288 471454
-rect 449968 471134 450288 471218
-rect 449968 470898 450010 471134
-rect 450246 470898 450288 471134
-rect 449968 470866 450288 470898
rect 342448 453454 342768 453486
rect 342448 453218 342490 453454
rect 342726 453218 342768 453454
@@ -18497,13 +18457,6 @@
rect 403888 452898 403930 453134
rect 404166 452898 404208 453134
rect 403888 452866 404208 452898
-rect 434608 453454 434928 453486
-rect 434608 453218 434650 453454
-rect 434886 453218 434928 453454
-rect 434608 453134 434928 453218
-rect 434608 452898 434650 453134
-rect 434886 452898 434928 453134
-rect 434608 452866 434928 452898
rect 327088 435454 327408 435486
rect 327088 435218 327130 435454
rect 327366 435218 327408 435454
@@ -18532,13 +18485,6 @@
rect 419248 434898 419290 435134
rect 419526 434898 419568 435134
rect 419248 434866 419568 434898
-rect 449968 435454 450288 435486
-rect 449968 435218 450010 435454
-rect 450246 435218 450288 435454
-rect 449968 435134 450288 435218
-rect 449968 434898 450010 435134
-rect 450246 434898 450288 435134
-rect 449968 434866 450288 434898
rect 342448 417454 342768 417486
rect 342448 417218 342490 417454
rect 342726 417218 342768 417454
@@ -18560,13 +18506,6 @@
rect 403888 416898 403930 417134
rect 404166 416898 404208 417134
rect 403888 416866 404208 416898
-rect 434608 417454 434928 417486
-rect 434608 417218 434650 417454
-rect 434886 417218 434928 417454
-rect 434608 417134 434928 417218
-rect 434608 416898 434650 417134
-rect 434886 416898 434928 417134
-rect 434608 416866 434928 416898
rect 327088 399454 327408 399486
rect 327088 399218 327130 399454
rect 327366 399218 327408 399454
@@ -18595,13 +18534,6 @@
rect 419248 398898 419290 399134
rect 419526 398898 419568 399134
rect 419248 398866 419568 398898
-rect 449968 399454 450288 399486
-rect 449968 399218 450010 399454
-rect 450246 399218 450288 399454
-rect 449968 399134 450288 399218
-rect 449968 398898 450010 399134
-rect 450246 398898 450288 399134
-rect 449968 398866 450288 398898
rect 342448 381454 342768 381486
rect 342448 381218 342490 381454
rect 342726 381218 342768 381454
@@ -18623,13 +18555,6 @@
rect 403888 380898 403930 381134
rect 404166 380898 404208 381134
rect 403888 380866 404208 380898
-rect 434608 381454 434928 381486
-rect 434608 381218 434650 381454
-rect 434886 381218 434928 381454
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@@ -18658,13 +18583,6 @@
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@@ -18686,13 +18604,6 @@
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@@ -18721,13 +18632,6 @@
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@@ -18749,13 +18653,6 @@
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@@ -31734,6 +31756,26 @@
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@@ -31768,26 +31810,6 @@
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@@ -31992,6 +32014,30 @@
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+rect 283306 32058 283542 32294
+rect 264986 -6342 265222 -6106
+rect 265306 -6342 265542 -6106
+rect 264986 -6662 265222 -6426
+rect 265306 -6662 265542 -6426
+rect 289826 3218 290062 3454
+rect 290146 3218 290382 3454
+rect 289826 2898 290062 3134
+rect 290146 2898 290382 3134
+rect 289826 -582 290062 -346
+rect 290146 -582 290382 -346
+rect 289826 -902 290062 -666
+rect 290146 -902 290382 -666
+rect 293546 6938 293782 7174
+rect 293866 6938 294102 7174
+rect 293546 6618 293782 6854
+rect 293866 6618 294102 6854
+rect 293546 -2502 293782 -2266
+rect 293866 -2502 294102 -2266
+rect 293546 -2822 293782 -2586
+rect 293866 -2822 294102 -2586
+rect 297266 10658 297502 10894
+rect 297586 10658 297822 10894
+rect 297266 10338 297502 10574
+rect 297586 10338 297822 10574
+rect 297266 -4422 297502 -4186
+rect 297586 -4422 297822 -4186
+rect 297266 -4742 297502 -4506
+rect 297586 -4742 297822 -4506
+rect 300986 14378 301222 14614
+rect 301306 14378 301542 14614
+rect 300986 14058 301222 14294
+rect 301306 14058 301542 14294
+rect 282986 -7302 283222 -7066
+rect 283306 -7302 283542 -7066
+rect 282986 -7622 283222 -7386
+rect 283306 -7622 283542 -7386
+rect 307826 21218 308062 21454
+rect 308146 21218 308382 21454
+rect 307826 20898 308062 21134
+rect 308146 20898 308382 21134
+rect 307826 -1542 308062 -1306
+rect 308146 -1542 308382 -1306
+rect 307826 -1862 308062 -1626
+rect 308146 -1862 308382 -1626
+rect 311546 24938 311782 25174
+rect 311866 24938 312102 25174
+rect 311546 24618 311782 24854
+rect 311866 24618 312102 24854
+rect 311546 -3462 311782 -3226
+rect 311866 -3462 312102 -3226
+rect 311546 -3782 311782 -3546
+rect 311866 -3782 312102 -3546
+rect 315266 28658 315502 28894
+rect 315586 28658 315822 28894
+rect 315266 28338 315502 28574
+rect 315586 28338 315822 28574
rect 325826 704602 326062 704838
rect 326146 704602 326382 704838
rect 325826 704282 326062 704518
@@ -32662,238 +32928,12 @@
rect 319306 68378 319542 68614
rect 318986 68058 319222 68294
rect 319306 68058 319542 68294
-rect 192986 14378 193222 14614
-rect 193306 14378 193542 14614
-rect 192986 14058 193222 14294
-rect 193306 14058 193542 14294
-rect 174986 -7302 175222 -7066
-rect 175306 -7302 175542 -7066
-rect 174986 -7622 175222 -7386
-rect 175306 -7622 175542 -7386
-rect 199826 21218 200062 21454
-rect 200146 21218 200382 21454
-rect 199826 20898 200062 21134
-rect 200146 20898 200382 21134
-rect 199826 -1542 200062 -1306
-rect 200146 -1542 200382 -1306
-rect 199826 -1862 200062 -1626
-rect 200146 -1862 200382 -1626
-rect 203546 24938 203782 25174
-rect 203866 24938 204102 25174
-rect 203546 24618 203782 24854
-rect 203866 24618 204102 24854
-rect 203546 -3462 203782 -3226
-rect 203866 -3462 204102 -3226
-rect 203546 -3782 203782 -3546
-rect 203866 -3782 204102 -3546
-rect 207266 28658 207502 28894
-rect 207586 28658 207822 28894
-rect 207266 28338 207502 28574
-rect 207586 28338 207822 28574
-rect 207266 -5382 207502 -5146
-rect 207586 -5382 207822 -5146
-rect 207266 -5702 207502 -5466
-rect 207586 -5702 207822 -5466
-rect 210986 32378 211222 32614
-rect 211306 32378 211542 32614
-rect 210986 32058 211222 32294
-rect 211306 32058 211542 32294
-rect 192986 -6342 193222 -6106
-rect 193306 -6342 193542 -6106
-rect 192986 -6662 193222 -6426
-rect 193306 -6662 193542 -6426
-rect 217826 3218 218062 3454
-rect 218146 3218 218382 3454
-rect 217826 2898 218062 3134
-rect 218146 2898 218382 3134
-rect 217826 -582 218062 -346
-rect 218146 -582 218382 -346
-rect 217826 -902 218062 -666
-rect 218146 -902 218382 -666
-rect 221546 6938 221782 7174
-rect 221866 6938 222102 7174
-rect 221546 6618 221782 6854
-rect 221866 6618 222102 6854
-rect 221546 -2502 221782 -2266
-rect 221866 -2502 222102 -2266
-rect 221546 -2822 221782 -2586
-rect 221866 -2822 222102 -2586
-rect 225266 10658 225502 10894
-rect 225586 10658 225822 10894
-rect 225266 10338 225502 10574
-rect 225586 10338 225822 10574
-rect 225266 -4422 225502 -4186
-rect 225586 -4422 225822 -4186
-rect 225266 -4742 225502 -4506
-rect 225586 -4742 225822 -4506
-rect 228986 14378 229222 14614
-rect 229306 14378 229542 14614
-rect 228986 14058 229222 14294
-rect 229306 14058 229542 14294
-rect 210986 -7302 211222 -7066
-rect 211306 -7302 211542 -7066
-rect 210986 -7622 211222 -7386
-rect 211306 -7622 211542 -7386
-rect 235826 21218 236062 21454
-rect 236146 21218 236382 21454
-rect 235826 20898 236062 21134
-rect 236146 20898 236382 21134
-rect 235826 -1542 236062 -1306
-rect 236146 -1542 236382 -1306
-rect 235826 -1862 236062 -1626
-rect 236146 -1862 236382 -1626
-rect 239546 24938 239782 25174
-rect 239866 24938 240102 25174
-rect 239546 24618 239782 24854
-rect 239866 24618 240102 24854
-rect 239546 -3462 239782 -3226
-rect 239866 -3462 240102 -3226
-rect 239546 -3782 239782 -3546
-rect 239866 -3782 240102 -3546
-rect 243266 28658 243502 28894
-rect 243586 28658 243822 28894
-rect 243266 28338 243502 28574
-rect 243586 28338 243822 28574
-rect 243266 -5382 243502 -5146
-rect 243586 -5382 243822 -5146
-rect 243266 -5702 243502 -5466
-rect 243586 -5702 243822 -5466
-rect 246986 32378 247222 32614
-rect 247306 32378 247542 32614
-rect 246986 32058 247222 32294
-rect 247306 32058 247542 32294
-rect 228986 -6342 229222 -6106
-rect 229306 -6342 229542 -6106
-rect 228986 -6662 229222 -6426
-rect 229306 -6662 229542 -6426
-rect 253826 3218 254062 3454
-rect 254146 3218 254382 3454
-rect 253826 2898 254062 3134
-rect 254146 2898 254382 3134
-rect 253826 -582 254062 -346
-rect 254146 -582 254382 -346
-rect 253826 -902 254062 -666
-rect 254146 -902 254382 -666
-rect 257546 6938 257782 7174
-rect 257866 6938 258102 7174
-rect 257546 6618 257782 6854
-rect 257866 6618 258102 6854
-rect 257546 -2502 257782 -2266
-rect 257866 -2502 258102 -2266
-rect 257546 -2822 257782 -2586
-rect 257866 -2822 258102 -2586
-rect 261266 10658 261502 10894
-rect 261586 10658 261822 10894
-rect 261266 10338 261502 10574
-rect 261586 10338 261822 10574
-rect 261266 -4422 261502 -4186
-rect 261586 -4422 261822 -4186
-rect 261266 -4742 261502 -4506
-rect 261586 -4742 261822 -4506
-rect 264986 14378 265222 14614
-rect 265306 14378 265542 14614
-rect 264986 14058 265222 14294
-rect 265306 14058 265542 14294
-rect 246986 -7302 247222 -7066
-rect 247306 -7302 247542 -7066
-rect 246986 -7622 247222 -7386
-rect 247306 -7622 247542 -7386
-rect 271826 21218 272062 21454
-rect 272146 21218 272382 21454
-rect 271826 20898 272062 21134
-rect 272146 20898 272382 21134
-rect 271826 -1542 272062 -1306
-rect 272146 -1542 272382 -1306
-rect 271826 -1862 272062 -1626
-rect 272146 -1862 272382 -1626
-rect 275546 24938 275782 25174
-rect 275866 24938 276102 25174
-rect 275546 24618 275782 24854
-rect 275866 24618 276102 24854
-rect 275546 -3462 275782 -3226
-rect 275866 -3462 276102 -3226
-rect 275546 -3782 275782 -3546
-rect 275866 -3782 276102 -3546
-rect 279266 28658 279502 28894
-rect 279586 28658 279822 28894
-rect 279266 28338 279502 28574
-rect 279586 28338 279822 28574
-rect 279266 -5382 279502 -5146
-rect 279586 -5382 279822 -5146
-rect 279266 -5702 279502 -5466
-rect 279586 -5702 279822 -5466
-rect 282986 32378 283222 32614
-rect 283306 32378 283542 32614
-rect 282986 32058 283222 32294
-rect 283306 32058 283542 32294
-rect 264986 -6342 265222 -6106
-rect 265306 -6342 265542 -6106
-rect 264986 -6662 265222 -6426
-rect 265306 -6662 265542 -6426
-rect 289826 3218 290062 3454
-rect 290146 3218 290382 3454
-rect 289826 2898 290062 3134
-rect 290146 2898 290382 3134
-rect 289826 -582 290062 -346
-rect 290146 -582 290382 -346
-rect 289826 -902 290062 -666
-rect 290146 -902 290382 -666
-rect 293546 6938 293782 7174
-rect 293866 6938 294102 7174
-rect 293546 6618 293782 6854
-rect 293866 6618 294102 6854
-rect 293546 -2502 293782 -2266
-rect 293866 -2502 294102 -2266
-rect 293546 -2822 293782 -2586
-rect 293866 -2822 294102 -2586
-rect 297266 10658 297502 10894
-rect 297586 10658 297822 10894
-rect 297266 10338 297502 10574
-rect 297586 10338 297822 10574
-rect 297266 -4422 297502 -4186
-rect 297586 -4422 297822 -4186
-rect 297266 -4742 297502 -4506
-rect 297586 -4742 297822 -4506
-rect 300986 14378 301222 14614
-rect 301306 14378 301542 14614
-rect 300986 14058 301222 14294
-rect 301306 14058 301542 14294
-rect 282986 -7302 283222 -7066
-rect 283306 -7302 283542 -7066
-rect 282986 -7622 283222 -7386
-rect 283306 -7622 283542 -7386
-rect 307826 21218 308062 21454
-rect 308146 21218 308382 21454
-rect 307826 20898 308062 21134
-rect 308146 20898 308382 21134
-rect 307826 -1542 308062 -1306
-rect 308146 -1542 308382 -1306
-rect 307826 -1862 308062 -1626
-rect 308146 -1862 308382 -1626
-rect 311546 24938 311782 25174
-rect 311866 24938 312102 25174
-rect 311546 24618 311782 24854
-rect 311866 24618 312102 24854
-rect 311546 -3462 311782 -3226
-rect 311866 -3462 312102 -3226
-rect 311546 -3782 311782 -3546
-rect 311866 -3782 312102 -3546
-rect 315266 28658 315502 28894
-rect 315586 28658 315822 28894
-rect 315266 28338 315502 28574
-rect 315586 28338 315822 28574
-rect 315266 -5382 315502 -5146
-rect 315586 -5382 315822 -5146
-rect 315266 -5702 315502 -5466
-rect 315586 -5702 315822 -5466
rect 342490 597218 342726 597454
rect 342490 596898 342726 597134
rect 373210 597218 373446 597454
rect 373210 596898 373446 597134
rect 403930 597218 404166 597454
rect 403930 596898 404166 597134
-rect 434650 597218 434886 597454
-rect 434650 596898 434886 597134
rect 327130 579218 327366 579454
rect 327130 578898 327366 579134
rect 357850 579218 358086 579454
@@ -32902,16 +32942,12 @@
rect 388570 578898 388806 579134
rect 419290 579218 419526 579454
rect 419290 578898 419526 579134
-rect 450010 579218 450246 579454
-rect 450010 578898 450246 579134
rect 342490 561218 342726 561454
rect 342490 560898 342726 561134
rect 373210 561218 373446 561454
rect 373210 560898 373446 561134
rect 403930 561218 404166 561454
rect 403930 560898 404166 561134
-rect 434650 561218 434886 561454
-rect 434650 560898 434886 561134
rect 327130 543218 327366 543454
rect 327130 542898 327366 543134
rect 357850 543218 358086 543454
@@ -32920,16 +32956,12 @@
rect 388570 542898 388806 543134
rect 419290 543218 419526 543454
rect 419290 542898 419526 543134
-rect 450010 543218 450246 543454
-rect 450010 542898 450246 543134
rect 342490 525218 342726 525454
rect 342490 524898 342726 525134
rect 373210 525218 373446 525454
rect 373210 524898 373446 525134
rect 403930 525218 404166 525454
rect 403930 524898 404166 525134
-rect 434650 525218 434886 525454
-rect 434650 524898 434886 525134
rect 327130 507218 327366 507454
rect 327130 506898 327366 507134
rect 357850 507218 358086 507454
@@ -32938,16 +32970,12 @@
rect 388570 506898 388806 507134
rect 419290 507218 419526 507454
rect 419290 506898 419526 507134
-rect 450010 507218 450246 507454
-rect 450010 506898 450246 507134
rect 342490 489218 342726 489454
rect 342490 488898 342726 489134
rect 373210 489218 373446 489454
rect 373210 488898 373446 489134
rect 403930 489218 404166 489454
rect 403930 488898 404166 489134
-rect 434650 489218 434886 489454
-rect 434650 488898 434886 489134
rect 327130 471218 327366 471454
rect 327130 470898 327366 471134
rect 357850 471218 358086 471454
@@ -32956,16 +32984,12 @@
rect 388570 470898 388806 471134
rect 419290 471218 419526 471454
rect 419290 470898 419526 471134
-rect 450010 471218 450246 471454
-rect 450010 470898 450246 471134
rect 342490 453218 342726 453454
rect 342490 452898 342726 453134
rect 373210 453218 373446 453454
rect 373210 452898 373446 453134
rect 403930 453218 404166 453454
rect 403930 452898 404166 453134
-rect 434650 453218 434886 453454
-rect 434650 452898 434886 453134
rect 327130 435218 327366 435454
rect 327130 434898 327366 435134
rect 357850 435218 358086 435454
@@ -32974,16 +32998,12 @@
rect 388570 434898 388806 435134
rect 419290 435218 419526 435454
rect 419290 434898 419526 435134
-rect 450010 435218 450246 435454
-rect 450010 434898 450246 435134
rect 342490 417218 342726 417454
rect 342490 416898 342726 417134
rect 373210 417218 373446 417454
rect 373210 416898 373446 417134
rect 403930 417218 404166 417454
rect 403930 416898 404166 417134
-rect 434650 417218 434886 417454
-rect 434650 416898 434886 417134
rect 327130 399218 327366 399454
rect 327130 398898 327366 399134
rect 357850 399218 358086 399454
@@ -32992,16 +33012,12 @@
rect 388570 398898 388806 399134
rect 419290 399218 419526 399454
rect 419290 398898 419526 399134
-rect 450010 399218 450246 399454
-rect 450010 398898 450246 399134
rect 342490 381218 342726 381454
rect 342490 380898 342726 381134
rect 373210 381218 373446 381454
rect 373210 380898 373446 381134
rect 403930 381218 404166 381454
rect 403930 380898 404166 381134
-rect 434650 381218 434886 381454
-rect 434650 380898 434886 381134
rect 327130 363218 327366 363454
rect 327130 362898 327366 363134
rect 357850 363218 358086 363454
@@ -33010,16 +33026,12 @@
rect 388570 362898 388806 363134
rect 419290 363218 419526 363454
rect 419290 362898 419526 363134
-rect 450010 363218 450246 363454
-rect 450010 362898 450246 363134
rect 342490 345218 342726 345454
rect 342490 344898 342726 345134
rect 373210 345218 373446 345454
rect 373210 344898 373446 345134
rect 403930 345218 404166 345454
rect 403930 344898 404166 345134
-rect 434650 345218 434886 345454
-rect 434650 344898 434886 345134
rect 327130 327218 327366 327454
rect 327130 326898 327366 327134
rect 357850 327218 358086 327454
@@ -33028,16 +33040,12 @@
rect 388570 326898 388806 327134
rect 419290 327218 419526 327454
rect 419290 326898 419526 327134
-rect 450010 327218 450246 327454
-rect 450010 326898 450246 327134
rect 342490 309218 342726 309454
rect 342490 308898 342726 309134
rect 373210 309218 373446 309454
rect 373210 308898 373446 309134
rect 403930 309218 404166 309454
rect 403930 308898 404166 309134
-rect 434650 309218 434886 309454
-rect 434650 308898 434886 309134
rect 325826 291218 326062 291454
rect 326146 291218 326382 291454
rect 325826 290898 326062 291134
@@ -33070,6 +33078,10 @@
rect 319306 32378 319542 32614
rect 318986 32058 319222 32294
rect 319306 32058 319542 32294
+rect 315266 -5382 315502 -5146
+rect 315586 -5382 315822 -5146
+rect 315266 -5702 315502 -5466
+rect 315586 -5702 315822 -5466
rect 300986 -6342 301222 -6106
rect 301306 -6342 301542 -6106
rect 300986 -6662 301222 -6426
@@ -33858,10 +33870,6 @@
rect 419866 24938 420102 25174
rect 419546 24618 419782 24854
rect 419866 24618 420102 24854
-rect 419546 -3462 419782 -3226
-rect 419866 -3462 420102 -3226
-rect 419546 -3782 419782 -3546
-rect 419866 -3782 420102 -3546
rect 423266 280658 423502 280894
rect 423586 280658 423822 280894
rect 423266 280338 423502 280574
@@ -33890,14 +33898,40 @@
rect 423586 64658 423822 64894
rect 423266 64338 423502 64574
rect 423586 64338 423822 64574
-rect 423266 28658 423502 28894
-rect 423586 28658 423822 28894
-rect 423266 28338 423502 28574
-rect 423586 28338 423822 28574
-rect 423266 -5382 423502 -5146
-rect 423586 -5382 423822 -5146
-rect 423266 -5702 423502 -5466
-rect 423586 -5702 423822 -5466
+rect 434650 597218 434886 597454
+rect 434650 596898 434886 597134
+rect 450010 579218 450246 579454
+rect 450010 578898 450246 579134
+rect 434650 561218 434886 561454
+rect 434650 560898 434886 561134
+rect 450010 543218 450246 543454
+rect 450010 542898 450246 543134
+rect 434650 525218 434886 525454
+rect 434650 524898 434886 525134
+rect 450010 507218 450246 507454
+rect 450010 506898 450246 507134
+rect 434650 489218 434886 489454
+rect 434650 488898 434886 489134
+rect 450010 471218 450246 471454
+rect 450010 470898 450246 471134
+rect 434650 453218 434886 453454
+rect 434650 452898 434886 453134
+rect 450010 435218 450246 435454
+rect 450010 434898 450246 435134
+rect 434650 417218 434886 417454
+rect 434650 416898 434886 417134
+rect 450010 399218 450246 399454
+rect 450010 398898 450246 399134
+rect 434650 381218 434886 381454
+rect 434650 380898 434886 381134
+rect 450010 363218 450246 363454
+rect 450010 362898 450246 363134
+rect 434650 345218 434886 345454
+rect 434650 344898 434886 345134
+rect 450010 327218 450246 327454
+rect 450010 326898 450246 327134
+rect 434650 309218 434886 309454
+rect 434650 308898 434886 309134
rect 426986 284378 427222 284614
rect 427306 284378 427542 284614
rect 426986 284058 427222 284294
@@ -33926,6 +33960,18 @@
rect 427306 68378 427542 68614
rect 426986 68058 427222 68294
rect 427306 68058 427542 68294
+rect 423266 28658 423502 28894
+rect 423586 28658 423822 28894
+rect 423266 28338 423502 28574
+rect 423586 28338 423822 28574
+rect 419546 -3462 419782 -3226
+rect 419866 -3462 420102 -3226
+rect 419546 -3782 419782 -3546
+rect 419866 -3782 420102 -3546
+rect 423266 -5382 423502 -5146
+rect 423586 -5382 423822 -5146
+rect 423266 -5702 423502 -5466
+rect 423586 -5702 423822 -5466
rect 426986 32378 427222 32614
rect 427306 32378 427542 32614
rect 426986 32058 427222 32294
@@ -48028,11 +48074,11 @@
rect 592618 -7622 592650 -7386
rect -8726 -7654 592650 -7622
use user_proj_example mprj
-timestamp 1636003697
+timestamp 1636199702
transform 1 0 200000 0 1 300000
box 0 0 300000 300000
use sram_32_256_sky130A mem
-timestamp 1636003697
+timestamp 1636199702
transform 1 0 200000 0 1 40000
box 0 0 115676 71068
<< labels >>
diff --git a/maglef/user_proj_example.mag b/maglef/user_proj_example.mag
index 3fbfba5..e775690 100644
--- a/maglef/user_proj_example.mag
+++ b/maglef/user_proj_example.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1635995321
+timestamp 1636138118
<< obsli1 >>
rect 1104 2159 298816 297585
<< obsm1 >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index 3b91305..7eb69ac 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,11 +1,11 @@
magic
tech sky130A
magscale 1 2
-timestamp 1636003760
+timestamp 1636199764
<< obsli1 >>
-rect 201104 40341 498816 597585
+rect 201104 2873 498816 597585
<< obsm1 >>
-rect 566 2796 503042 602268
+rect 566 2864 503042 602064
<< metal2 >>
rect 8086 703520 8198 704960
rect 24278 703520 24390 704960
@@ -539,431 +539,431 @@
rect 583362 -960 583474 480
<< obsm2 >>
rect 572 536 503038 602313
-rect 710 480 1590 536
-rect 1814 480 2786 536
-rect 3010 480 3982 536
-rect 4206 480 5178 536
-rect 5402 480 6374 536
-rect 6598 480 7570 536
-rect 7794 480 8674 536
-rect 8898 480 9870 536
-rect 10094 480 11066 536
-rect 11290 480 12262 536
-rect 12486 480 13458 536
-rect 13682 480 14654 536
-rect 14878 480 15850 536
-rect 16074 480 16954 536
-rect 17178 480 18150 536
-rect 18374 480 19346 536
-rect 19570 480 20542 536
-rect 20766 480 21738 536
-rect 21962 480 22934 536
-rect 23158 480 24130 536
-rect 24354 480 25234 536
-rect 25458 480 26430 536
-rect 26654 480 27626 536
-rect 27850 480 28822 536
-rect 29046 480 30018 536
-rect 30242 480 31214 536
-rect 31438 480 32318 536
-rect 32542 480 33514 536
-rect 33738 480 34710 536
-rect 34934 480 35906 536
-rect 36130 480 37102 536
-rect 37326 480 38298 536
-rect 38522 480 39494 536
-rect 39718 480 40598 536
-rect 40822 480 41794 536
-rect 42018 480 42990 536
-rect 43214 480 44186 536
-rect 44410 480 45382 536
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<< metal3 >>
rect -960 697220 480 697460
rect 583520 697084 584960 697324
@@ -1073,7 +1073,7 @@
rect 583520 19668 584960 19908
rect 583520 6476 584960 6716
<< obsm3 >>
-rect 9949 3299 503043 602309
+rect 197997 3299 503043 602309
<< metal4 >>
rect -8726 -7654 -8106 711590
rect -7766 -6694 -7146 710630
@@ -1412,47 +1412,74 @@
rect 308494 112988 311434 298080
rect 312214 112988 315154 298080
rect 315934 112988 318874 298080
-rect 200272 38523 318874 112988
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+rect 200272 38080 318874 112988
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<< metal5 >>
rect -8726 710970 592650 711590
rect -7766 710010 591690 710630
@@ -3732,7 +3759,7 @@
string FIXED_BBOX 0 0 584000 704000
string LEFview TRUE
string GDS_FILE /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/magic/user_project_wrapper.gds
-string GDS_END 71540146
+string GDS_END 71541042
string GDS_START 70505550
<< end >>
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 71545ce..580d926 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -26,7 +26,7 @@
$script_dir/../../verilog/rtl/clk_gate.v \
$script_dir/../../verilog/rtl/rvmyth.v"
set ::env(VERILOG_INCLUDE_DIRS) "\
- $script_dir/../../verilog/include"
+ $script_dir/../../verilog/rtl/include"
set ::env(DESIGN_IS_CORE) 0
diff --git a/signoff/user_proj_example/final_summary_report.csv b/signoff/user_proj_example/final_summary_report.csv
index 3a995d1..9fdfbff 100644
--- a/signoff/user_proj_example/final_summary_report.csv
+++ b/signoff/user_proj_example/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,flow_completed,0h55m31s,-1,10616.0,2.25,5308.0,5.6,1606.75,11943,0,0,0,0,0,0,0,17,0,0,-1,865563,136959,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,613459023.0,0.1,10.22,8.84,0.12,0.2,-1,9113,11620,311,2818,0,0,0,11242,0,0,0,0,0,0,0,4,2161,2532,23,1086,31337,0,32423,19.607843137254903,51,50,AREA 0,5,50,1,153.6,153.18,0.2,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,flow_completed,1h11m38s,-1,10616.0,2.25,5308.0,5.6,1606.68,11943,0,0,0,0,0,0,0,17,0,0,-1,865563,136959,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,613459023.0,0.1,10.22,8.84,0.12,0.2,-1,9113,11620,311,2818,0,0,0,11242,0,0,0,0,0,0,0,4,2161,2532,23,1086,31337,0,32423,19.607843137254903,51,50,AREA 0,5,50,1,153.6,153.18,0.2,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 7882249..dc6eddc 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h21m23s,-1,0.38916562889165623,10.2784,0.19458281444582812,-1,495.0,2,0,0,0,0,0,0,0,0,0,-1,-1,231408,495,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,0.36,0.64,0.11,0.3,-1,30,686,30,686,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,19.607843137254903,51,50,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h21m16s,-1,0.38916562889165623,10.2784,0.19458281444582812,-1,494.03,2,0,0,0,0,0,0,0,0,0,-1,-1,192116,500,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,0.22,0.61,0.05,0.37,-1,31,687,31,687,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,19.607843137254903,51,50,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/spi/lvs/user_project_wrapper.spice b/spi/lvs/user_project_wrapper.spice
index 0a94a4f..1f51158 100644
--- a/spi/lvs/user_project_wrapper.spice
+++ b/spi/lvs/user_project_wrapper.spice
@@ -126,28 +126,29 @@
+ wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3]
+ wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0]
+ wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
-Xmprj wb_clk_i wbs_dat_o[0] wbs_dat_o[1] wbs_dat_o[2] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5]
-+ wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] mem/dout0[0] mem/dout0[10] mem/dout0[11]
-+ mem/dout0[12] mem/dout0[13] mem/dout0[14] mem/dout0[15] mem/dout0[16] mem/dout0[17]
-+ mem/dout0[18] mem/dout0[19] mem/dout0[1] mem/dout0[20] mem/dout0[21] mem/dout0[22]
-+ mem/dout0[23] mem/dout0[24] mem/dout0[25] mem/dout0[26] mem/dout0[27] mem/dout0[28]
-+ mem/dout0[29] mem/dout0[2] mem/dout0[30] mem/dout0[31] mem/dout0[3] mem/dout0[4]
-+ mem/dout0[5] mem/dout0[6] mem/dout0[7] mem/dout0[8] mem/dout0[9] wbs_adr_i[0] wbs_adr_i[1]
-+ wbs_adr_i[2] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_sel_i[0]
-+ mem/addr0[0] mem/addr0[1] mem/addr0[2] mem/addr0[3] mem/addr0[4] mem/addr0[5] mem/addr0[6]
-+ mem/addr0[7] mem/web0 wb_rst_i vccd1 vssd1 user_proj_example
-Xmem mem/csb0 mem/web0 wb_clk_i wbs_dat_i[0] wbs_dat_i[1] wbs_dat_i[2] wbs_dat_i[3]
-+ wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_i[10]
-+ wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16]
-+ wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22]
-+ wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28]
-+ wbs_dat_i[29] wbs_dat_i[30] wbs_dat_i[31] mem/dout0[0] mem/dout0[1] mem/dout0[2]
-+ mem/dout0[3] mem/dout0[4] mem/dout0[5] mem/dout0[6] mem/dout0[7] mem/dout0[8] mem/dout0[9]
-+ mem/dout0[10] mem/dout0[11] mem/dout0[12] mem/dout0[13] mem/dout0[14] mem/dout0[15]
-+ mem/dout0[16] mem/dout0[17] mem/dout0[18] mem/dout0[19] mem/dout0[20] mem/dout0[21]
-+ mem/dout0[22] mem/dout0[23] mem/dout0[24] mem/dout0[25] mem/dout0[26] mem/dout0[27]
-+ mem/dout0[28] mem/dout0[29] mem/dout0[30] mem/dout0[31] mem/addr0[0] mem/addr0[1]
-+ mem/addr0[2] mem/addr0[3] mem/addr0[4] mem/addr0[5] mem/addr0[6] mem/addr0[7] vccd1
-+ vssd1 sram_32_256_sky130A
+Xmprj wb_clk_i la_data_out[64] la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68]
++ la_data_out[69] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73]
++ mem/dout0[0] mem/dout0[10] mem/dout0[11] mem/dout0[12] mem/dout0[13] mem/dout0[14]
++ mem/dout0[15] mem/dout0[16] mem/dout0[17] mem/dout0[18] mem/dout0[19] mem/dout0[1]
++ mem/dout0[20] mem/dout0[21] mem/dout0[22] mem/dout0[23] mem/dout0[24] mem/dout0[25]
++ mem/dout0[26] mem/dout0[27] mem/dout0[28] mem/dout0[29] mem/dout0[2] mem/dout0[30]
++ mem/dout0[31] mem/dout0[3] mem/dout0[4] mem/dout0[5] mem/dout0[6] mem/dout0[7] mem/dout0[8]
++ mem/dout0[9] la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48]
++ la_data_in[49] la_data_in[50] la_data_in[51] la_data_in[36] mem/addr0[0] mem/addr0[1]
++ mem/addr0[2] mem/addr0[3] mem/addr0[4] mem/addr0[5] mem/addr0[6] mem/addr0[7] mem/web0
++ la_data_in[32] vccd1 vssd1 user_proj_example
+Xmem la_data_in[40] mem/web0 wb_clk_i la_data_in[0] la_data_in[1] la_data_in[2] la_data_in[3]
++ la_data_in[4] la_data_in[5] la_data_in[6] la_data_in[7] la_data_in[8] la_data_in[9]
++ la_data_in[10] la_data_in[11] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15]
++ la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[30] la_data_in[31] mem/dout0[0] mem/dout0[1]
++ mem/dout0[2] mem/dout0[3] mem/dout0[4] mem/dout0[5] mem/dout0[6] mem/dout0[7] mem/dout0[8]
++ mem/dout0[9] mem/dout0[10] mem/dout0[11] mem/dout0[12] mem/dout0[13] mem/dout0[14]
++ mem/dout0[15] mem/dout0[16] mem/dout0[17] mem/dout0[18] mem/dout0[19] mem/dout0[20]
++ mem/dout0[21] mem/dout0[22] mem/dout0[23] mem/dout0[24] mem/dout0[25] mem/dout0[26]
++ mem/dout0[27] mem/dout0[28] mem/dout0[29] mem/dout0[30] mem/dout0[31] mem/addr0[0]
++ mem/addr0[1] mem/addr0[2] mem/addr0[3] mem/addr0[4] mem/addr0[5] mem/addr0[6] mem/addr0[7]
++ vccd1 vssd1 sram_32_256_sky130A
.ends
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index d87238f..42dec11 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
+PATTERNS = la_test
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile
deleted file mode 100644
index 5237a05..0000000
--- a/verilog/dv/io_ports/Makefile
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## PDK
-PDK_PATH = $(PDK_ROOT)/sky130A
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = io_ports
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
- iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
- $< -o $@
-else
- iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- $< -o $@
-endif
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
- ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
- $(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
- $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
- $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c
deleted file mode 100644
index 0b23571..0000000
--- a/verilog/dv/io_ports/io_ports.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-/*
- IO Test:
- - Configures MPRJ lower 8-IO pins as outputs
- - Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
-*/
-
-void main()
-{
- /*
- IO Control Registers
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
-
- Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-
-
- Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-
- */
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
- // Configure lower 8-IOs as user output
- // Observe counter value in the testbench
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
-}
-
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
deleted file mode 100644
index f7628bc..0000000
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ /dev/null
@@ -1,169 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-
-module io_ports_tb;
- reg clock;
- reg RSTB;
- reg CSB;
- reg power1, power2;
- reg power3, power4;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
-
- assign mprj_io_0 = mprj_io[7:0];
- // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
-
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
- // assign mprj_io[3] = 1'b1;
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("io_ports.vcd");
- $dumpvars(0, io_ports_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (25) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- // Observe Output pins [7:0]
- wait(mprj_io_0 == 8'h01);
- wait(mprj_io_0 == 8'h02);
- wait(mprj_io_0 == 8'h03);
- wait(mprj_io_0 == 8'h04);
- wait(mprj_io_0 == 8'h05);
- wait(mprj_io_0 == 8'h06);
- wait(mprj_io_0 == 8'h07);
- wait(mprj_io_0 == 8'h08);
- wait(mprj_io_0 == 8'h09);
- wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'hFF);
- wait(mprj_io_0 == 8'h00);
-
- `ifdef GL
- $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
- `else
- $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
- `endif
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #170000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- power3 <= 1'b0;
- power4 <= 1'b0;
- #100;
- power1 <= 1'b1;
- #100;
- power2 <= 1'b1;
- #100;
- power3 <= 1'b1;
- #100;
- power4 <= 1'b1;
- end
-
- always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire USER_VDD3V3 = power3;
- wire USER_VDD1V8 = power4;
- wire VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (USER_VDD3V3),
- .vdda2 (USER_VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (USER_VDD1V8),
- .vccd2 (USER_VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("io_ports.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/la_test/Makefile
similarity index 92%
rename from verilog/dv/wb_port/Makefile
rename to verilog/dv/la_test/Makefile
index 1c784c6..2f7b008 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/la_test/Makefile
@@ -28,6 +28,7 @@
## User Project Pointers
UPRJ_VERILOG_PATH ?= ../../../verilog
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_INCLUDE_PATH = $(UPRJ_RTL_PATH)/include
UPRJ_BEHAVIOURAL_MODELS = ../
## RISCV GCC
@@ -40,7 +41,7 @@
.SUFFIXES:
-PATTERN = wb_port
+PATTERN = la_test
all: ${PATTERN:=.vcd}
@@ -50,12 +51,12 @@
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_INCLUDE_PATH) \
$< -o $@
else
iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/la_test/la_test.c b/verilog/dv/la_test/la_test.c
new file mode 100644
index 0000000..a8d1a94
--- /dev/null
+++ b/verilog/dv/la_test/la_test.c
@@ -0,0 +1,157 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+ MPRJ LA Test:
+ - Sets MPRJ initial data through LA[31:0]
+ - Sets MPRJ clk through LA[32]
+ - Sets MPRJ rst through LA[36]
+ - Sets MPRJ initial write enable through LA[40]
+ - Sets MPRJ initial address through LA[51:44]
+ - Observes 10-bit result of the initial program (e.g. sum of 0 to 9) which will be written on r17 through LA[73:64]
+*/
+
+int clk = 0;
+
+int getIMemContent(int addr) {
+ return
+ addr == 0x0 ? 0b00000000000100000000010010010011 :
+ addr == 0x1 ? 0b00000010101100000000010100010011 :
+ addr == 0x2 ? 0b00000000000000000000010110010011 :
+ addr == 0x3 ? 0b00000000000000000000100010010011 :
+ addr == 0x4 ? 0b00000000101110001000100010110011 :
+ addr == 0x5 ? 0b00000000000101011000010110010011 :
+ addr == 0x6 ? 0b11111110101001011001110011100011 :
+ addr == 0x7 ? 0b00000000101110001000100010110011 :
+ addr == 0x8 ? 0b01000000101110001000100010110011 :
+ addr == 0x9 ? 0b01000000100101011000010110110011 :
+ addr == 0xA ? 0b11111110100101011001110011100011 :
+ addr == 0xB ? 0b01000000101110001000100010110011 :
+ addr == 0xC ? 0b11111110000000000000000011100011 :
+ 0b00000000000000000000000000000000 ;
+}
+
+void main()
+{
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+
+ // All GPIO pins are configured to be output
+ // Used to flad the start/end of a test
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Configure All LA probes
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0] => Output from the CPU
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32] => Output from the CPU
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] => Input to the CPU
+ reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96] => Input to the CPU
+
+ // Flag start of the test
+ reg_mprj_datal = 0xAB600000;
+
+ // [31: 0] => DAT_IN
+ reg_la0_data = 0x00000000;
+
+ // [ 3: 0] => RST // Active High
+ // [ 7: 4] => WEN // Active High
+ // [11: 8] => CSB // Active Low
+ // [19:12] => ADR
+ reg_la1_data = 0x00000000;
+
+ // Delay
+ for (int i = 0; i < 5; i++);
+
+ // IMem initiation
+ for (int i = 0; i < 13; i++) {
+ reg_la1_data = 0x00000011 | i << 12;
+ reg_la0_data =
+ i == 0x0 ? 0b00000000000100000000010010010011 :
+ i == 0x1 ? 0b00000010101100000000010100010011 :
+ i == 0x2 ? 0b00000000000000000000010110010011 :
+ i == 0x3 ? 0b00000000000000000000100010010011 :
+ i == 0x4 ? 0b00000000101110001000100010110011 :
+ i == 0x5 ? 0b00000000000101011000010110010011 :
+ i == 0x6 ? 0b11111110101001011001110011100011 :
+ i == 0x7 ? 0b00000000101110001000100010110011 :
+ i == 0x8 ? 0b01000000101110001000100010110011 :
+ i == 0x9 ? 0b01000000100101011000010110110011 :
+ i == 0xA ? 0b11111110100101011001110011100011 :
+ i == 0xB ? 0b01000000101110001000100010110011 :
+ i == 0xC ? 0b11111110000000000000000011100011 :
+ 0b00000000000000000000000000000000 ;
+ }
+
+ // Write enable signal de-assert and keep reset asserted
+ reg_la1_data = 0x00000001;
+ // Wait for a few clocks to propagate signals
+ for (int i = 0; i < 2; i++);
+ // Reset signal de-assert and RVMYTH starts
+ reg_la1_data = 0x00000000;
+ // Wait for the expected result
+ while ((reg_la2_data & 0x000003FF) != 0x2D);
+ // Test has been done successfully
+ reg_mprj_datal = 0xAB610000;
+}
+
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test/la_test_tb.v
similarity index 88%
rename from verilog/dv/la_test2/la_test2_tb.v
rename to verilog/dv/la_test/la_test_tb.v
index e09905e..2fd892d 100644
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ b/verilog/dv/la_test/la_test_tb.v
@@ -21,15 +21,15 @@
`include "caravel_netlists.v"
`include "spiflash.v"
-module la_test2_tb;
+module la_test_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
- wire gpio;
- wire [37:0] mprj_io;
+ wire gpio;
+ wire [37:0] mprj_io;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
@@ -42,11 +42,12 @@
end
initial begin
- $dumpfile("la_test2.vcd");
- $dumpvars(0, la_test2_tb);
+ $dumpfile("la_test.vcd");
+ $dumpvars(0, la_test_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (30) begin
+ // Clock preiod is 25ns => 60 * 1000 * 25 = 1,500,000ns (whole simulation time)
+ repeat (60) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
@@ -70,9 +71,9 @@
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
+ CSB <= 1'b1; // Force CSB high
#2000;
- RSTB <= 1'b1; // Release reset
+ RSTB <= 1'b1; // Release reset
#170000;
CSB = 1'b0; // CSB can be released
end
@@ -116,7 +117,7 @@
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
@@ -125,7 +126,7 @@
);
spiflash #(
- .FILENAME("la_test2.hex")
+ .FILENAME("la_test.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
deleted file mode 100644
index ba979f7..0000000
--- a/verilog/dv/la_test1/Makefile
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## PDK
-PDK_PATH = $(PDK_ROOT)/sky130A
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = la_test1
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
- iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
- $< -o $@
-else
- iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- $< -o $@
-endif
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
- ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
- $(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
- $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
- $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
deleted file mode 100644
index 220bdfe..0000000
--- a/verilog/dv/la_test1/la_test1.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-// --------------------------------------------------------
-
-/*
- MPRJ Logic Analyzer Test:
- - Observes counter value through LA probes [31:0]
- - Sets counter initial value through LA probes [63:32]
- - Flags when counter value exceeds 500 through the management SoC gpio
- - Outputs message to the UART when the test concludes successfuly
-*/
-
-void main()
-{
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
- // The upper GPIO pins are configured to be output
- // and accessble to the management SoC.
- // Used to flad the start/end of a test
- // The lower GPIO pins are configured to be output
- // and accessible to the user project. They show
- // the project count value, although this test is
- // designed to read the project count through the
- // logic analyzer probes.
- // I/O 6 is configured for the UART Tx line
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Set UART clock to 64 kbaud (enable before I/O configuration)
- reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Configure LA probes [31:0], [127:64] as inputs to the cpu
- // Configure LA probes [63:32] as outputs from the cpu
- reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB400000;
-
- // Set Counter value to zero through LA probes [63:32]
- reg_la1_data = 0x00000000;
-
- // Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
-
- while (1) {
- if (reg_la0_data > 0x1F4) {
- reg_mprj_datal = 0xAB410000;
- break;
- }
- }
- print("\n");
- print("Monitor: Test 2 Passed\n\n"); // Makes simulation very long!
- reg_mprj_datal = 0xAB510000;
-}
-
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
deleted file mode 100644
index 626e390..0000000
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module la_test1_tb;
- reg clock;
- reg RSTB;
- reg CSB;
-
- reg power1, power2;
-
- wire gpio;
- wire uart_tx;
- wire [37:0] mprj_io;
- wire [15:0] checkbits;
-
- assign checkbits = mprj_io[31:16];
- assign uart_tx = mprj_io[6];
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
- initial begin
- // $dumpfile("la_test1.vcd");
- // $dumpvars(0, la_test1_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (200) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test LA (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test LA (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'hAB40);
- $display("LA Test 1 started");
- wait(checkbits == 16'hAB41);
- wait(checkbits == 16'hAB51);
- #10000;
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #170000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD1V8;
- wire VDD3V3;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("la_test1.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
- // Testbench UART
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
deleted file mode 100644
index 0435500..0000000
--- a/verilog/dv/la_test2/Makefile
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## PDK
-PDK_PATH = $(PDK_ROOT)/sky130A
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = la_test2
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
- iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
- $< -o $@
-else
- iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- $< -o $@
-endif
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
- ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
- $(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
- $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
- $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c
deleted file mode 100644
index 5875432..0000000
--- a/verilog/dv/la_test2/la_test2.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-/*
- MPRJ LA Test:
- - Sets counter clk through LA[64]
- - Sets counter rst through LA[65]
- - Observes count value for five clk cycle through LA[31:0]
-*/
-
-int clk = 0;
-int i;
-
-void main()
-{
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
-
- // All GPIO pins are configured to be output
- // Used to flad the start/end of a test
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Configure All LA probes as inputs to the cpu
- reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB600000;
-
- // Configure LA[64] LA[65] as outputs from the cpu
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;
-
- // Set clk & reset to one
- reg_la2_data = 0x00000003;
-
- // DELAY
- for (i=0; i<5; i=i+1) {}
-
- // Toggle clk & de-assert reset
- for (i=0; i<11; i=i+1) {
- clk = !clk;
- reg_la2_data = 0x00000000 | clk;
- }
-
- if (reg_la0_data >= 0x05) {
- reg_mprj_datal = 0xAB610000;
- }
-
-}
-
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
deleted file mode 100644
index 3a73b99..0000000
--- a/verilog/dv/mprj_stimulus/Makefile
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## PDK
-PDK_PATH = $(PDK_ROOT)/sky130A
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = mprj_stimulus
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
- iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
- $< -o $@
-else
- iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- $< -o $@
-endif
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
- ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
- $(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
- $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
- $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
deleted file mode 100644
index e4d0a2d..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-
-// --------------------------------------------------------
-
-void main()
-{
- // The upper GPIO pins are configured to be output
- // and accessble to the management SoC.
- // Used to flag the start/end of a test
- // The lower GPIO pins are configured to be output
- // and accessible to the user project. They show
- // the project count value, although this test is
- // designed to read the project count through the
- // logic analyzer probes.
- // I/O 6 is configured for the UART Tx line
- uint32_t testval;
-
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2
-
- reg_mprj_datal = 0x00000000;
- reg_mprj_datah = 0x00000000;
-
- reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;;
- reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;;
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Set UART clock to 64 kbaud (enable before I/O configuration)
- reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- /* TEST: Recast channels 35 to 32 to allow input to user project */
- /* This is done locally only: Do not run reg_mprj_xfer! */
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Configure LA probes [31:0], [127:64] as inputs to the cpu
- // Configure LA probes [63:32] as outputs from the cpu
- reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB400000;
-
- // Set Counter value to zero through LA probes [63:32]
- reg_la1_data = 0x00000000;
-
- // Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
-
- reg_mprj_datal = 0xAB410000;
- reg_mprj_datah = 0x00000000;
-
- // Test ability to force data on channel 37
- // NOTE: Only the low 6 bits of reg_mprj_datah are meaningful
- reg_mprj_datah = 0xffffffca;
- reg_mprj_datah = 0x00000000;
- reg_mprj_datah = 0x0f0f0fc5;
- reg_mprj_datah = 0x00000000;
-
- // Test ability to read back data generated by the user project
- // on the "monitored" outputs. Read from the lower 16 bits and
- // copy the value to the upper 16 bits.
-
- testval = reg_mprj_datal;
- reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000;
-
- // Flag end of the test
- reg_mprj_datal = 0xAB510000;
-}
-
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
deleted file mode 100644
index 1409015..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype wire
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module mprj_stimulus_tb;
- // Signals declaration
- reg clock;
- reg RSTB;
- reg CSB;
- reg power1, power2;
- reg power3, power4;
-
- wire HIGH;
- wire LOW;
- wire TRI;
- assign HIGH = 1'b1;
- assign LOW = 1'b0;
- assign TRI = 1'bz;
-
- wire gpio;
- wire uart_tx;
- wire [37:0] mprj_io;
- wire [15:0] checkbits;
- wire [3:0] status;
-
- // Signals Assignment
- assign checkbits = mprj_io[31:16];
- assign status = mprj_io[35:32];
- assign uart_tx = mprj_io[6];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("mprj_stimulus.vcd");
- $dumpvars(0, mprj_stimulus_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (150) begin
- repeat (1000) @(posedge clock);
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'hAB40);
- $display("Monitor: mprj_stimulus test started");
- wait(status == 4'ha);
- wait(status == 4'h5);
- // Value 0009 reflects copying user-controlled outputs to memory and back
- // to management-controlled outputs.
- wait(checkbits == 16'h0009);
- wait(checkbits == 16'hAB51);
- $display("Monitor: mprj_stimulus test Passed");
- #10000;
- $finish;
- end
-
- // Reset Operation
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #170000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
-
- spiflash #(
- .FILENAME("mprj_stimulus.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
- // Testbench UART
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
deleted file mode 100644
index 425c115..0000000
--- a/verilog/dv/wb_port/wb_port.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-/*
- Wishbone Test:
- - Configures MPRJ lower 8-IO pins as outputs
- - Checks counter value through the wishbone port
-*/
-int i = 0;
-int clk = 0;
-
-void main()
-{
-
- /*
- IO Control Registers
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
- Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-
-
- Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
- */
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
-
- // Flag start of the test
- reg_mprj_datal = 0xAB600000;
-
- reg_mprj_slave = 0x00002710;
- if (reg_mprj_slave == 0x2752) {
- reg_mprj_datal = 0xAB610000;
- } else {
- reg_mprj_datal = 0xAB600000;
- }
-}
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
deleted file mode 100644
index b32f900..0000000
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-
-module wb_port_tb;
- reg clock;
- reg RSTB;
- reg CSB;
- reg power1, power2;
- reg power3, power4;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- wire [15:0] checkbits;
-
- assign checkbits = mprj_io[31:16];
-
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("wb_port.vcd");
- $dumpvars(0, wb_port_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (30) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- wait(checkbits == 16'h AB60);
- $display("Monitor: MPRJ-Logic WB Started");
- wait(checkbits == 16'h AB61);
- `ifdef GL
- $display("Monitor: Mega-Project WB (GL) Passed");
- `else
- $display("Monitor: Mega-Project WB (RTL) Passed");
- `endif
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #170000;
- CSB = 1'b0; // CSB can be released
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- power3 <= 1'b0;
- power4 <= 1'b0;
- #100;
- power1 <= 1'b1;
- #100;
- power2 <= 1'b1;
- #100;
- power3 <= 1'b1;
- #100;
- power4 <= 1'b1;
- end
-
- always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
- end
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire USER_VDD3V3 = power3;
- wire USER_VDD1V8 = power4;
- wire VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (USER_VDD3V3),
- .vdda2 (USER_VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (USER_VDD1V8),
- .vccd2 (USER_VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("wb_port.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
\ No newline at end of file
diff --git a/verilog/gl/clk_gate.v b/verilog/gl/clk_gate.v
deleted file mode 100644
index 6df5b7d..0000000
--- a/verilog/gl/clk_gate.v
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
-Copyright (c) 2015, Steven F. Hoover
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * The name of Steven F. Hoover
- may not be used to endorse or promote products derived from this software
- without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-`include "sp_verilog.vh"
-
-
-// Clock gate module used by SandPiper default project.
-
-module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override);
-
- assign gated_clk = free_clk;
-endmodule
diff --git a/verilog/gl/rvmyth.v b/verilog/gl/rvmyth.v
deleted file mode 100644
index 9e96890..0000000
--- a/verilog/gl/rvmyth.v
+++ /dev/null
@@ -1,269 +0,0 @@
-//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta
-`include "sp_verilog.vh" //_\SV
- // Included URL: "https://raw.githubusercontent.com/shivanishah269/risc-v-core/master/FPGA_Implementation/riscv_shell_lib.tlv"// Included URL: "https://raw.githubusercontent.com/stevehoover/warp-v_includes/2d6d36baa4d2bc62321f982f78c8fe1456641a43/risc-v_defs.tlv"
-
- module rvmyth (
- output reg [9:0] OUT,
- input CLK,
- input reset,
-
- output [7:0] imem_addr,
- input [31:0] imem_data
- );
-
- wire clk = CLK;
-
-`include "rvmyth_gen.v"
-generate //_\TLV
- //_|cpu
- //_@0
- assign CPU_reset_a0 = reset;
-
- //Fetch
- // Next PC
- assign CPU_pc_a0[31:0] = (CPU_reset_a1) ? 32'd0 :
- (CPU_valid_taken_br_a3) ? CPU_br_tgt_pc_a3 :
- (CPU_valid_load_a3) ? CPU_inc_pc_a3 :
- (CPU_valid_jump_a3 && CPU_is_jal_a3) ? CPU_br_tgt_pc_a3 :
- (CPU_valid_jump_a3 && CPU_is_jalr_a3) ? CPU_jalr_tgt_pc_a3 : CPU_inc_pc_a1;
-
- //_@1
- assign imem_addr = CPU_pc_a0[9:2];
- assign CPU_instr_a1[31:0] = imem_data;
- assign CPU_inc_pc_a1[31:0] = CPU_pc_a1 + 32'd4;
-
- // Decode
- assign CPU_is_i_instr_a1 = CPU_instr_a1[6:2] == 5'b00000 ||
- CPU_instr_a1[6:2] == 5'b00001 ||
- CPU_instr_a1[6:2] == 5'b00100 ||
- CPU_instr_a1[6:2] == 5'b00110 ||
- CPU_instr_a1[6:2] == 5'b11001;
- assign CPU_is_r_instr_a1 = CPU_instr_a1[6:2] == 5'b01011 ||
- CPU_instr_a1[6:2] == 5'b10100 ||
- CPU_instr_a1[6:2] == 5'b01100 ||
- CPU_instr_a1[6:2] == 5'b01101;
- assign CPU_is_b_instr_a1 = CPU_instr_a1[6:2] == 5'b11000;
- assign CPU_is_u_instr_a1 = CPU_instr_a1[6:2] == 5'b00101 ||
- CPU_instr_a1[6:2] == 5'b01101;
- assign CPU_is_s_instr_a1 = CPU_instr_a1[6:2] == 5'b01000 ||
- CPU_instr_a1[6:2] == 5'b01001;
- assign CPU_is_j_instr_a1 = CPU_instr_a1[6:2] == 5'b11011;
-
- assign CPU_imm_a1[31:0] = CPU_is_i_instr_a1 ? { {21{CPU_instr_a1[31]}} , CPU_instr_a1[30:20] } :
- CPU_is_s_instr_a1 ? { {21{CPU_instr_a1[31]}} , CPU_instr_a1[30:25] , CPU_instr_a1[11:8] , CPU_instr_a1[7] } :
- CPU_is_b_instr_a1 ? { {20{CPU_instr_a1[31]}} , CPU_instr_a1[7] , CPU_instr_a1[30:25] , CPU_instr_a1[11:8] , 1'b0} :
- CPU_is_u_instr_a1 ? { CPU_instr_a1[31:12] , 12'b0} :
- CPU_is_j_instr_a1 ? { {12{CPU_instr_a1[31]}} , CPU_instr_a1[19:12] , CPU_instr_a1[20] , CPU_instr_a1[30:21] , 1'b0} : 32'b0;
-
- assign CPU_rs2_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1;
- assign CPU_rs1_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1 || CPU_is_i_instr_a1;
- assign CPU_rd_valid_a1 = CPU_is_r_instr_a1 || CPU_is_i_instr_a1 || CPU_is_u_instr_a1 || CPU_is_j_instr_a1;
- assign CPU_funct3_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1 || CPU_is_i_instr_a1;
- assign CPU_funct7_valid_a1 = CPU_is_r_instr_a1;
-
- //_?$rs2_valid
- assign CPU_rs2_a1[4:0] = CPU_instr_a1[24:20];
- //_?$rs1_valid
- assign CPU_rs1_a1[4:0] = CPU_instr_a1[19:15];
- //_?$rd_valid
- assign CPU_rd_a1[4:0] = CPU_instr_a1[11:7];
- //_?$funct3_valid
- assign CPU_funct3_a1[2:0] = CPU_instr_a1[14:12];
- //_?$funct7_valid
- assign CPU_funct7_a1[6:0] = CPU_instr_a1[31:25];
-
- assign CPU_opcode_a1[6:0] = CPU_instr_a1[6:0];
-
- assign CPU_dec_bits_a1[10:0] = {CPU_funct7_a1[5],CPU_funct3_a1,CPU_opcode_a1};
-
- // Branch Instruction
- assign CPU_is_beq_a1 = CPU_dec_bits_a1[9:0] == 10'b000_1100011;
- assign CPU_is_bne_a1 = CPU_dec_bits_a1[9:0] == 10'b001_1100011;
- assign CPU_is_blt_a1 = CPU_dec_bits_a1[9:0] == 10'b100_1100011;
- assign CPU_is_bge_a1 = CPU_dec_bits_a1[9:0] == 10'b101_1100011;
- assign CPU_is_bltu_a1 = CPU_dec_bits_a1[9:0] == 10'b110_1100011;
- assign CPU_is_bgeu_a1 = CPU_dec_bits_a1[9:0] == 10'b111_1100011;
-
- // Arithmetic Instruction
- assign CPU_is_add_a1 = CPU_dec_bits_a1 == 11'b0_000_0110011;
- assign CPU_is_addi_a1 = CPU_dec_bits_a1[9:0] == 10'b000_0010011;
- assign CPU_is_or_a1 = CPU_dec_bits_a1 == 11'b0_110_0110011;
- assign CPU_is_ori_a1 = CPU_dec_bits_a1[9:0] == 10'b110_0010011;
- assign CPU_is_xor_a1 = CPU_dec_bits_a1 == 11'b0_100_0110011;
- assign CPU_is_xori_a1 = CPU_dec_bits_a1[9:0] == 10'b100_0010011;
- assign CPU_is_and_a1 = CPU_dec_bits_a1 == 11'b0_111_0110011;
- assign CPU_is_andi_a1 = CPU_dec_bits_a1[9:0] == 10'b111_0010011;
- assign CPU_is_sub_a1 = CPU_dec_bits_a1 == 11'b1_000_0110011;
- assign CPU_is_slti_a1 = CPU_dec_bits_a1[9:0] == 10'b010_0010011;
- assign CPU_is_sltiu_a1 = CPU_dec_bits_a1[9:0] == 10'b011_0010011;
- assign CPU_is_slli_a1 = CPU_dec_bits_a1 == 11'b0_001_0010011;
- assign CPU_is_srli_a1 = CPU_dec_bits_a1 == 11'b0_101_0010011;
- assign CPU_is_srai_a1 = CPU_dec_bits_a1 == 11'b1_101_0010011;
- assign CPU_is_sll_a1 = CPU_dec_bits_a1 == 11'b0_001_0110011;
- assign CPU_is_slt_a1 = CPU_dec_bits_a1 == 11'b0_010_0110011;
- assign CPU_is_sltu_a1 = CPU_dec_bits_a1 == 11'b0_011_0110011;
- assign CPU_is_srl_a1 = CPU_dec_bits_a1 == 11'b0_101_0110011;
- assign CPU_is_sra_a1 = CPU_dec_bits_a1 == 11'b1_101_0110011;
-
- // Load Instruction
- assign CPU_is_load_a1 = CPU_dec_bits_a1[6:0] == 7'b0000011;
-
- // Store Instruction
- assign CPU_is_sb_a1 = CPU_dec_bits_a1[9:0] == 10'b000_0100011;
- assign CPU_is_sh_a1 = CPU_dec_bits_a1[9:0] == 10'b001_0100011;
- assign CPU_is_sw_a1 = CPU_dec_bits_a1[9:0] == 10'b010_0100011;
-
- // Jump Instruction
- assign CPU_is_lui_a1 = CPU_dec_bits_a1[6:0] == 7'b0110111;
- assign CPU_is_auipc_a1 = CPU_dec_bits_a1[6:0] == 7'b0010111;
- assign CPU_is_jal_a1 = CPU_dec_bits_a1[6:0] == 7'b1101111;
- assign CPU_is_jalr_a1 = CPU_dec_bits_a1[9:0] == 10'b000_1100111;
-
- assign CPU_is_jump_a1 = CPU_is_jal_a1 || CPU_is_jalr_a1;
-
- //_@2
- // Register File Read
- assign CPU_rf_rd_en1_a2 = CPU_rs1_valid_a2;
- //_?$rf_rd_en1
- assign CPU_rf_rd_index1_a2[4:0] = CPU_rs1_a2[4:0];
-
- assign CPU_rf_rd_en2_a2 = CPU_rs2_valid_a2;
- //_?$rf_rd_en2
- assign CPU_rf_rd_index2_a2[4:0] = CPU_rs2_a2[4:0];
-
- // Branch Target PC
- assign CPU_br_tgt_pc_a2[31:0] = CPU_pc_a2 + CPU_imm_a2;
-
- // Jump Target PC
- assign CPU_jalr_tgt_pc_a2[31:0] = CPU_src1_value_a2 + CPU_imm_a2;
-
- // Input signals to ALU
- assign CPU_src1_value_a2[31:0] = ((CPU_rd_a3 == CPU_rs1_a2) && CPU_rf_wr_en_a3) ? CPU_result_a3 : CPU_rf_rd_data1_a2[31:0];
- assign CPU_src2_value_a2[31:0] = ((CPU_rd_a3 == CPU_rs2_a2) && CPU_rf_wr_en_a3) ? CPU_result_a3 : CPU_rf_rd_data2_a2[31:0];
-
- //_@3
-
- // ALU
- assign CPU_sltu_result_a3 = CPU_src1_value_a3 < CPU_src2_value_a3 ;
- assign CPU_sltiu_result_a3 = CPU_src1_value_a3 < CPU_imm_a3 ;
-
- assign CPU_result_a3[31:0] = CPU_is_addi_a3 ? CPU_src1_value_a3 + CPU_imm_a3 :
- CPU_is_add_a3 ? CPU_src1_value_a3 + CPU_src2_value_a3 :
- CPU_is_or_a3 ? CPU_src1_value_a3 | CPU_src2_value_a3 :
- CPU_is_ori_a3 ? CPU_src1_value_a3 | CPU_imm_a3 :
- CPU_is_xor_a3 ? CPU_src1_value_a3 ^ CPU_src2_value_a3 :
- CPU_is_xori_a3 ? CPU_src1_value_a3 ^ CPU_imm_a3 :
- CPU_is_and_a3 ? CPU_src1_value_a3 & CPU_src2_value_a3 :
- CPU_is_andi_a3 ? CPU_src1_value_a3 & CPU_imm_a3 :
- CPU_is_sub_a3 ? CPU_src1_value_a3 - CPU_src2_value_a3 :
- CPU_is_slti_a3 ? ((CPU_src1_value_a3[31] == CPU_imm_a3[31]) ? CPU_sltiu_result_a3 : {31'b0,CPU_src1_value_a3[31]}) :
- CPU_is_sltiu_a3 ? CPU_sltiu_result_a3 :
- CPU_is_slli_a3 ? CPU_src1_value_a3 << CPU_imm_a3[5:0] :
- CPU_is_srli_a3 ? CPU_src1_value_a3 >> CPU_imm_a3[5:0] :
- CPU_is_srai_a3 ? ({{32{CPU_src1_value_a3[31]}}, CPU_src1_value_a3} >> CPU_imm_a3[4:0]) :
- CPU_is_sll_a3 ? CPU_src1_value_a3 << CPU_src2_value_a3[4:0] :
- CPU_is_slt_a3 ? ((CPU_src1_value_a3[31] == CPU_src2_value_a3[31]) ? CPU_sltu_result_a3 : {31'b0,CPU_src1_value_a3[31]}) :
- CPU_is_sltu_a3 ? CPU_sltu_result_a3 :
- CPU_is_srl_a3 ? CPU_src1_value_a3 >> CPU_src2_value_a3[5:0] :
- CPU_is_sra_a3 ? ({{32{CPU_src1_value_a3[31]}}, CPU_src1_value_a3} >> CPU_src2_value_a3[4:0]) :
- CPU_is_lui_a3 ? ({CPU_imm_a3[31:12], 12'b0}) :
- CPU_is_auipc_a3 ? CPU_pc_a3 + CPU_imm_a3 :
- CPU_is_jal_a3 ? CPU_pc_a3 + 4 :
- CPU_is_jalr_a3 ? CPU_pc_a3 + 4 :
- (CPU_is_load_a3 || CPU_is_s_instr_a3) ? CPU_src1_value_a3 + CPU_imm_a3 : 32'bx;
-
- // Register File Write
- assign CPU_rf_wr_en_a3 = (CPU_rd_valid_a3 && CPU_valid_a3 && CPU_rd_a3 != 5'b0) || CPU_valid_load_a5;
- //_?$rf_wr_en
- assign CPU_rf_wr_index_a3[4:0] = !CPU_valid_a3 ? CPU_rd_a5[4:0] : CPU_rd_a3[4:0];
-
- assign CPU_rf_wr_data_a3[31:0] = !CPU_valid_a3 ? CPU_ld_data_a5[31:0] : CPU_result_a3[31:0];
-
- // Branch
- assign CPU_taken_br_a3 = CPU_is_beq_a3 ? (CPU_src1_value_a3 == CPU_src2_value_a3) :
- CPU_is_bne_a3 ? (CPU_src1_value_a3 != CPU_src2_value_a3) :
- CPU_is_blt_a3 ? ((CPU_src1_value_a3 < CPU_src2_value_a3) ^ (CPU_src1_value_a3[31] != CPU_src2_value_a3[31])) :
- CPU_is_bge_a3 ? ((CPU_src1_value_a3 >= CPU_src2_value_a3) ^ (CPU_src1_value_a3[31] != CPU_src2_value_a3[31])) :
- CPU_is_bltu_a3 ? (CPU_src1_value_a3 < CPU_src2_value_a3) :
- CPU_is_bgeu_a3 ? (CPU_src1_value_a3 >= CPU_src2_value_a3) : 1'b0;
-
- assign CPU_valid_taken_br_a3 = CPU_valid_a3 && CPU_taken_br_a3;
-
- // Load
- assign CPU_valid_load_a3 = CPU_valid_a3 && CPU_is_load_a3;
- assign CPU_valid_a3 = !(CPU_valid_taken_br_a4 || CPU_valid_taken_br_a5 || CPU_valid_load_a4 || CPU_valid_load_a5 || CPU_valid_jump_a4 || CPU_valid_jump_a5);
-
- // Jump
- assign CPU_valid_jump_a3 = CPU_valid_a3 && CPU_is_jump_a3;
-
- //_@4
- assign CPU_dmem_rd_en_a4 = CPU_valid_load_a4;
- assign CPU_dmem_wr_en_a4 = CPU_valid_a4 && CPU_is_s_instr_a4;
- assign CPU_dmem_addr_a4[3:0] = CPU_result_a4[5:2];
- assign CPU_dmem_wr_data_a4[31:0] = CPU_src2_value_a4[31:0];
-
- //_@5
- assign CPU_ld_data_a5[31:0] = CPU_dmem_rd_data_a5[31:0];
-
- // Note: Because of the magic we are using for visualisation, if visualisation is enabled below,
- // be sure to avoid having unassigned signals (which you might be using for random inputs)
- // other than those specifically expected in the labs. You'll get strange errors for these.
-
- `BOGUS_USE(CPU_is_beq_a5 CPU_is_bne_a5 CPU_is_blt_a5 CPU_is_bge_a5 CPU_is_bltu_a5 CPU_is_bgeu_a5)
- `BOGUS_USE(CPU_is_sb_a5 CPU_is_sh_a5 CPU_is_sw_a5)
- // Assert these to end simulation (before Makerchip cycle limit).
- /*SV_plus*/
- always @ (posedge CLK) begin
- OUT = CPU_Xreg_value_a5[17];
- end
-
- // Macro instantiations for:
- // o instruction memory
- // o register file
- // o data memory
- // o CPU visualization
- //_|cpu
- // m4+imem(@1) // Args: (read stage)
- //_\source /raw.githubusercontent.com/shivanishah269/riscvcore/master/FPGAImplementation/riscvshelllib.tlv 31 // Instantiated from rvmyth.tlv, 226 as: m4+rf(@2, @3)
- // Reg File
- //_@3
- for (xreg = 0; xreg <= 31; xreg=xreg+1) begin : L1_CPU_Xreg //_/xreg
-
- // For $wr.
- wire L1_wr_a3;
-
- assign L1_wr_a3 = CPU_rf_wr_en_a3 && (CPU_rf_wr_index_a3 != 5'b0) && (CPU_rf_wr_index_a3 == xreg);
- assign CPU_Xreg_value_a3[xreg][31:0] = CPU_reset_a3 ? xreg :
- L1_wr_a3 ? CPU_rf_wr_data_a3 :
- CPU_Xreg_value_a4[xreg][31:0];
- end
- //_@2
- //_?$rf_rd_en1
- assign CPU_rf_rd_data1_a2[31:0] = CPU_Xreg_value_a4[CPU_rf_rd_index1_a2];
- //_?$rf_rd_en2
- assign CPU_rf_rd_data2_a2[31:0] = CPU_Xreg_value_a4[CPU_rf_rd_index2_a2];
- `BOGUS_USE(CPU_rf_rd_data1_a2 CPU_rf_rd_data2_a2)
- //_\end_source // Args: (read stage, write stage) - if equal, no register bypass is required
- //_\source /raw.githubusercontent.com/shivanishah269/riscvcore/master/FPGAImplementation/riscvshelllib.tlv 48 // Instantiated from rvmyth.tlv, 227 as: m4+dmem(@4)
- // Data Memory
- //_@4
- for (dmem = 0; dmem <= 15; dmem=dmem+1) begin : L1_CPU_Dmem //_/dmem
-
- // For $wr.
- wire L1_wr_a4;
-
- assign L1_wr_a4 = CPU_dmem_wr_en_a4 && (CPU_dmem_addr_a4 == dmem);
- assign CPU_Dmem_value_a4[dmem][31:0] = CPU_reset_a4 ? dmem :
- L1_wr_a4 ? CPU_dmem_wr_data_a4 :
- CPU_Dmem_value_a5[dmem][31:0];
-
- end
- //_?$dmem_rd_en
- assign CPU_dmem_rd_data_a4[31:0] = CPU_Dmem_value_a5[CPU_dmem_addr_a4];
- //`BOGUS_USE($dmem_rd_data)
- //_\end_source // Args: (read/write stage)
-endgenerate
-
-//_\SV
-
- endmodule
diff --git a/verilog/gl/sram_32_256_sky130A.v b/verilog/gl/sram_32_256_sky130A.v
deleted file mode 100644
index d45d17e..0000000
--- a/verilog/gl/sram_32_256_sky130A.v
+++ /dev/null
@@ -1,72 +0,0 @@
-// OpenRAM SRAM model
-// Words: 256
-// Word size: 32
-
-module sram_32_256_sky130A(
-`ifdef USE_POWER_PINS
- vccd1,
- vssd1,
-`endif
-// Port 0: RW
- clk0,csb0,web0,addr0,din0,dout0
- );
-
- parameter DATA_WIDTH = 32 ;
- parameter ADDR_WIDTH = 8 ;
- parameter RAM_DEPTH = 1 << ADDR_WIDTH;
- // FIXME: This delay is arbitrary.
- parameter DELAY = 3 ;
- parameter VERBOSE = 1 ; //Set to 0 to only display warnings
- parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
-
-`ifdef USE_POWER_PINS
- inout vccd1;
- inout vssd1;
-`endif
- input clk0; // clock
- input csb0; // active low chip select
- input web0; // active low write control
- input [ADDR_WIDTH-1:0] addr0;
- input [DATA_WIDTH-1:0] din0;
- output [DATA_WIDTH-1:0] dout0;
-
- reg csb0_reg;
- reg web0_reg;
- reg [ADDR_WIDTH-1:0] addr0_reg;
- reg [DATA_WIDTH-1:0] din0_reg;
- reg [DATA_WIDTH-1:0] dout0;
-
- // All inputs are registers
- always @(posedge clk0)
- begin
- csb0_reg = csb0;
- web0_reg = web0;
- addr0_reg = addr0;
- din0_reg = din0;
- #(T_HOLD) dout0 = 32'bx;
- if ( !csb0_reg && web0_reg && VERBOSE )
- $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
- if ( !csb0_reg && !web0_reg && VERBOSE )
- $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
- end
-
-reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
- // Memory Write Block Port 0
- // Write Operation : When web0 = 0, csb0 = 0
- always @ (negedge clk0)
- begin : MEM_WRITE0
- if ( !csb0_reg && !web0_reg ) begin
- mem[addr0_reg][31:0] = din0_reg[31:0];
- end
- end
-
- // Memory Read Block Port 0
- // Read Operation : When web0 = 1, csb0 = 0
- always @ (negedge clk0)
- begin : MEM_READ0
- if (!csb0_reg && web0_reg)
- dout0 <= #(DELAY) mem[addr0_reg];
- end
-
-endmodule
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 427a612..32231cf 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -94,9 +94,8 @@
wire \mem_addr[6] ;
wire \mem_addr[7] ;
wire mem_wr;
- wire zero_;
- sram_32_256_sky130A mem (.csb0(zero_),
+ sram_32_256_sky130A mem (.csb0(la_data_in[40]),
.web0(mem_wr),
.clk0(wb_clk_i),
.vccd1(vccd1),
@@ -109,38 +108,38 @@
\mem_addr[2] ,
\mem_addr[1] ,
\mem_addr[0] }),
- .din0({wbs_dat_i[31],
- wbs_dat_i[30],
- wbs_dat_i[29],
- wbs_dat_i[28],
- wbs_dat_i[27],
- wbs_dat_i[26],
- wbs_dat_i[25],
- wbs_dat_i[24],
- wbs_dat_i[23],
- wbs_dat_i[22],
- wbs_dat_i[21],
- wbs_dat_i[20],
- wbs_dat_i[19],
- wbs_dat_i[18],
- wbs_dat_i[17],
- wbs_dat_i[16],
- wbs_dat_i[15],
- wbs_dat_i[14],
- wbs_dat_i[13],
- wbs_dat_i[12],
- wbs_dat_i[11],
- wbs_dat_i[10],
- wbs_dat_i[9],
- wbs_dat_i[8],
- wbs_dat_i[7],
- wbs_dat_i[6],
- wbs_dat_i[5],
- wbs_dat_i[4],
- wbs_dat_i[3],
- wbs_dat_i[2],
- wbs_dat_i[1],
- wbs_dat_i[0]}),
+ .din0({la_data_in[31],
+ la_data_in[30],
+ la_data_in[29],
+ la_data_in[28],
+ la_data_in[27],
+ la_data_in[26],
+ la_data_in[25],
+ la_data_in[24],
+ la_data_in[23],
+ la_data_in[22],
+ la_data_in[21],
+ la_data_in[20],
+ la_data_in[19],
+ la_data_in[18],
+ la_data_in[17],
+ la_data_in[16],
+ la_data_in[15],
+ la_data_in[14],
+ la_data_in[13],
+ la_data_in[12],
+ la_data_in[11],
+ la_data_in[10],
+ la_data_in[9],
+ la_data_in[8],
+ la_data_in[7],
+ la_data_in[6],
+ la_data_in[5],
+ la_data_in[4],
+ la_data_in[3],
+ la_data_in[2],
+ la_data_in[1],
+ la_data_in[0]}),
.dout0({\imem_data[31] ,
\imem_data[30] ,
\imem_data[29] ,
@@ -174,21 +173,21 @@
\imem_data[1] ,
\imem_data[0] }));
user_proj_example mprj (.CLK(wb_clk_i),
- .init_en(wbs_sel_i[0]),
+ .init_en(la_data_in[36]),
.mem_wr(mem_wr),
- .reset(wb_rst_i),
+ .reset(la_data_in[32]),
.vccd1(vccd1),
.vssd1(vssd1),
- .OUT({wbs_dat_o[9],
- wbs_dat_o[8],
- wbs_dat_o[7],
- wbs_dat_o[6],
- wbs_dat_o[5],
- wbs_dat_o[4],
- wbs_dat_o[3],
- wbs_dat_o[2],
- wbs_dat_o[1],
- wbs_dat_o[0]}),
+ .OUT({la_data_out[73],
+ la_data_out[72],
+ la_data_out[71],
+ la_data_out[70],
+ la_data_out[69],
+ la_data_out[68],
+ la_data_out[67],
+ la_data_out[66],
+ la_data_out[65],
+ la_data_out[64]}),
.imem_data({\imem_data[31] ,
\imem_data[30] ,
\imem_data[29] ,
@@ -221,14 +220,14 @@
\imem_data[2] ,
\imem_data[1] ,
\imem_data[0] }),
- .init_addr({wbs_adr_i[7],
- wbs_adr_i[6],
- wbs_adr_i[5],
- wbs_adr_i[4],
- wbs_adr_i[3],
- wbs_adr_i[2],
- wbs_adr_i[1],
- wbs_adr_i[0]}),
+ .init_addr({la_data_in[51],
+ la_data_in[50],
+ la_data_in[49],
+ la_data_in[48],
+ la_data_in[47],
+ la_data_in[46],
+ la_data_in[45],
+ la_data_in[44]}),
.mem_addr({\mem_addr[7] ,
\mem_addr[6] ,
\mem_addr[5] ,
diff --git a/verilog/include/rvmyth_gen.v b/verilog/rtl/include/rvmyth_gen.v
similarity index 100%
rename from verilog/include/rvmyth_gen.v
rename to verilog/rtl/include/rvmyth_gen.v
diff --git a/verilog/include/sandpiper.vh b/verilog/rtl/include/sandpiper.vh
similarity index 100%
rename from verilog/include/sandpiper.vh
rename to verilog/rtl/include/sandpiper.vh
diff --git a/verilog/include/sandpiper_gen.vh b/verilog/rtl/include/sandpiper_gen.vh
similarity index 100%
rename from verilog/include/sandpiper_gen.vh
rename to verilog/rtl/include/sandpiper_gen.vh
diff --git a/verilog/include/sp_default.vh b/verilog/rtl/include/sp_default.vh
similarity index 100%
rename from verilog/include/sp_default.vh
rename to verilog/rtl/include/sp_default.vh
diff --git a/verilog/include/sp_verilog.vh b/verilog/rtl/include/sp_verilog.vh
similarity index 100%
rename from verilog/include/sp_verilog.vh
rename to verilog/rtl/include/sp_verilog.vh
diff --git a/verilog/rtl/sram_32_256_sky130A.v b/verilog/rtl/sram_32_256_sky130A.v
index d45d17e..0699ff6 100644
--- a/verilog/rtl/sram_32_256_sky130A.v
+++ b/verilog/rtl/sram_32_256_sky130A.v
@@ -16,7 +16,7 @@
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3 ;
- parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter VERBOSE = 0 ; //Set to 0 to only display warnings
parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..ea72bbe 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -22,7 +22,11 @@
`default_nettype wire
`include "gl/user_project_wrapper.v"
`include "gl/user_proj_example.v"
+ `include "sram_32_256_sky130A.v"
`else
`include "user_project_wrapper.v"
`include "user_proj_example.v"
+ `include "sram_32_256_sky130A.v"
+ `include "rvmyth.v"
+ `include "clk_gate.v"
`endif
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index c08f62d..f4e42e9 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -77,6 +77,8 @@
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
+ wire global_clk = wb_clk_i;
+
wire mem_wr;
wire [7:0] mem_addr;
@@ -87,14 +89,14 @@
.vccd1(vccd1), // User area 1 1.8V supply
.vssd1(vssd1), // User area 1 digital ground
`endif
- .OUT(wbs_dat_o[9:0]),
- .CLK(wb_clk_i),
- .reset(wb_rst_i),
+ .OUT(la_data_out[73:64]),
+ .CLK(global_clk),
+ .reset(la_data_in[32]),
.mem_wr(mem_wr),
.mem_addr(mem_addr),
- .init_en(wbs_sel_i[0]),
- .init_addr(wbs_adr_i[7:0]),
+ .init_en(la_data_in[36]),
+ .init_addr(la_data_in[51:44]),
.imem_data(imem_data)
);
@@ -103,11 +105,11 @@
.vccd1(vccd1), // User area 1 1.8V supply
.vssd1(vssd1), // User area 1 digital ground
`endif
- .clk0(wb_clk_i),
- .csb0(1'b0),
+ .clk0(global_clk),
+ .csb0(la_data_in[40]),
.web0(mem_wr),
.addr0(mem_addr),
- .din0(wbs_dat_i),
+ .din0(la_data_in[31:0]),
.dout0(imem_data)
);
