commit: 2a5295947df98d0e1c005acdf64446fa3d5765b7
[log] [tgz]
author: Manili <ma.nili@me.com>
Sat Nov 06 19:12:28 2021 +0330
committer: Manili <ma.nili@me.com>
Sat Nov 06 19:12:28 2021 +0330
tree: d181833760f60d6a408352085d489c86b2f9e356
parent: 2156bf6f2d3873270fb32e955905d764ead8e12d [diff]

simulation for LA ports added

def/user_project_wrapper.def[diff]
gds/sram_32_256_sky130A.gds[Deleted - diff]
gds/sram_32_256_sky130A.gds.gz[Added - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_proj_example.gds.gz[Added - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/user_project_wrapper.lef[diff]
mag/user_proj_example.mag[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj_example.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_proj_example/config.tcl[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/Makefile[diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test/Makefile[Renamed from verilog/dv/wb_port/Makefile - diff]
verilog/dv/la_test/la_test.c[Added - diff]
verilog/dv/la_test/la_test_tb.v[Renamed from verilog/dv/la_test2/la_test2_tb.v - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]
verilog/gl/clk_gate.v[Deleted - diff]
verilog/gl/rvmyth.v[Deleted - diff]
verilog/gl/sram_32_256_sky130A.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/include/rvmyth_gen.v[Renamed from verilog/include/rvmyth_gen.v - diff]
verilog/rtl/include/sandpiper.vh[Renamed from verilog/include/sandpiper.vh - diff]
verilog/rtl/include/sandpiper_gen.vh[Renamed from verilog/include/sandpiper_gen.vh - diff]
verilog/rtl/include/sp_default.vh[Renamed from verilog/include/sp_default.vh - diff]
verilog/rtl/include/sp_verilog.vh[Renamed from verilog/include/sp_verilog.vh - diff]
verilog/rtl/sram_32_256_sky130A.v[diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

45 files changed

tree: d181833760f60d6a408352085d489c86b2f9e356

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.