- ef957a6 Updated the documentation to reflect the changes made to the source by Tim Edwards · 3 years, 9 months ago
- c89cfac Update to coincide with the most recent commit to the caravel by Tim Edwards · 3 years, 9 months ago
- 340cc4a Update full chip simulation to run from root by manarabdelaty · 3 years, 9 months ago
- 4bbff2e Update README.md by Manar · 3 years, 9 months ago
- b41301c Added top level makefile by manarabdelaty · 3 years, 9 months ago
- 22f3cd0 Submodule caravel-lite by manarabdelaty · 3 years, 9 months ago
- c0f458a Update DV Makefile by manarabdelaty · 3 years, 9 months ago
- eac56e8 Rename CARAVEL_MASTER -> CARAVEL_ROOT by manarabdelaty · 3 years, 9 months ago
- 8dbabc1 Update DV Makefiles by manarabdelaty · 3 years, 9 months ago
- 8e8bf63 Update la_test2 Makefile by manarabdelaty · 3 years, 9 months ago
- 496112a Add CARAVEL_PATH for the testbenches by manarabdelaty · 3 years, 9 months ago
- f989c64 Corrected the user_project_wrapper verilog to have the correct by Tim Edwards · 3 years, 9 months ago
- a7929f3 Added mprj_stimulus test by manarabdelaty · 3 years, 9 months ago
- d184bf6 Update wb_port dv makefile by manarabdelaty · 3 years, 9 months ago
- a63e2e6 Makefile and RTL updates to run GL sim by manarabdelaty · 3 years, 9 months ago
- 10b3a10 Update README.md by Manar · 3 years, 9 months ago
- 69bd326 Updated DV tests by manarabdelaty · 3 years, 9 months ago
- d4ec2f0 Example of a full run of user_project_wrapper by Ahmed Ghazy · 3 years, 9 months ago