commit: d4ec2f0d93b90182cf84c8b545818b2176d1ed9a
[log] [tgz]
author: Ahmed Ghazy <ax3ghazy@aucegypt.edu>
Mon Apr 05 18:32:10 2021 +0200
committer: Ahmed Ghazy <ax3ghazy@aucegypt.edu>
Mon Apr 05 18:32:10 2021 +0200
tree: cb1db91caa2bc46bc9df9eed75a8db6e5ec88219
parent: 2f8702ecde470d675960c2a6f98ef6aa688e6899 [diff]

Example of a full run of user_project_wrapper

Makefile[Added - diff]
def/user_proj_example.def[Added - diff]
def/user_project_wrapper.def[Added - diff]
gds/user_proj_example.gds.gz[Added - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/user_proj_example.lef[Added - diff]
lef/user_project_wrapper.lef[Added - diff]
mag/user_proj_example.mag[Added - diff]
mag/user_project_wrapper.mag[Added - diff]
maglef/user_proj_example.mag[Added - diff]
maglef/user_project_wrapper.mag[Added - diff]
openlane/.gitignore[Added - diff]
openlane/Makefile[Added - diff]
openlane/user_proj_example/config.tcl[Added - diff]
openlane/user_proj_example/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[Added - diff]
signoff/user_proj_example/PDK_SOURCES[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[Added - diff]
spi/lvs/user_proj_example.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[Added - diff]
verilog/dv/user_proj_example/Makefile[Added - diff]
verilog/dv/user_proj_example/README.md[Added - diff]
verilog/dv/user_proj_example/io_ports/Makefile[Added - diff]
verilog/dv/user_proj_example/io_ports/io_ports.c[Added - diff]
verilog/dv/user_proj_example/io_ports/io_ports_tb.v[Added - diff]
verilog/dv/user_proj_example/la_test1/Makefile[Added - diff]
verilog/dv/user_proj_example/la_test1/la_test1.c[Added - diff]
verilog/dv/user_proj_example/la_test1/la_test1_tb.v[Added - diff]
verilog/dv/user_proj_example/la_test2/Makefile[Added - diff]
verilog/dv/user_proj_example/la_test2/la_test2.c[Added - diff]
verilog/dv/user_proj_example/la_test2/la_test2_tb.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
verilog/gl/user_project_wrapper.v[Added - diff]
verilog/rtl/user_proj_example.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]

39 files changed

tree: cb1db91caa2bc46bc9df9eed75a8db6e5ec88219

README.md

Caravel Project Example