| --- |
| project: |
| description: "Elpis is a 5-stage pipelined and multi-cycle processor implemented from scratch based on RISC-V architecture, mixed with some MIPS ideas." |
| foundry: "SkyWater" |
| git_url: "https://github.com/theatomb/Elpis-Light-MPW3.git" |
| organization: "Universitat Politecnica de Catalunya (UPC)" |
| organization_url: "https://www.upc.edu" |
| owner: "Rodrigo Huerta and Aurora Tomas" |
| process: "SKY130" |
| project_name: "Elpis-Light-MPW3" |
| project_id: "00000000" |
| tags: |
| - "Open MPW" |
| - "MPW-3" |
| - "CPU" |
| - "RISC-V" |
| - "MIPS" |
| category: "Test Harness" |
| top_level_netlist: "caravel/verilog/gl/caravel.v" |
| user_level_netlist: "verilog/gl/user_project_wrapper.v" |
| version: "1.00" |
| cover_image: "docs/source/_static/caravel_harness.png" |
