removed most slew violations in the core, only 2 remaining

openlane/core/config.tcl

diff --git a/openlane/core/config.tcl b/openlane/core/config.tcl
index d74216f..64642e0 100755
--- a/openlane/core/config.tcl
+++ b/openlane/core/config.tcl
@@ -51,8 +51,7 @@
 set ::env(PL_TARGET_DENSITY) 0.24
 set ::env(FP_CORE_UTIL) "50"
 
-#set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
-
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 50
 
 # Maximum layer used for routing is metal 4.
 # This is because this macro will be inserted in a top level (user_project_wrapper) 
@@ -70,15 +69,8 @@
 
 set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) "0.3"
 set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) "0.3"
-# set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) "30"
-# set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) "30"
-# set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) "30"
-# set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
-# set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) 1
 
-# set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_2"
-# set ::env(SYNTH_STRATEGY) "AREA 2" 
-# default 2
+set ::env(SYNTH_STRATEGY) "DELAY 2" 
 # set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 
 # set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0