printing test compiles but still fails
diff --git a/verilog/dv/testPrint/testPrint.c b/verilog/dv/testPrint/testPrint.c index 6d66398..a903817 100644 --- a/verilog/dv/testPrint/testPrint.c +++ b/verilog/dv/testPrint/testPrint.c
@@ -227,7 +227,7 @@ while (reg_la3_data != 0x00000010); // Check bit 100 has the right data - if (reg_la3_data == 0x00000002){ + if (reg_wb_reads == 0x00000002){ print("OK\n\n"); } else{
diff --git a/verilog/dv/testPrint/testPrint.hex b/verilog/dv/testPrint/testPrint.hex index 661f102..50bd111 100755 --- a/verilog/dv/testPrint/testPrint.hex +++ b/verilog/dv/testPrint/testPrint.hex
@@ -122,13 +122,13 @@ BA 85 3E 85 3D 34 B7 07 00 25 13 87 C7 02 85 47 1C C3 37 07 00 25 71 07 1C C3 B7 07 00 25 B1 07 09 47 98 C3 B7 07 00 25 B1 07 23 A0 07 00 01 00 -B7 07 00 25 B1 07 98 43 C1 47 E3 1B F7 FE B7 07 -00 25 B1 07 98 43 89 47 63 18 F7 00 B7 17 00 10 -13 85 C7 81 65 32 31 A0 B7 17 00 10 13 85 47 82 -71 3A B7 07 00 26 B1 07 37 07 41 AB 98 C3 B7 17 -00 10 13 85 C7 82 59 32 B7 17 00 10 13 85 07 83 -B5 3A B7 07 00 26 B1 07 37 07 51 AB 98 C3 01 00 -83 20 C1 11 03 24 81 11 15 61 82 80 4F 4B 0A 0A +B7 07 00 25 B1 07 98 43 C1 47 E3 1B F7 FE B7 17 +00 30 98 43 89 47 63 18 F7 00 B7 17 00 10 13 85 +C7 81 6D 32 31 A0 B7 17 00 10 13 85 47 82 79 3A +B7 07 00 26 B1 07 37 07 41 AB 98 C3 B7 17 00 10 +13 85 C7 82 61 32 B7 17 00 10 13 85 07 83 BD 3A +B7 07 00 26 B1 07 37 07 51 AB 98 C3 01 00 83 20 +C1 11 03 24 81 11 15 61 82 80 00 00 4F 4B 0A 0A 00 00 00 00 45 52 52 4F 52 0A 0A 00 0A 00 00 00 4D 6F 6E 69 74 6F 72 3A 20 54 65 73 74 20 31 20 50 61 73 73 65 64 0A 0A 00 00 00 00
diff --git a/verilog/dv/testPrint/testPrint_tb.v b/verilog/dv/testPrint/testPrint_tb.v index fb082e9..f9247cb 100644 --- a/verilog/dv/testPrint/testPrint_tb.v +++ b/verilog/dv/testPrint/testPrint_tb.v
@@ -59,7 +59,7 @@ `ifdef GL $display ("Monitor: Timeout, Test Output (print) to Elpis (GL) Failed"); `else - $display ("Monitor: Timeout, Test Output (print) to Elpis(RTL) Failed"); + $display ("Monitor: Timeout, Test Output (print) to Elpis (RTL) Failed"); `endif $display("%c[0m",27); $finish; @@ -67,8 +67,8 @@ initial begin $display("Test 1 (Output (print) to Elpis) started"); - wait(testPrint_tb.uut.mprj.la_data_out[100] == 1); - wait(testPrint_tb.uut.mprj.wb_dat_o == 2); + wait(testPrint_tb.uut.mprj.la_data_out[100] == 1'b1); + wait(testPrint_tb.uut.mprj.wbs_dat_o == 'd2); $display("%c[1;32m",27); $display("Test 1 (Output (print) to Elpis) Finished correctly"); $display("%c[0m",27);