verilog/dv/testIn/preview.gtkw

[*]
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Fri Nov  5 09:20:23 2021
[*]
[dumpfile] "/home/rodhuega/Elpis-Light-MPW3/verilog/dv/testIn/testIn.vcd"
[dumpfile_mtime] "Fri Nov  5 08:58:10 2021"
[dumpfile_size] 2121784546
[savefile] "/home/rodhuega/Elpis-Light-MPW3/verilog/dv/testIn/preview.gtkw"
[timestart] 2380528000
[size] 3000 1862
[pos] -77 -77
*-15.000000 2380686200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] testIn_tb.
[treeopen] testIn_tb.uut.
[treeopen] testIn_tb.uut.mprj.
[treeopen] testIn_tb.uut.mprj.core0.
[treeopen] testIn_tb.uut.mprj.core0.datapath.
[sst_width] 388
[signals_width] 801
[sst_expanded] 1
[sst_vpaned_height] 558
@28
testIn_tb.uut.mprj.sram_wrapper.clk
testIn_tb.uut.mprj.sram_wrapper.is_loading_memory_into_core
@200
-I_arbiter
@28
testIn_tb.uut.mprj.io_input_arbiter.arb_state[1:0]
@22
testIn_tb.uut.mprj.io_input_arbiter.data_out[31:0]
@28
testIn_tb.uut.mprj.io_input_arbiter.is_ready_core0
testIn_tb.uut.mprj.io_input_arbiter.next_arb_state[1:0]
testIn_tb.uut.mprj.io_input_arbiter.read_enable
@22
testIn_tb.uut.mprj.io_input_arbiter.read_value[31:0]
@28
testIn_tb.uut.mprj.io_input_arbiter.req_core0
@200
-Core
@22
testIn_tb.uut.mprj.core0.datapath.f_inst[31:0]
testIn_tb.uut.mprj.core0.datapath.pc[31:0]
@200
-SpecialReg
@23
testIn_tb.uut.mprj.core0.datapath.specialreg.\rm[0][31:0]
testIn_tb.uut.mprj.core0.datapath.specialreg.\rm[1][31:0]
testIn_tb.uut.mprj.core0.datapath.specialreg.\rm[2][31:0]
testIn_tb.uut.mprj.core0.datapath.specialreg.\rm[3][31:0]
testIn_tb.uut.mprj.core0.datapath.specialreg.\rm[4][31:0]
@200
-Regfile
@22
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[0][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[1][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[2][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[3][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[4][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[5][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[6][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[7][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[8][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[9][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[10][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[11][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[12][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[13][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[14][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[15][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[16][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[17][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[18][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[19][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[20][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[21][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[22][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[23][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[24][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[25][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[26][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[27][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[28][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[29][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[30][31:0]
testIn_tb.uut.mprj.core0.datapath.regfile.\registers[31][31:0]
[pattern_trace] 1
[pattern_trace] 0