printing test not working yet
diff --git a/signoff/custom_sram/final_summary_report.csv b/signoff/custom_sram/final_summary_report.csv index 714fe5b..cacf6a3 100644 --- a/signoff/custom_sram/final_summary_report.csv +++ b/signoff/custom_sram/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/custom_sram,custom_sram,custom_sram,flow_completed,0h54m31s,-1,51945.555555555555,1.8,25972.777777777777,40.1,2327.98,46751,0,0,0,0,0,0,0,30,0,0,-1,2776445,528493,-84.33,-151.49,-1,0.0,-1,-1157368.12,-2053896.75,-1,0.0,-1,1453041291.0,0.42,37.73,35.68,2.14,0.92,-1,17938,33922,520,16504,0,0,0,33866,0,0,0,0,0,0,0,4,16426,16384,10,1086,25070,0,26156,19.607843137254903,51,50,AREA 0,5,50,1,153.6,153.18,0.46,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/custom_sram,custom_sram,custom_sram,flow_completed,1h2m37s,-1,51945.555555555555,1.8,25972.777777777777,40.1,2329.77,46751,0,0,0,0,0,0,0,30,0,0,-1,2776445,528493,-84.33,-151.49,-1,0.0,-1,-1157368.12,-2053896.75,-1,0.0,-1,1453041291.0,0.42,37.73,35.68,2.14,0.92,-1,17938,33922,520,16504,0,0,0,33866,0,0,0,0,0,0,0,4,16426,16384,10,1086,25070,0,26156,19.607843137254903,51,50,AREA 0,5,50,1,153.6,153.18,0.46,0.0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/testOut/preview.gtkw b/verilog/dv/testOut/preview.gtkw deleted file mode 100644 index dca3366..0000000 --- a/verilog/dv/testOut/preview.gtkw +++ /dev/null
@@ -1,65 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI -[*] Wed Nov 3 18:30:40 2021 -[*] -[dumpfile] "/home/aurora/Elpis-Light-MPW3/verilog/dv/testOut/testOut.vcd" -[dumpfile_mtime] "Wed Nov 3 18:23:55 2021" -[dumpfile_size] 1739269985 -[savefile] "/home/aurora/Elpis-Light-MPW3/verilog/dv/testOut/preview.gtkw" -[timestart] 2048896900 -[size] 2560 1466 -[pos] -77 -77 -*-17.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] testOut_tb. -[treeopen] testOut_tb.uut. -[treeopen] testOut_tb.uut.mprj. -[treeopen] testOut_tb.uut.mprj.core0. -[treeopen] testOut_tb.uut.mprj.core0.datapath. -[sst_width] 388 -[signals_width] 462 -[sst_expanded] 1 -[sst_vpaned_height] 425 -@28 -testOut_tb.uut.mprj.core0.datapath.clk -@29 -testOut_tb.uut.mprj.sram_wrapper.is_loading_memory_into_core -@22 -testOut_tb.uut.mprj.core0.datapath.pc[31:0] -testOut_tb.uut.mprj.core0.datapath.f_inst[31:0] -@200 --Regfile -@22 -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[0][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[1][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[2][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[3][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[4][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[5][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[6][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[7][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[8][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[9][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[10][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[11][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[12][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[13][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[14][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[15][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[16][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[17][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[18][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[19][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[20][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[21][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[22][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[23][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[24][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[25][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[26][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[27][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[28][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[29][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[30][31:0] -testOut_tb.uut.mprj.core0.datapath.regfile.\registers[31][31:0] -[pattern_trace] 1 -[pattern_trace] 0
diff --git a/verilog/dv/testOut/Makefile b/verilog/dv/testPrint/Makefile similarity index 99% rename from verilog/dv/testOut/Makefile rename to verilog/dv/testPrint/Makefile index f4884ce..7659d1e 100644 --- a/verilog/dv/testOut/Makefile +++ b/verilog/dv/testPrint/Makefile
@@ -40,7 +40,7 @@ .SUFFIXES: -PATTERN = testOut +PATTERN = testPrint all: ${PATTERN:=.vcd}
diff --git a/verilog/dv/testPrint/preview.gtkw b/verilog/dv/testPrint/preview.gtkw new file mode 100644 index 0000000..6de4a62 --- /dev/null +++ b/verilog/dv/testPrint/preview.gtkw
@@ -0,0 +1,65 @@ +[*] +[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI +[*] Wed Nov 3 18:30:40 2021 +[*] +[dumpfile] "/home/aurora/Elpis-Light-MPW3/verilog/dv/testPrint/testPrint.vcd" +[dumpfile_mtime] "Wed Nov 3 18:23:55 2021" +[dumpfile_size] 1739269985 +[savefile] "/home/aurora/Elpis-Light-MPW3/verilog/dv/testPrint/preview.gtkw" +[timestart] 2048896900 +[size] 2560 1466 +[pos] -77 -77 +*-17.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] testPrint_tb. +[treeopen] testPrint_tb.uut. +[treeopen] testPrint_tb.uut.mprj. +[treeopen] testPrint_tb.uut.mprj.core0. +[treeopen] testPrint_tb.uut.mprj.core0.datapath. +[sst_width] 388 +[signals_width] 462 +[sst_expanded] 1 +[sst_vpaned_height] 425 +@28 +testPrint_tb.uut.mprj.core0.datapath.clk +@29 +testPrint_tb.uut.mprj.sram_wrapper.is_loading_memory_into_core +@22 +testPrint_tb.uut.mprj.core0.datapath.pc[31:0] +testPrint_tb.uut.mprj.core0.datapath.f_inst[31:0] +@200 +-Regfile +@22 +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[0][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[1][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[2][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[3][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[4][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[5][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[6][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[7][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[8][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[9][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[10][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[11][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[12][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[13][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[14][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[15][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[16][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[17][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[18][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[19][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[20][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[21][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[22][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[23][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[24][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[25][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[26][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[27][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[28][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[29][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[30][31:0] +testPrint_tb.uut.mprj.core0.datapath.regfile.\registers[31][31:0] +[pattern_trace] 1 +[pattern_trace] 0
diff --git a/verilog/dv/testOut/testOut.c b/verilog/dv/testPrint/testPrint.c similarity index 92% rename from verilog/dv/testOut/testOut.c rename to verilog/dv/testPrint/testPrint.c index ce27d4f..6d66398 100644 --- a/verilog/dv/testOut/testOut.c +++ b/verilog/dv/testPrint/testPrint.c
@@ -19,6 +19,9 @@ #include "verilog/dv/caravel/defs.h" #include "verilog/dv/caravel/stub.c" +#define reg_wb_register (*(volatile uint32_t*)0x30100010) +#define reg_wb_reads (*(volatile uint32_t*)0x30001000) + void elpis_load_memory(uint32_t* program_data, uint32_t* program_addr) { @@ -197,25 +200,17 @@ OS_ADDR[29] = 0xFFFFFFFF; // Elpis user program - uint32_t USER_DATA[8]; - USER_DATA[0] = 0x00002203; - USER_DATA[1] = 0x004202B3; - USER_DATA[2] = 0x0041E1B3; - USER_DATA[3] = 0x00418333; - USER_DATA[4] = 0x0041F3B3; - USER_DATA[5] = 0x00334433; - USER_DATA[6] = 0x00000003; - USER_DATA[7] = 0xFFFFFFFF; + uint32_t USER_DATA[4]; + USER_DATA[0] = 0x00200093; + USER_DATA[1] = 0x0210022F; + USER_DATA[2] = 0x00600073; + USER_DATA[3] = 0xFFFFFFFF; - uint32_t USER_ADDR[8]; + uint32_t USER_ADDR[4]; USER_ADDR[0] = 0x00000040; USER_ADDR[1] = 0x00000041; USER_ADDR[2] = 0x00000042; - USER_ADDR[3] = 0x00000043; - USER_ADDR[4] = 0x00000044; - USER_ADDR[5] = 0x00000045; - USER_ADDR[6] = 0x00000100; - USER_ADDR[7] = 0xFFFFFFFF; + USER_ADDR[3] = 0xFFFFFFFF; // Loading elpis memory @@ -228,6 +223,17 @@ reg_la3_data = 0x00000002; reg_la3_data = 0x00000000; + // Check bit 100 to be active + while (reg_la3_data != 0x00000010); + + // Check bit 100 has the right data + if (reg_la3_data == 0x00000002){ + print("OK\n\n"); + } + else{ + print("ERROR\n\n"); + } + reg_mprj_datal = 0xAB410000; print("\n"); print("Monitor: Test 1 Passed\n\n"); // Makes simulation very long!
diff --git a/verilog/dv/testOut/testOut.hex b/verilog/dv/testPrint/testPrint.hex similarity index 83% rename from verilog/dv/testOut/testOut.hex rename to verilog/dv/testPrint/testPrint.hex index 85a869f..661f102 100755 --- a/verilog/dv/testOut/testOut.hex +++ b/verilog/dv/testPrint/testPrint.hex
@@ -6,7 +6,7 @@ 13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 -13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 85 7D +13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 7D 93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE C1 22 @@ -37,8 +37,8 @@ 00 25 B1 07 15 47 98 C3 B7 07 00 25 B1 07 11 47 98 C3 83 27 C4 FE 85 07 23 26 F4 FE 83 27 84 FE C9 FF B7 07 00 25 B1 07 05 47 98 C3 B7 07 00 25 -B1 07 23 A0 07 00 01 00 32 54 45 61 82 80 29 71 -23 2E 11 12 23 2C 81 12 80 02 B7 07 00 24 29 67 +B1 07 23 A0 07 00 01 00 32 54 45 61 82 80 2D 71 +23 2E 11 10 23 2C 81 10 00 12 B7 07 00 24 29 67 09 07 98 C3 B7 07 00 26 93 87 07 0A 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 C7 09 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 87 09 09 67 13 07 @@ -113,22 +113,22 @@ 70 02 23 2E F4 F4 93 07 80 02 23 20 F4 F6 93 07 90 02 23 22 F4 F6 93 07 A0 02 23 24 F4 F6 93 07 B0 02 23 26 F4 F6 95 47 23 28 F4 F6 FD 57 23 2A -F4 F6 89 67 93 87 37 20 23 20 F4 EE B7 07 42 00 -93 87 37 2B 23 22 F4 EE B7 E7 41 00 93 87 37 1B -23 24 F4 EE B7 87 41 00 93 87 37 33 23 26 F4 EE -B7 F7 41 00 93 87 37 3B 23 28 F4 EE B7 47 33 00 -93 87 37 43 23 2A F4 EE 8D 47 23 2C F4 EE FD 57 -23 2E F4 EE 93 07 00 04 23 20 F4 EC 93 07 10 04 -23 22 F4 EC 93 07 20 04 23 24 F4 EC 93 07 30 04 -23 26 F4 EC 93 07 40 04 23 28 F4 EC 93 07 50 04 -23 2A F4 EC 93 07 00 10 23 2C F4 EC FD 57 23 2E -F4 EC 13 07 04 F0 93 07 84 F7 BA 85 3E 85 D5 3A -13 07 04 EC 93 07 04 EE BA 85 3E 85 DD 32 B7 07 -00 25 13 87 C7 02 85 47 1C C3 37 07 00 25 71 07 -1C C3 B7 07 00 25 B1 07 09 47 98 C3 B7 07 00 25 -B1 07 23 A0 07 00 B7 07 00 26 B1 07 37 07 41 AB -98 C3 B7 17 00 10 13 85 07 83 8D 3A B7 17 00 10 -13 85 47 83 A5 32 B7 07 00 26 B1 07 37 07 51 AB -98 C3 01 00 83 20 C1 13 03 24 81 13 31 61 82 80 -0A 00 00 00 4D 6F 6E 69 74 6F 72 3A 20 54 65 73 -74 20 31 20 50 61 73 73 65 64 0A 0A 00 00 00 00 +F4 F6 B7 07 20 00 93 87 37 09 23 28 F4 EE B7 07 +10 02 93 87 F7 22 23 2A F4 EE B7 07 60 00 93 87 +37 07 23 2C F4 EE FD 57 23 2E F4 EE 93 07 00 04 +23 20 F4 EE 93 07 10 04 23 22 F4 EE 93 07 20 04 +23 24 F4 EE FD 57 23 26 F4 EE 13 07 04 F0 93 07 +84 F7 BA 85 3E 85 35 3C 13 07 04 EE 93 07 04 EF +BA 85 3E 85 3D 34 B7 07 00 25 13 87 C7 02 85 47 +1C C3 37 07 00 25 71 07 1C C3 B7 07 00 25 B1 07 +09 47 98 C3 B7 07 00 25 B1 07 23 A0 07 00 01 00 +B7 07 00 25 B1 07 98 43 C1 47 E3 1B F7 FE B7 07 +00 25 B1 07 98 43 89 47 63 18 F7 00 B7 17 00 10 +13 85 C7 81 65 32 31 A0 B7 17 00 10 13 85 47 82 +71 3A B7 07 00 26 B1 07 37 07 41 AB 98 C3 B7 17 +00 10 13 85 C7 82 59 32 B7 17 00 10 13 85 07 83 +B5 3A B7 07 00 26 B1 07 37 07 51 AB 98 C3 01 00 +83 20 C1 11 03 24 81 11 15 61 82 80 4F 4B 0A 0A +00 00 00 00 45 52 52 4F 52 0A 0A 00 0A 00 00 00 +4D 6F 6E 69 74 6F 72 3A 20 54 65 73 74 20 31 20 +50 61 73 73 65 64 0A 0A 00 00 00 00
diff --git a/verilog/dv/testOut/testOut_tb.v b/verilog/dv/testPrint/testPrint_tb.v similarity index 77% rename from verilog/dv/testOut/testOut_tb.v rename to verilog/dv/testPrint/testPrint_tb.v index 2f75e93..fb082e9 100644 --- a/verilog/dv/testOut/testOut_tb.v +++ b/verilog/dv/testPrint/testPrint_tb.v
@@ -23,7 +23,7 @@ `include "spiflash.v" `include "tbuart.v" -module testOut_tb; +module testPrint_tb; reg clock; reg RSTB; reg CSB; @@ -47,8 +47,8 @@ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; initial begin - $dumpfile("testOut.vcd"); - $dumpvars(0, testOut_tb); + $dumpfile("testPrint.vcd"); + $dumpvars(0, testPrint_tb); // TIP. Increase the first repeat number until it is needed // Repeat cycles of 1000 clock edges as needed to complete testbench repeat (100) begin @@ -57,24 +57,20 @@ end $display("%c[1;31m",27); `ifdef GL - $display ("Monitor: Timeout, Test LA (GL) Failed"); + $display ("Monitor: Timeout, Test Output (print) to Elpis (GL) Failed"); `else - $display ("Monitor: Timeout, Test LA (RTL) Failed"); + $display ("Monitor: Timeout, Test Output (print) to Elpis(RTL) Failed"); `endif $display("%c[0m",27); $finish; end initial begin - $display("Test 1 (Basic Ops) started"); - wait(testOut_tb.uut.mprj.core0.datapath.regfile.registers[3] == 3); - wait(testOut_tb.uut.mprj.core0.datapath.regfile.registers[4] == 3); - wait(testOut_tb.uut.mprj.core0.datapath.regfile.registers[5] == 6); - wait(testOut_tb.uut.mprj.core0.datapath.regfile.registers[6] == 6); - wait(testOut_tb.uut.mprj.core0.datapath.regfile.registers[7] == 3); - wait(testOut_tb.uut.mprj.core0.datapath.regfile.registers[8] == 5); + $display("Test 1 (Output (print) to Elpis) started"); + wait(testPrint_tb.uut.mprj.la_data_out[100] == 1); + wait(testPrint_tb.uut.mprj.wb_dat_o == 2); $display("%c[1;32m",27); - $display("Test 1 (Basic Ops) Finished correctly"); + $display("Test 1 (Output (print) to Elpis) Finished correctly"); $display("%c[0m",27); #1; $finish; @@ -84,14 +80,14 @@ integer i_mem; initial begin for (i_mem = 0; i_mem < 512; i_mem = i_mem + 1) begin - $dumpvars(0, testOut_tb.uut.mprj.custom_sram.mem[i_mem]); + $dumpvars(0, testPrint_tb.uut.mprj.custom_sram.mem[i_mem]); end end integer i_reg; initial begin for (i_reg = 0; i_reg < 32; i_reg = i_reg + 1) begin - $dumpvars(0, testOut_tb.uut.mprj.core0.datapath.regfile.registers[i_reg]); + $dumpvars(0, testPrint_tb.uut.mprj.core0.datapath.regfile.registers[i_reg]); end end @@ -152,7 +148,7 @@ ); spiflash #( - .FILENAME("testOut.hex") + .FILENAME("testPrint.hex") ) spiflash ( .csb(flash_csb), .clk(flash_clk),