commit	46bbb3893e9042f3db068f023a835c5d58a4355e	[log] [tgz]
author	Rodrigo Huerta <rodrigodenia@gmail.com>	Fri Oct 29 19:59:13 2021 +0200
committer	Rodrigo Huerta <rodrigodenia@gmail.com>	Fri Oct 29 19:59:13 2021 +0200
tree	c2c15ebd7a97871b45fe65c0f327a8ca06c6fcc4
parent	fced76b127e960f91cf9e32c1b60614f678d23be [diff]

Added rtl and macros configuration

caravel[Added - diff]
def/arbiter.def[Added - diff]
lef/arbiter.lef[Added - diff]
openlane/EX_MEM/config.tcl[Added - diff]
openlane/ID_EX/config.tcl[Added - diff]
openlane/IF_ID/config.tcl[Added - diff]
openlane/MEM_WB/config.tcl[Added - diff]
openlane/TLBAddressAdder/config.tcl[Added - diff]
openlane/alu/config.tcl[Added - diff]
openlane/arbiter/config.tcl[Added - diff]
openlane/branchComparer/config.tcl[Added - diff]
openlane/cache/config.tcl[Added - diff]
openlane/controlunit/config.tcl[Added - diff]
openlane/core/config.tcl[Added - diff]
openlane/core/pin_order.cfg[Added - diff]
openlane/datapath/config.tcl[Added - diff]
openlane/forwardingunit/config.tcl[Added - diff]
openlane/forwardingunit_st/config.tcl[Added - diff]
openlane/hazardDetectionUnit/config.tcl[Added - diff]
openlane/i_arbiter/config.tcl[Added - diff]
openlane/i_arbiter/pin_order.cfg[Added - diff]
openlane/memory/config.tcl[Added - diff]
openlane/memory/macro.cfg[Added - diff]
openlane/memory/pin_order.cfg[Added - diff]
openlane/mux3_1/config.tcl[Added - diff]
openlane/o_arbiter/config.tcl[Added - diff]
openlane/o_arbiter/pin_order.cfg[Added - diff]
openlane/regfile/config.tcl[Added - diff]
openlane/specialreg/config.tcl[Added - diff]
openlane/storeBuffer/config.tcl[Added - diff]
openlane/tlb/config.tcl[Added - diff]
openlane/user_proj_example/config.tcl[diff]
openlane/user_proj_example/macro.cfg[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/pin_order.cfg[diff]
signoff/arbiter/OPENLANE_VERSION[Added - diff]
signoff/arbiter/PDK_SOURCES[Added - diff]
signoff/arbiter/final_summary_report.csv[Added - diff]
spi/lvs/arbiter.spice[Added - diff]
verilog/dv/testOut/Makefile[Added - diff]
verilog/dv/testOut/preview.gtkw[Added - diff]
verilog/dv/testOut/testOut.c[Added - diff]
verilog/dv/testOut/testOut.hex[Added - diff]
verilog/dv/testOut/testOut_tb.v[Added - diff]
verilog/gl/arbiter.v[Added - diff]
verilog/rtl/elpis/IO_arbiter.v[Added - diff]
verilog/rtl/elpis/alu.v[Added - diff]
verilog/rtl/elpis/arbiter.v[Added - diff]
verilog/rtl/elpis/betweenStages.v[Added - diff]
verilog/rtl/elpis/branchComparer.v[Added - diff]
verilog/rtl/elpis/cache.v[Added - diff]
verilog/rtl/elpis/controlunit.v[Added - diff]
verilog/rtl/elpis/core.v[Added - diff]
verilog/rtl/elpis/datapath.v[Added - diff]
verilog/rtl/elpis/decoder.v[Added - diff]
verilog/rtl/elpis/definitions.v[Added - diff]
verilog/rtl/elpis/forwardingunit.v[Added - diff]
verilog/rtl/elpis/hazardDetectionUnit.v[Added - diff]
verilog/rtl/elpis/memory.v[Added - diff]
verilog/rtl/elpis/regfile.v[Added - diff]
verilog/rtl/elpis/specialreg.v[Added - diff]
verilog/rtl/elpis/sram_32_1024_sky130.v[Added - diff]
verilog/rtl/elpis/storebuffer.v[Added - diff]
verilog/rtl/elpis/tlb.v[Added - diff]
verilog/rtl/elpis/top.v[Added - diff]
verilog/rtl/elpis/utils.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]

67 files changed

tree: c2c15ebd7a97871b45fe65c0f327a8ca06c6fcc4

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.