Update Makefile to work with efabless style
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile index e3560d7..5237a05 100644 --- a/verilog/dv/io_ports/Makefile +++ b/verilog/dv/io_ports/Makefile
@@ -35,6 +35,7 @@ GCC_PREFIX?=riscv32-unknown-elf ## Simulation mode: RTL/GL +SIM_DEFINES = -DFUNCTIONAL -DSIM SIM?=RTL .SUFFIXES: @@ -47,12 +48,12 @@ %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) - iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ $< -o $@ else - iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ $< -o $@ @@ -82,6 +83,10 @@ ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) endif +# check for efabless style installation +ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) +SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE +endif # ---- Clean ----
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile index 14d6ee6..ba979f7 100644 --- a/verilog/dv/la_test1/Makefile +++ b/verilog/dv/la_test1/Makefile
@@ -33,9 +33,9 @@ ## RISCV GCC GCC_PATH?=/ef/apps/bin GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL +SIM_DEFINES = -DFUNCTIONAL -DSIM SIM?=RTL .SUFFIXES: @@ -48,12 +48,12 @@ %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) - iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ $< -o $@ else - iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ $< -o $@ @@ -83,6 +83,10 @@ ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) endif +# check for efabless style installation +ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) +SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE +endif # ---- Clean ----
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile index 46f127b..0435500 100644 --- a/verilog/dv/la_test2/Makefile +++ b/verilog/dv/la_test2/Makefile
@@ -35,6 +35,7 @@ GCC_PREFIX?=riscv32-unknown-elf ## Simulation mode: RTL/GL +SIM_DEFINES = -DFUNCTIONAL -DSIM SIM?=RTL .SUFFIXES: @@ -47,12 +48,12 @@ %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) - iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ $< -o $@ else - iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ $< -o $@ @@ -82,6 +83,10 @@ ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) endif +# check for efabless style installation +ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) +SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE +endif # ---- Clean ----
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile index 72818e3..3a73b99 100644 --- a/verilog/dv/mprj_stimulus/Makefile +++ b/verilog/dv/mprj_stimulus/Makefile
@@ -35,6 +35,7 @@ GCC_PREFIX?=riscv32-unknown-elf ## Simulation mode: RTL/GL +SIM_DEFINES = -DFUNCTIONAL -DSIM SIM?=RTL .SUFFIXES: @@ -47,12 +48,12 @@ %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) - iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ $< -o $@ else - iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ $< -o $@ @@ -82,6 +83,10 @@ ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) endif +# check for efabless style installation +ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) +SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE +endif # ---- Clean ----
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index 27c9715..1c784c6 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -35,6 +35,7 @@ GCC_PREFIX?=riscv32-unknown-elf ## Simulation mode: RTL/GL +SIM_DEFINES = -DFUNCTIONAL -DSIM SIM?=RTL .SUFFIXES: @@ -47,12 +48,12 @@ %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) - iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ $< -o $@ else - iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ $< -o $@ @@ -82,6 +83,10 @@ ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) endif +# check for efabless style installation +ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) +SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE +endif # ---- Clean ----