commit: bfb72c90150b11fd6c15953385fcf97840b31374
[log]
author: Dhayalakumar <61288836+dhayalakumarm@users.noreply.github.com>
Wed Oct 20 20:35:55 2021 +0530
committer: GitHub <noreply@github.com>
Wed Oct 20 20:35:55 2021 +0530
tree: 85281a7e1d40c72010d9c8caa6a673363f59be85
parent: a5a3d248437ab96b603c5598f78e8a51a342c2fe [diff]

Add files via upload

verilog/dv/io_ports/Makefile[Added - diff]
verilog/dv/io_ports/io_ports.c[Added - diff]
verilog/dv/io_ports/io_ports.hex[Added - diff]
verilog/dv/io_ports/io_ports_tb.v[Added - diff]

4 files changed

tree: 85281a7e1d40c72010d9c8caa6a673363f59be85

README.md

Caravel User Project

18 bit Adder